JPH0221694B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse delay method and apparatus for delaying an input pulse by a predetermined time and outputting the delayed pulse.

The conventional pulse delay device consists of an input terminal 1, a flip-flop circuit 2, a clock pulse generator 3, a gate circuit 4, a down counter 5, a differentiator circuit 6, and an output terminal 7, as shown in FIG. Thus, the delay time setting section 5A of the down counter 5 sets the delay time in the down counter 5 as a digital number. In such a pulse delay device, when an input pulse is applied to an input terminal 1 and inputted to a flip-flop circuit 2, the flip-flop circuit 2 is turned on and its output is applied to a differentiating circuit 6 and a gate circuit 4.
Since the differentiating circuit 6 is designed to output a delayed output pulse at the fall of the output of the flip-flop circuit 2, it does not output an output pulse at this point. When the gate circuit 4 receives a signal from the flip-flop circuit 2, it passes the clock pulse from the clock signal generator 3. The clock pulse that has passed through the gate circuit 4 is applied to the down counter 5 as a subtraction input. When a clock pulse is inputted to the down counter 5 for the number of delay times set and the difference becomes zero, that is, when the set delay time elapses, an output pulse is output from the down counter 5 to the flip-flop circuit 2, and the output pulse is output from the down counter 5 to the flip-flop circuit 2. The output of 2 becomes zero. As a result, the gate of the gate circuit 4 closes to prevent the passage of the clock pulse, and the differentiating circuit 6 outputs a delayed output pulse at the fall of the output of the flip-flop circuit 2.

Recently, there has been a demand for a pulse delay device that can take a delay time longer than the repetition time of an input pulse.

However, the pulse delay device having the structure shown in FIG. 1 has the disadvantage that it cannot take a delay time longer than the repetition time of the input pulse. Furthermore, in the device shown in FIG. 1, in order to widen the delay time range, it is necessary to increase the number of bits in the down counter 5, which has the disadvantage that it tends to cause variations in the delay time. be.

SUMMARY OF THE INVENTION An object of the present invention is to provide a pulse delay method and apparatus that can take a delay time longer than the input pulse repetition time without increasing the number of bits in the counter.

In the pulse delay method according to the present invention, the number of delay time settings T is divided into the number of sparse delay time settings T _s and the number of fine delay time settings.
T _n and specify the number of write addresses A _W of the storage device based on the sparse delay time setting number T _s ,
The number of write memories formed based on the number involved in the arrival point of input pulse P _i and the fine delay time setting number T _n is the address of the storage device specified by the number of write addresses A _W and read out the write memory number written in the storage device after a time corresponding to the sparse delay time setting number _Ts ,
The device is characterized in that a delayed output pulse is output after a time corresponding to the number of write memories from this read time.

One pulse delay device according to the present invention includes a clock pulse generator that outputs a high-frequency clock pulse P _c , and a clock pulse generator that divides the clock pulse P _c into 1/N (N is a frequency division number, an integer of 2 or more). A frequency divider that outputs a frequency-divided pulse P _b , a digital delay time T, the number of coarse delay time settings T _s , and the number of fine delay time settings T _n
A delay time setting section that divides the divided pulse into two and outputs it, and writes to the write address A _W specified for each cycle of the frequency-divided pulse P _b and from the address of the specified read address A _R. A random access memory (hereinafter referred to as RAM) that performs reading of the RAM and a random access memory (hereinafter referred to as RAM), which counts the frequency division pulse P _b with the maximum number of addresses of the RAM as the maximum count number, and uses the count number as the number of read addresses A _R of the RAM. a read address counter that specifies an address for reading, a sparse delay time setting number T _s given from the delay time setting section with the maximum number of addresses of the RAM as the maximum count number, and the number T s given from the read address counter. The sum of the number of read addresses A _R and the current number of read addresses (T _s + A _R ) is defined as the number of write addresses A _W as described above.
A write address counter that specifies a RAM write address, and a write address counter that uses the frequency division pulse P _b as a control signal to calculate the number of read addresses A _R and the number of write addresses A _W for each half cycle of the frequency division pulse. a switch that switches and supplies the RAM;
A gate control signal generator that outputs a gate control signal G ₁ during a period d ₂ from when an input pulse P _i is applied to the falling edge of the frequency _- divided pulse P _b at that time; Count the number D ₂ of the clock pulses P _c given during the period of time and subtract that number D ₂ from the frequency division number N to find the cycle of the frequency division pulse when the input pulse P _i is given. The clock pulse corresponds to a time interval d ₁ from the beginning to the time of input of the input pulse P _i
Calculate the number D ₁ of P _c and add the fine delay time setting number _{T n given} from the delay time setting section to the number D 1 to calculate the number of write memories (T _n + D ₁ ). Only when (T _n + D ₁ ) > N _, the number of sparse delay times set in the write address counter is set _.
An overflow signal is issued to increase T _s. Meanwhile, the write memory number (T _n + D ₁ ) is set to the address of the RAM of the write address number A _W (=T _s + A _R ) specified by the write address counter. A write memory counter that outputs data to be written, and a read memory counter in which the number of read addresses is increased by T _s from the number of read addresses A _R at the time of writing the number of write memories (T _{n +} D 1 ). When the number of write memories (T _n +D ₁ ) read from the RAM at the time of address number (T _s +A _R ) is given, this number of write memories is determined by the clock pulse P _c
, and a down counter that outputs a delayed output pulse P _d when the number reaches zero.

Another pulse delay device according to the present invention includes a clock pulse generator that outputs a high-frequency clock pulse P _c , and a clock pulse generator that outputs a high-frequency clock pulse P _c to 1/N (N
is a frequency division number, and outputs a frequency-divided pulse P _b whose frequency is divided into an integer of 2 or more), a frequency divider that outputs a frequency-divided pulse P b whose frequency is divided into two, and a delay time T which is a digital coarse delay time setting number T _s and a digital fine delay time setting number T _n a delay time setting section that outputs the output after two minutes;
A _{random access} memory (hereinafter _, referred to as
It is called RAM. ), the frequency division pulse P _b is counted with the maximum address number of the RAM as the maximum count number, and the count number is set as the number of read addresses.
A read address counter that specifies the read address of the RAM as A _R , and a sparse delay time setting number T _s given by the delay time setting section with the maximum number of addresses of the RAM as the maximum count number.
and the current number of read addresses A _R given from the read address counter, and the sum (T _s + A _R ) of the write address number A _W is used to specify the write address of the RAM. an address counter, and a switch that uses the frequency division pulse P _b as a control signal to switch the number of read addresses A _R and the number of write addresses A _W every half cycle of the frequency division pulse to the RAM; a gate control signal generator that outputs a gate control signal G ₁ during a period d ₂ from when the input pulse P _i is applied until the fall of the frequency-divided pulse P _b at that time;
A number obtained by counting the number _D2 of the clock pulses _Pc given during the period in which the gate control signal _G1 is output and subtracting the number _D2 from the fine delay time setting number _Tn ( _Tn - _D2 ). When T _n ≧ D ₂ , an underflow signal indicating no underflow is output, and when T _n < D ₂ , an underflow signal indicating underflow is output, and when the underflow is present. outputs (T _n - D ₂ + N) as the number of write memories, and when there is no underflow, outputs (T _n - D ₂ ) as the number of write memories, and these underflow signals and the number of write memories are Number of write addresses specified from the write address counter A _W (=T _s + A _R )
A write memory counter that is output to be written to the RAN address of , and the number of read addresses at the time when the write memory number is written.
When the number of read addresses increases by T _s from A _R (T _s + A _R ), the RAM
Given the number of write memories read from , and an underflow signal, if the underflow signal at that time means no underflow, the number of write memories read (T _n - D ₂ ) is divided by the frequency division number N. (T _n - D ₂ + N) is subtracted by the clock pulse P _c , and when the number becomes zero, the delayed output pulse P _d is output, and the underflow signal at that time means that there is an underflow. When doing so, the number of write memories read (T _n −D ₂ +N)
The present invention is characterized by comprising a down counter which subtracts the number by the clock pulse P _c and outputs a delayed output pulse when the number becomes zero.

Hereinafter, specific examples of the pulse delay device according to the present invention will be explained in detail with reference to the drawings. FIGS. 2 and 3 show a first embodiment of the present invention. In the figure, 8 is an input terminal to which an input pulse P _i is applied, 9 is a clock pulse generator that generates a high frequency clock pulse P _c , and 10 is a clock pulse P _c
1/N (N is the dividing number, an integer of 2 or more,
In this embodiment, N=64. ), and 11 is a delay time setting unit that sets the delay time as a digital _number . When the number of delay time settings is given as a digital number T, this delay time setting section 11 divides this into a digital sparse delay time setting number T _s and a digital fine delay time setting number T _n and outputs it. It's becoming like that. Here, T= _Ts + _Tn . Reference _{numeral 12} designates a random access memory ( _hereinafter referred to as
It is called RAM. ), 13 is a read address counter that counts the divided pulse P _b using the maximum address number of RAM 12 as the maximum count number, and specifies the read address of RAM 12 using the counted number A _R , 14 is the maximum address number of RAM 12 The sum of the coarse delay time setting number T _s given from the delay time setting unit 11 and the current count number A _R given from the read address counter 13 is calculated as the maximum count number (T _s + A _R ). A write address counter specifies the write address of the RAM 12 as the number of write addresses A _W , and 15 is a divided pulse P _b which uses the frequency division pulse P b as a control signal to calculate the number of read addresses A _{R and} the number of write addresses A _W.
This is a switch that switches and supplies data to the RAM 12 every half cycle. In this embodiment, the period of "0" of the divided pulse P _b of one cycle is the write period,
The period of "1" is the read period, and the write period is the output of the address counter 14 for writing to the RAM 1.
2 to designate a write address, and during a read period, the output of the read address counter 13 is supplied to the RAM 12 to designate a read address. 16 is a gate control signal generator that generates first and second gate control signals G ₁ and G ₂ based on the input pulse P _i and the frequency-divided pulse P _b . This gate control signal generator 16 controls the first gate during a period d ₂ from when the input pulse P _i is applied in a certain cycle of the frequency-divided pulse P _b to the falling edge of the frequency-divided pulse P _b in that cycle. A second gate control is performed for one cycle of the next frequency-divided pulse P _{b from the falling edge of the first gate control signal G 1 ,} that is, from the falling edge of _the frequency-divided pulse P _b in that period. It is designed to emit signal _G2 . 17 is a memory counter for writing, which counts the number _D2 of clock pulses _Pc given from the clock pulse generator 9 during the period when the first gate control signal _G1 is output from the gate control signal generating section 16; the number
Subtract D ₂ from 64 (frequency division number) to get the input pulse P _i
The cycle AB of the divided pulse P _b when is given
The input pulse from the beginning of its cycle A during
Calculate the number D ₁ of clock pulses P _c corresponding to the time interval d ₁ up to the point in time when P _i is input, and
_The number of write memories ( _{T n}
+D ₁ ). In addition, when the number of write memories (T _n +D ₁ ) exceeds the division number N, that is, 64 in this embodiment, the write memory counter 17 temporarily becomes zero and starts counting from 1 again. There is. Memory counter 1 for writing
7 outputs an overflow signal to the write address counter 14 when the number of write memories (T _n + D ₁ ) exceeds the frequency division number N, and thereby the number of write addresses in the write address counter 14 increases by 1. This ensures that no delay time is lost. Note that D ₁ and D ₂ are both numbers involved in the arrival point of input pulse P _i , and the relationship D ₁ + D ₂ = N (=64) is maintained due to changes in the arrival point of input pulse P _i . It is a number that changes in such a way that when one decreases, the other increases. 18 is the number of memories for writing (T _n +D ₁ ) during the period when the second gate control signal G ₂ is output from the gate control signal generator 16.
This is a gate circuit that allows the signal to pass through. Gate circuit 18
The number of write memories (T _n + D ₁ ) that has passed through is the RAM 12 during the write period of the divided pulse P _b at that point.
, that is, the number of write addresses specified from the write address counter 14.
It is designed to be written at the location A _W (=T _s + A _R ). Further, the RAM 12 is adapted to read from the RAM 12 at the number of read addresses A _R specified by the read address counter 13 at each time point. 19 is a down counter that subtracts the write memory number (T _n + D ₁ ) read from the RAM 12 by a clock pulse P _c , and when it becomes zero, outputs a delayed output pulse signal P _d to the output terminal 20. It's starting to come out.

Next, a pulse delay method using such a pulse delay device will be explained in detail with reference to FIGS. 2 to 4. The clock pulse generator 9 outputs _a high frequency clock pulse P _c as shown in FIG.
In other words, in this embodiment, the frequency is divided by 1/64 and outputted as a frequency-divided pulse P _b shown in FIG. 3B.

A required delay time is set as a digital number T in the delay time setting section 11. Delay time setting section 11
When the number of delay time settings T is given as a digital number, this is expressed as the number of digital sparse delay time settings T _s
and digital fine delay time setting number T _n .
In this case, the number of sparse delay time settings T _s is set to be less than or equal to the maximum number of addresses in the RAM 12 . On the other hand, the read address counter 13 counts the frequency-divided pulse P _b and supplies this as the number of read addresses A _R to the RAM 12 via the switch 15 to sequentially designate addresses for read. When the read address counter 13 reaches the maximum number of addresses in the RAM 12, its count becomes 0 and starts counting again from 1. Write address counter 14
is the number of coarse delay time settings T _s given from the delay time setting section 11 and the number of read addresses A _R given from the read address counter 13 and the sum of the numbers (T _s + A _R ) is calculated as the number for writing. Number of addresses
It is applied to the RAM 12 via the switch 15 as A _W. The switch 15 passes the write address number A _W during the "0" period of each cycle of the frequency-divided pulse P _b , and passes the read address number A _R during the "1" period. Therefore, data is stored in the RAM 12 at an address corresponding to the number of read addresses A _R for each cycle of the frequency-divided pulse P _b , as shown in FIG. Read the number of write memories, and read the number A _R
The current number of write memories A _W is written to an address where the write address number A W is greater than T _s , that is, (A _R +T _s )=A _W. The write memory number written to the write address number A _W is read because the current read is from the A _R address, so the frequency division pulse P _b is sent to the read address counter 13. This is the point when T _s pieces have been added. Therefore, after the write memory number is written, the readout is delayed by _Ts .

Now, suppose that an input pulse P _i is applied to the input terminal 8 at a certain point in time as shown in FIG. 3C. This input pulse P _i is applied to the gate control signal generator 16 . The gate control signal generator 16 receives an input pulse P _i
is applied, from the rising edge of this input pulse P _i , 1 of the divided pulse P _b to which this input pulse P _i belongs
During the period up to the fall of the cycle, the first gate control signal _G1 is generated as shown in FIG. 3D, and from the fall of the first gate control signal _G1 , the next divided pulse _Pb is During the period up to the falling edge, the second gate control signal _G2 is generated as shown in FIG. 3E.

The first gate control signal G ₁ is applied to the write memory counter 17 . first gate control signal
The write memory counter 17 that receives G ₁ counts the number D ₂ of clock pulses P _c input during the period when this first gate control signal G 1 is applied, and divides the number _{D 2 into} 64 (minutes). The number of clock pulses in one cycle of the frequency pulse is subtracted from the number of clock pulses in one cycle of the frequency pulse P _i between the cycles AB of the frequency divided pulse P _b when the input pulse P _i is applied from the beginning A of the cycle. The number D ₁ of clock pulses P _c during d ₁ up to the point in time is calculated, and the fine delay time setting number T _n given from the delay time setting section ₁₁ is added to the number D 1.
are added and output as the number of write memories (T _n + D ₁ ). Such calculation is performed using the write period of the next cycle of the frequency-divided pulse _Pb after the first gate control signal _G1 disappears. At this time, the number of write memories (T _n + D ₁ ) is the frequency division number N (=
64), an overflow signal is output from the write memory counter 17, and this causes the write address counter 14 to set the sparse delay time setting number _Ts to 1.
The number of write addresses A _W is increased by 1 to prevent partial loss of the delay time T _n . Number of write memories (T _n +
D ₁ ) is applied to the RAM 12 via the gate circuit 18 . At this time, since the second gate control signal G ₂ is applied to the gate circuit ₁₈ and the gate is open as shown in _FIG . It is done without. Noise signals are prevented from passing during the period when the second gate control signal _G2 is not applied.

The sum of the number of read addresses A _R and the number of coarse delay time settings T _s during the cycle between BC of the divided pulse P _b (A _R + T _s ) = RAM 12 corresponding to the number of write addresses A _W of A _W Write memory number (T _n +
D ₁ ) is written. At the time this writing is performed, reading from RAM 12 is as shown in Figure 4.
Since the A _R address is being read, the number of currently written write memories (T _n + D ₁ ) will be read only when T _s frequency-divided pulses P _b are input to the read address counter 13. This is the point when the count reaches (A _R + T _s ). In other words, the number of write memories (T _n + D ₁ ) is as shown in Figure 3 E.
It will be read at a cycle delayed by T _s from the cycle in which it was written. The read memory number for writing (T _n + D ₁ ) is given to the down counter 19, and this number (T _n + D ₁ ) is subtracted by the clock pulse P _c until this number (T _n + D ₁ ) becomes zero. At this point in time, a delayed pulse P _d is output at the output terminal 20 . That is, as _shown in _{FIG .}
After reading is performed, the delayed pulse P _d is output after a further delay of (T _n +D ₁ ) as shown in FIG.

As is clear from FIG _. 3 _{, this} delayed _pulse P _d is output after the input pulse _{P i is applied .} )=128+T after a time delay. This constant 128
is an unavoidable fixed delay even with a normal delay device. The time of this fixed delay is the clock pulse
It can be shortened by increasing the frequency of P _c .

FIG. 5 shows a second embodiment of the invention. The pulse delay device of this embodiment includes a write memory counter 17, a gate circuit 18, a RAM 12,
There is a feature in the down counter 19, and the other points have the same structure as the first embodiment.
The write memory counter 17 counts the number of clock pulses P _c given during the period when the first gate control signal G ₁ is output from the gate control signal generator 16.
D ₂ is counted, and the number D ₂ is subtracted from the fine delay time setting number T _n given from the delay time setting section 11 to output the number of write memories (T _n - D ₂ ). . This write memory counter 19 is
When T _n ≧ D ₂ , an underflow signal “1” is output, which means no underflow, and when T _n < D ₂ , an underflow signal “0”, which means there is an underflow, is output. ing. When there is an underflow, the write memory counter 19 divides the frequency by this number (T _n - D ₂ ) so that the number of write memories (T _n - D ₂ ) does not become negative.
64 and use this as the new number of write memories (T _n
−D ₂ +64). When there is no underflow,
The write memory counter 19 does not add the frequency division number to the write memory number (T _n −D ₂ ). The number of write memories (T _n −D ₂ ) or (T _n −D ₂ +64) output from the write memory counter 17 and the underflow signal use the period in which the second gate control signal G ₂ is present. and passes through the gate circuit 18, RAM
12, and as mentioned above, the frequency-divided pulse P _b
Number of read addresses during cycles between BCs
The sum of A _R and the number of sparse delay time settings T _s (A _R + T _s ) = A _W
Both are written to the address of the RAM 12 corresponding to the number of write addresses _AW . Number of write memories written at this point (T _n − D ₂ ) or (T _n − D ₂ + 64)
The underflow signal means that the pulse P _b divided by T _s times from the time of writing is input to the read address counter 13, delayed by T _s , and the count number becomes (A _R + T _s ), it will be read out. The read write memory number (T _s −D ₂ ) or (T _n −D ₂ +64) and the underflow signal are given to the down counter 19 . The read underflow signal is “1” which means there is no underflow.
In this case, the down counter 19 adds the frequency division number 64 to the write memory number (T _s - D ₂ ), and the contents of the down counter 19 become T _n - _{D 2} + 64, where D ₂ = 64. −D ₁ , so by substituting this into the above equation, we get T _n −D ₂ +64=T _n −64+D ₁ +64 =T _n +D ₁ , and (T _n −D ₂ +64) becomes (T _n +D ₁ ) It can be seen that it is equivalent to The down counter 19 subtracts this write memory number (T _n + D ₁ ) by the clock pulse P _c , and when this number (T _n + D ₁ ) becomes zero, a delay pulse P _d is output to the output terminal 20. Ru. This delayed pulse P _d is output after a delay of (128+T) after the input pulse P _i is applied, as in the case described above.

When the read underflow signal is "0" meaning that there is an underflow, the down counter 19 does not add the frequency division number to the number of write memories (T _n -D ₂ +64). This number of write memories (T _n −D ₂ +64) is equivalent to (T _n +D ₁ ) as described above. down counter 1
9, this write memory number (T _n + D ₁ ) is subtracted by the clock pulse P _c , and when this number (T _n + D ₁ ) becomes zero, the delay pulse P _d is sent to the output terminal 20.
is output to.

As explained above, according to the pulse delay method and apparatus according to the present invention, it is possible to obtain a delay time longer than the repetition time of input pulses, which has been difficult in the past. In addition, in the pulse delay device of the present invention, a RAM is used, and the address side of the RAM is used for sparse delay times, and the memory side is used for dense delay times. It has the advantage of being able to set a long delay time without increasing the number of RAM bits. Furthermore, in the present invention, in view of the fact that the count number D ₂ that is unavoidably added to determine the input time point of the input pulse P _i is a variable that changes depending on the input time point of the input pulse P _i , D ₁ (=
By adding the frequency division number - D ₂ ), D ₂ + D ₁ = 64, that is, a constant, so that it can be treated as a fixed delay, so that no undefined variables are entered from the equipment side within the delay time.
It can be used like a normal delay device.
Next, in the third aspect of the present invention, processing when an underflow occurs during counting by the write memory counter is performed within the write memory counter.
The second invention can solve the timing problem when giving an overflow signal to the write address counter.

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional pulse delay device.
2 is a block diagram of the first embodiment of the pulse delay device according to the present invention, FIG. 3 A to F are waveform diagrams for explaining the operation of FIG. 2, and FIG. 4 is a sparse delay according to the present invention An explanatory diagram showing the relationship between the number of addresses indicating time, FIG. 5 is a second diagram of the pulse delay device according to the present invention.
FIG. 2 is a block diagram of an embodiment. 8... Input terminal, 9... Clock pulse generator, 10... Frequency divider, 11... Delay time setting section,
12...Random access memory (RAM), 1
3... Read address counter, 14... Write address counter, 15... Switch, 16...
... Gate control signal generator, 17 ... Memory counter for writing, 18 ... Gate circuit, 19 ... Down counter, 20 ... Output terminal.

Claims (1)

[Scope of Claims] 1. The number of delay time settings T is divided into the number of sparse delay time settings T _s and the number of fine delay time settings T _n , and the number of delay time settings T _s is used for writing to the storage device. Specify the number of addresses A _W , and use the number of write addresses A W to calculate the number of write memories formed based on the number involved in the arrival point of input pulse P _i and _the number of fine delay time settings T _n . Write to the specified address of the storage device, read the write memory number written to the storage device after a time corresponding to the sparse delay time setting number T _s , and from this reading time, the write memory number will be changed to the write memory number. A pulse delay method characterized in that a delayed output pulse is issued after a corresponding time. 2. A clock pulse generator that outputs a high frequency clock pulse P _c , and a clock pulse generator that outputs a high frequency clock pulse P c, and a clock pulse generator that outputs a high frequency clock pulse P _c .
A frequency divider that outputs a frequency-divided pulse P _b divided into N (N is a frequency division number, an integer of 2 or more), a delay time T, a digital coarse delay time setting number T _s , and a fine delay time setting. A delay time setting section that divides the divided pulse into two and outputs the number T _n , and the number of write addresses A specified for each cycle of the frequency-divided pulse P _b and the number A of read addresses specified for writing to the address _W. Random access memory (hereinafter referred to as RAM) that performs reading from address _R , counts the frequency divided pulse P _b with the maximum number of addresses of the RAM as the maximum count number, and calculates the count number as the number of addresses for reading. A read address counter for specifying an address for reading the RAM as A _R ;
The sum of the number of sparse delay time settings T _s given by the delay time setting section and the current number of read addresses A _R given by the read address counter, with the maximum number of addresses in RAM as the maximum count number. A write address counter that specifies the write address of the RAM with (T _s + A _R ) as the write address number A _W , and a write address counter that specifies the write address of the RAM using the frequency division pulse P _b as the control signal.
A switch that switches A _R and the number of write addresses A _W to the RAM every half cycle of the frequency-divided _{pulse ;} A gate control signal generator that outputs a gate control signal G ₁ during a period d ₂ up to a falling edge, and a gate control signal generator that counts the number D ₂ of the clock pulses P _c applied during the period in which the gate control signal G ₁ is being output. The number D ₂ is subtracted from the dividing number N to give the time interval d ₁ between the beginning of the cycle of the dividing pulse when the input pulse P _i is given and the time of input of the input pulse P _i . The number D ₁ of the corresponding clock pulses P _c is calculated, and the number of fine delay time settings T _n given from the delay time setting section is added to the number D ₁ to obtain the number of write memories (T _n + D ₁ ).
is calculated, and only when this number ( _{T n} + D ₁ )>N, an overflow signal is sent to the write address counter to increase the sparse delay time _setting number T _s , while the write memory number ( T _n +D ₁ ) is a write memory counter that outputs the number of write addresses A _W (=T _s + A _R ) specified by the write address counter to be written to the address of the RAM; The data is read from the RAM at the time when the number of read addresses (T _s + A _R ) is increased by T _s from the number of read addresses A _R at the time when the memory number (T _n + D ₁ ) is written. and a down counter that subtracts the number of write memories (T _n +D ₁ ) by the clock pulse P _c and outputs a delayed output pulse P _d when the number becomes zero. A pulse delay device characterized by: 3 A clock pulse generator that outputs a high frequency clock pulse P _c , and a clock pulse generator that outputs a high frequency clock pulse P _c , and a
A frequency divider that outputs a frequency-divided pulse P _b divided into N (N is a frequency division number, an integer of 2 or more), a delay time T, a digital coarse delay time setting number T _s , and a fine delay time setting. A delay time setting section that divides the divided pulse into two and outputs the number T _n , and the number of write addresses A specified for each cycle of the frequency-divided pulse P _b and the number A of read addresses specified for writing to the address _W. Random access memory (hereinafter referred to as RAM) that performs reading from address _R , counts the frequency divided pulse P _b with the maximum number of addresses of the RAM as the maximum count number, and calculates the count number as the number of addresses for reading. A read address counter for specifying an address for reading the RAM as A _R ;
The sum of the number of sparse delay time settings T _s given by the delay time setting section and the current number of read addresses A _R given by the read address counter, with the maximum number of addresses in RAM as the maximum count number. A write address counter that specifies the write address of the RAM with (T _s + A _R ) as the write address number A _W , and a write address counter that specifies the write address of the RAM using the frequency division pulse P _b as the control signal.
A switch that switches A _R and the number of write addresses A _W to the RAM every half cycle of the frequency-divided _{pulse ;} A gate control signal generator that outputs a gate control signal G ₁ during a period d ₂ up to a falling edge, and a gate control signal generator that counts the number D ₂ of the clock pulses P _c applied during the period in which the gate control signal G ₁ is being output. The number D ₂ is the fine delay time setting number Tm
Obtain the number (T _n − D ₂ ) subtracted from , and when T _n ≧ D ₂ , output an underflow signal that means no underflow, and when T _n < D ₂ , output an underflow signal that means there is an underflow. When the signal is output and there is underflow, (T _n −D ₂ +
N) is output as the number of write memories, and when there is no underflow, (T _n −D ₂ ) is output as the number of write memories, and these underflow signals and the number of write memories are specified from the write address counter. Number of write addresses A _W (=T _s
A write memory counter outputs to be written to the RAM address of +A _R ), and the number of read addresses increases by T _s from the number of read addresses A _R at the time the write memory number is written. When the number of read addresses (T _s + A _R ) reached
Given the number of write memories read from RAM and an underflow signal, if the underflow signal at that time means no underflow, the number of write memories read from RAM (T _n - D ₂ ).
The number obtained by adding the frequency division number N (T _n - D ₂ +N) is subtracted by the clock pulse P _c , and when the number becomes zero, a delayed output pulse P _d is output, and the underflow signal at that time is When it means underflow, the number of write memories read (T _n −
D ₂ +N) by the clock pulse P _c and a down counter that outputs a delayed output pulse when the number becomes zero.