JPH0221761U - - Google Patents

Info

Publication number
JPH0221761U
JPH0221761U JP1988101015U JP10101588U JPH0221761U JP H0221761 U JPH0221761 U JP H0221761U JP 1988101015 U JP1988101015 U JP 1988101015U JP 10101588 U JP10101588 U JP 10101588U JP H0221761 U JPH0221761 U JP H0221761U
Authority
JP
Japan
Prior art keywords
light emitting
emitting surface
light
semiconductor device
optically coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1988101015U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988101015U priority Critical patent/JPH0221761U/ja
Publication of JPH0221761U publication Critical patent/JPH0221761U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H10W72/5473—Dispositions of multiple bond wires multiple bond wires connected to a common bond pad
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/753—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Description

【図面の簡単な説明】
第１図は本考案の一実施例を示す切欠き斜視図
、第２図は発光ダイオードの斜視図、第３図は従
来の発光ダイオードの斜視図、第４図は従来の光
結合半導体装置の斜視図である。 １：光結合半導体装置、１０：発光ダイオード
、１１：発光面、１２：電極面、２１：外装樹脂
、２２：リードフレーム、２３：ボンデイングワ
イヤ、２４：受光素子、２５：ＦＥＴ。

Claims (1)

  1. 【実用新案登録請求の範囲】 一対の電極面への入力信号の印加により発光面
    より発光を行なう発光ダイオードと、該発光面か
    らの光を受光する受光素子とを備えた光結合半導
    体装置において、 上記発光ダイオードを、上面・下面を三角形と
    する三角柱に形成し、その上面・下面に電極面を
    配し、その側面に発光面を配すると共に、ダイオ
    ードの三角形の長辺側の発光面を上記受光素子と
    対向するように配置したことを特徴とする光結合
    半導体装置。
JP1988101015U 1988-07-29 1988-07-29 Pending JPH0221761U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988101015U JPH0221761U (ja) 1988-07-29 1988-07-29

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988101015U JPH0221761U (ja) 1988-07-29 1988-07-29

Publications (1)

Publication Number Publication Date
JPH0221761U true JPH0221761U (ja) 1990-02-14

Family

ID=31329622

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988101015U Pending JPH0221761U (ja) 1988-07-29 1988-07-29

Country Status (1)

Country Link
JP (1) JPH0221761U (ja)

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