JPH02218149A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent short-circuit accidents and to provide high integration density by forming the contact part of a lower wiring pattern into a protruding hill shape, and coupling said part into the through hole in an interlayer insulating film. CONSTITUTION:Wiring patterns are formed in many layers on a semiconductor substrate 11 through an insulating film 12. A contact part 20 of a lower wiring pattern 13 is electrically connected to a contact part 21 of an upper wiring pattern 15 by way of a contact hole 18 which is formed in an interlayer insulating film 14 in this semiconductor device. In this device, the contact part 20 of the lower wiring pattern 13 is formed into a protruding hill shape and coupled into the through hole 18 of the interlayer insulating film 14. As a result, the current capacity in the upper wiring pattern 15 can be increased without enlarging the through hole 18. Thus, short-circuit accidents can be prevented, and the high integration density can be provided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device such as an IC in which a wiring pattern is formed in a multilayer structure on a semiconductor substrate, and a method for manufacturing the same.

[Conventional technology]

ICC pellets such as linear IC, MOS, and IC 1
Circuit components including multiple semiconductor elements, resistors, capacitors, etc. are formed on a single semiconductor substrate, and these circuit components are electrically connected using a wiring pattern made of an AI vapor deposited film formed on the semiconductor substrate via an insulating film. Connected structures are common. Wiring patterns on semiconductor substrates are required to have an increasingly high degree of integration, and in order to meet this demand, wiring patterns are often formed in multiple layers with insulating films interposed therebetween.

For example, an example of a semiconductor device in which wiring patterns are formed in two layers is shown in FIG. 11, and its manufacturing process is shown in FIGS. 12 to 19, which will be explained as follows.

In FIG. 11, (1) is a semiconductor substrate, (2) to (5)
) is an insulating film, a lower layer wiring pattern, an interlayer insulating film, and an upper layer wiring pattern which are sequentially laminated on the semiconductor substrate (1).

That is, first, as shown in FIG. 12, a semiconductor substrate (1) on which circuit components (6) are formed in advance is prepared. next,
As shown in FIG. 13, C
An insulating film (2) such as an oxide film (SiOz) or a nitride film (Si3N4) is formed by VD (chemical vapor deposition), and then, as shown in FIG. A contact hole (7) is formed by selectively removing a portion of the semiconductor substrate (1) corresponding to the electrode portion of the circuit component (6) using PR (photolithography). Next, as shown in FIG. 15, an Al vapor-deposited PA (3') is formed on the entire surface of the semiconductor substrate (1), and then, as shown in FIG.
3') is patterned by PR to form a desired lower wiring pattern (3) on a selected portion of the semiconductor substrate (1) exposed from the insulating film (2) and the contact portion (7). Next, as shown in FIG. 17, an interlayer insulating film (4) such as phosphor glass (PSG) is formed by CvD on the exposed portions of the lower wiring pattern (3) and the insulating layer (2), and then, As shown in FIG. 18, the portion corresponding to the portion where the lower layer wiring pattern (3) of the interlayer insulating film (4) and the upper layer wiring pattern (5) to be formed later are electrically connected is selectively used by PR. Then, as shown in FIG. 19, interlayer insulation II! is removed to form a through hole (8). J
(4) Form the A/evaporation film (5') on the entire surface of the selected part of the lower wiring pattern (3) exposed from the upper and contact parts (8), and then form the A/evaporation film (5') PI
? The desired upper layer wiring pattern (5
) to obtain a semiconductor device as shown in FIG. The upper layer wiring pattern (5) and the lower layer wiring pattern (3) partially intersect with each other to increase the degree of wiring pattern integration.

[Problem to be solved by the invention]

By the way, the through-hole (8) of the semiconductor device has a 20th hole in order to prevent the upper layer wiring pattern (5) from breaking.
As shown in the figure, the upper part is tapered,
There is a large level difference between the surface of the lower layer wiring pattern (3) and the interlayer insulation [% (4), and the upper layer wiring pattern (5) is still
There was a drawback that the steps were easily broken.

Further, when the upper part of the through hole (8) is tapered, the opening area at the lower end of the through hole (8) is smaller than that at the upper end, resulting in a disadvantage that the current capacity of the upper layer wiring pattern (5) becomes smaller. In addition, if the lower end opening area of the through hole (8) is increased in order to increase the current capacity of the upper layer wiring pattern (5), the upper end opening area will increase accordingly, which may reduce the degree of integration or increase the current capacity of the upper layer wiring pattern. Pattern (5) had a problem in that short-circuit accidents were more likely to occur.

[Means to solve the problem]

This invention has been devised in view of the above problem, and the first invention to solve this problem is to form a wiring pattern in multiple layers on a semiconductor substrate with an insulating film interposed therebetween, and to form a lower layer wiring pattern. In a semiconductor device in which the contact portion of the lower layer wiring pattern and the contact portion of the upper layer wiring pattern are electrically connected by a through hole formed in an interlayer insulating film, the contact portion of the lower layer wiring pattern is formed to protrude in a mountain shape to form a through hole in the interlayer insulating film. This is a semiconductor device fitted inside the device.

Further, in a second invention, an insulating film is formed on a semiconductor substrate on which circuit components are formed, and a contact hole is formed by removing a portion of the insulating film corresponding to an electrode portion of a circuit component of the semiconductor substrate. After that, when forming a wiring pattern on the electrode portion of the circuit component of the semiconductor substrate exposed from the insulating film and the contact hole, a wiring pattern is formed on the electrode portion of the circuit component of the semiconductor substrate exposed from the insulating film and the contact hole. To make it thicker! This is a method of manufacturing a semiconductor device in which a wiring pattern material such as an evaporated film is formed, and the thickness of this wiring pattern material is selectively thinned by PR or the like to form a protruding mountain-shaped contact portion with an upper layer wiring pattern. .

[Effect]

By the above means, the step difference between the lower layer wiring pattern and the interlayer insulating film is reduced, and the problem of step breakage at the through hole of the upper layer wiring pattern is solved. Since the contact portion of the lower layer wiring pattern is formed in a mountain shape, the current capacity of the upper layer wiring pattern can be increased without increasing the size of the through hole.

〔Example〕

This invention will be explained below according to one embodiment.

FIG. 1 shows a cross section of essential parts of a semiconductor device according to the present invention, in which (11) is a semiconductor substrate, (12) to (15) are insulating films sequentially formed on the semiconductor substrate (11), These are a lower layer wiring pattern, an interlayer insulating film, and an upper layer wiring pattern. (16) is a circuit component formed on a semiconductor substrate (1 piece), (17) is a semiconductor substrate (11) of an insulating film (12)
The contact hole (18) is formed in a portion corresponding to the electrode portion of the circuit component (16);
4) Lower layer wiring pattern (13) and upper layer wiring pattern (
15) is a contact hole formed in a portion corresponding to the electrical connection portion, (19) is a contact portion of the lower wiring pattern (13) with the electrode of the circuit component (16) of the semiconductor substrate (11), (2o) (21) is the contact portion of the lower layer wiring pattern (13) with the upper layer wiring pattern (15);
is the lower layer wiring pattern (13) of the upper layer wiring pattern (15)
) is the contact part.

The semiconductor device of the present invention is characterized by a lower wiring pattern (1
3) Contact portion (2) with upper layer wiring pattern (15)
0) is formed to protrude in the shape of a mountain with a step above the lower wiring pattern (13), and is fitted into the through hole (1B) of the interlayer insulating film (14). In this way, the contact portion (2) of the lower wiring pattern (13)
0) to interlayer insulation M\[(14) through hole (18)
When inserted into the inner layer, the step difference between the lower layer wiring pattern (13) and the interlayer insulating film (14) is reduced and the upper layer wiring pattern (15)
) The problem of breakage at the through hole (18) of the interlayer insulation il (14) is solved. In addition, since the contact portion (20) of the lower layer wiring pattern (13) is formed in a mountain shape, the current capacity of the upper layer wiring pattern (15) can be increased without having to large-scale the through hole (18). ,
There is no need to worry about a decrease in the degree of integration or short-circuit accidents.

Next, a method for manufacturing a semiconductor device according to the present invention for manufacturing the above-mentioned semiconductor device will be explained according to the steps.

First, as shown in FIG. 2, the circuit components (16) are prepared in advance.
A semiconductor substrate (11) on which is formed is prepared.
As shown in the figure, the entire surface of the semiconductor substrate (11) is
Insulating PA (12
), followed by PR to insulate [l!] as shown in FIG. (12) Circuit configuration of semiconductor substrate (11) @
(16) is selectively removed to form a contact hole (17). Next, as shown in FIG. An At evaporated film (13°) is formed on the exposed electrode portion of the circuit component (16) of the semiconductor substrate (11) to be thicker than the lower wiring pattern (13) to be formed later. At this time, AI vapor deposition II! l! ! (13°) enters the contact hole (17) to form a contact portion (19) with the electrode portion of the circuit component (16) of the semiconductor substrate (11) of the lower wiring pattern (13) to be formed later. Next, as shown in FIG.
The lower layer wiring pattern (13) and the upper layer wiring pattern (15) will be formed later by selectively thinning the film thickness of 3°) with PR.
A contact portion (20) is formed in a protruding mountain shape.

Next, as shown in FIG. 7, the Af evaporated film (13°) was
R patterning to form the desired lower layer wiring pattern (1
3) Form. Next, as shown in FIG. 8, insulate the lower layer wiring pattern (13)! I! An interlayer insulating film (14) such as PGS is formed on the exposed portion of J (12) by CvD. At this time, a contact portion (20) of the lower layer wiring pattern (13) is provided in a portion corresponding to an electrical connection portion between the lower layer wiring pattern (13) of the interlayer insulation 1111 (14) and the upper layer wiring pattern (15) to be formed later. Then, as shown in FIG. 9, the lower wiring pattern (1) of the interlayer insulation M (14) is formed.
A portion corresponding to the contact portion (20) in 3) is selectively removed using PR to form the upper part of the through hole (18).

Next, as shown in FIG. 10, the lower wiring pattern (
13) An At evaporated film (
15"). At this time, Al vapor deposition Ill (1
5°) enters the through hole (18) and the lower layer wiring pattern (1
3) where the contact portion (21) is formed, the A
The t-deposited film (15'') is patterned by PR to form a desired upper layer wiring pattern (15) to obtain a semiconductor device as shown in FIG.

Note that the present invention is not limited to semiconductor devices with two-layer wiring, but can be similarly applied to devices having wiring patterns of two or more layers.

〔Effect of the invention〕

According to the present invention, the step difference between the lower layer wiring pattern and the interlayer insulating film is reduced, the problem of step breakage at the through hole of the upper layer wiring pattern is solved, and a highly reliable semiconductor device can be provided. Furthermore, since the current capacity of the upper layer wiring pattern can be increased without increasing the size of the through hole as in the conventional case, there is no fear of short circuit accidents, etc., and high integration is possible.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of essential parts showing an embodiment of a semiconductor device according to the present invention, and FIGS. 2 to 10 illustrate a method for manufacturing a semiconductor device according to the present invention for manufacturing the semiconductor device shown in FIG. FIG. 3 is a cross-sectional view of a main part showing each process for explanation. FIG. 11 is a sectional view of main parts showing a conventional example of a semiconductor device,
2 to 19 are cross-sectional views of main parts showing each process for explaining the manufacturing method of the semiconductor device shown in FIG. 11, and FIG. 20 is an enlarged cross-sectional view of main parts showing through holes of a conventional semiconductor device. . (11)--Semiconductor substrate, (12)-Insulating film, (13)
- Lower layer wiring pattern, (14) -... - Interlayer insulating film, (15) - Upper layer wiring pattern, (16) - Circuit component, (17) - Contact hole, (18) - Through hole, (19) ~(21) -・Contact part. Figure 9 Figure 11 Figure 13 Figure 15 Figure 10 Figure 12 Figure 14 Figure 16

Claims (2)

[Claims] (1) A semiconductor in which wiring patterns are formed in multiple layers on a semiconductor substrate via insulating films, and the contact portions of the lower layer wiring pattern and the contact portions of the upper layer wiring pattern are electrically connected through through holes formed in the interlayer insulating film. 1. A semiconductor device, characterized in that a contact portion of a lower wiring pattern is formed in a protruding mountain shape and is fitted into a through hole of an interlayer insulating film. (2) After forming an insulator 1 on a semiconductor substrate on which circuit components are formed, and forming a contact hole by removing a portion of this insulating film that corresponds to an electrode portion of a circuit component of the semiconductor substrate, the insulating film is When forming a wiring pattern on the electrode part of the circuit component of the semiconductor substrate exposed from the top and contact hole, the wiring pattern should be thicker than the wiring pattern on the electrode part of the circuit component of the semiconductor substrate exposed from the top of the insulating film and the contact hole. A semiconductor characterized in that a wiring pattern material such as an Al evaporation film is formed, and the thickness of this wiring pattern material is selectively thinned by PR or the like to form a protruding mountain-shaped contact portion with an upper layer wiring pattern. Method of manufacturing the device.