JPH02218206A - Ic for power amplification - Google Patents
Ic for power amplificationInfo
- Publication number
- JPH02218206A JPH02218206A JP1039811A JP3981189A JPH02218206A JP H02218206 A JPH02218206 A JP H02218206A JP 1039811 A JP1039811 A JP 1039811A JP 3981189 A JP3981189 A JP 3981189A JP H02218206 A JPH02218206 A JP H02218206A
- Authority
- JP
- Japan
- Prior art keywords
- connection
- btl
- gain
- terminal
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Bipolar Integrated Circuits (AREA)
- Amplifiers (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
(産業上の利用分野)
本発明は電力増幅用IC(集積回路)に関するもので、
特にオーディオ用に使用されるものである。[Detailed Description of the Invention] [Object of the Invention] (Field of Industrial Application) The present invention relates to a power amplification IC (integrated circuit),
It is especially used for audio.
(従来の技術)
従来より電力増幅用ICにおいては、デュアル(Dua
l)接続方式及びB T L (BalancedTr
ansformer Less)接続方式のいずれの使
用も可能である。しかしながら帰還回路用の抵抗は、少
くともBTL接続においては外付けされている。(Conventional technology) Conventionally, power amplification ICs have dual (Dua)
l) Connection method and BTL (BalancedTr)
It is possible to use any of the following connection methods. However, the resistor for the feedback circuit is externally attached at least in the BTL connection.
第3図はデュアル接続、第4図はBTL接続の具体例で
あり、1は入力信号源、2は電力増幅用IC部、3,4
は増幅器(オペアンプ)、5は負荷である。またRF
r R9、RE r RA r RBは利得を決める抵
抗であるが、第2図のBTL接続例ではRE、RA、R
Bが外付けとなっている。Figure 3 shows a specific example of dual connection, and Figure 4 shows a specific example of BTL connection, where 1 is an input signal source, 2 is a power amplification IC section, 3, 4
is an amplifier (op-amp), and 5 is a load. Also RF
r R9, RE r RA r RB are resistors that determine the gain, but in the BTL connection example in Figure 2, RE, RA, R
B is externally attached.
(発明が解決しようとする課題)
上記のように従来の電力増幅用ICは、特にBTL接続
では外付は抵抗を必要とするため、閉ループ電圧利得(
以下利得という)が、電力増幅用10部2内の抵抗RF
、R8と外付は抵抗R5゜RA + RBの比関係で決
定されるため、どちらか一方のばらつきにより利得がば
らついてしまう欠点がある。またデュアル接続とBTL
接続は回路構成が異なるため、これらは使用に応じて使
い分けしなければならず、設計、製作、使用等に手間を
要する。(Problems to be Solved by the Invention) As mentioned above, conventional power amplification ICs require external resistors, especially in BTL connections, so closed-loop voltage gain (
(hereinafter referred to as gain) is the resistance RF in the power amplifying section 2.
, R8 and the external connection are determined by the ratio of the resistor R5°RA + RB, so there is a drawback that the gain varies due to variations in either one. Also dual connection and BTL
Since the connections have different circuit configurations, these must be used depending on the use, which requires time and effort in designing, manufacturing, and using.
そこで本発明の目的は、デュアル接続、BTL接続いず
れの使用状態においても、利得のばらつきが少くかつI
C設計、製作が容易な電力増幅用ICを提供することに
ある。Therefore, it is an object of the present invention to reduce gain variation and improve I
An object of the present invention is to provide a power amplification IC that is easy to design and manufacture.
(課題を解決するための手段と作用)
本発明は、
BTL接続で利得を決める各抵抗と増幅器を同一チップ
内に形成し、デュアル接続とする場合は前記各抵抗の一
部を不使用状態におき、BTL接続とする場合は前記各
抵抗を使用してなり、前記デュアル接続、BTL接続間
の使用切り換えは、スイッチ切り換え、配線の有無を選
択的に用いることで行なうことを特徴とする電力増幅用
ICである。(Means and effects for solving the problem) The present invention forms each resistor that determines the gain and the amplifier in the same chip by BTL connection, and in the case of dual connection, leaves a part of each of the resistors in an unused state. The power amplification is characterized in that the above-mentioned respective resistors are used when the dual connection and the BTL connection are made, and the use switching between the dual connection and the BTL connection is performed by switching a switch and selectively using the presence or absence of wiring. This is an IC for use.
即ち本発明は、IC製造においては該ICの各抵抗値間
の比を一定化することは容易であることから、増幅器の
利得を決める各抵抗を同一チップ内に形成する。またデ
ュアル接続とBTL接続は、一部構成が類似しているこ
とから、利得を決める各抵抗をBTL接続方式側に統一
しておき、デュアル接続、BTL接続の選択を、スイッ
チの切り換え、配線の有無等で行なうようにしたもので
ある。That is, in the present invention, since it is easy to keep the ratio between the respective resistance values of the IC constant during IC manufacturing, each resistor that determines the gain of the amplifier is formed in the same chip. In addition, since dual connection and BTL connection have some similar configurations, each resistor that determines the gain is unified on the BTL connection method side, and the selection between dual connection and BTL connection can be made by changing the switch and changing the wiring. This is done based on presence or absence.
(実施例)
以下図面を参照して本発明の詳細な説明する。第1図、
第2図は同実施例の回路図であるが、これらは第3図、
第4図のものと対応させた場合の例であるから、対応個
所には同一符号を付して説明を省略し、特徴とする点の
説明を行なう。第1図、第2図において111〜119
はICチップ2の外部導出端子、12はスイッチ、a、
bはその固定接点である。(Example) The present invention will be described in detail below with reference to the drawings. Figure 1,
Figure 2 is a circuit diagram of the same embodiment;
Since this is an example corresponding to that in FIG. 4, the corresponding parts will be given the same reference numerals and the explanation will be omitted, and the characteristic points will be explained. 111 to 119 in Figures 1 and 2
is an external lead-out terminal of IC chip 2, 12 is a switch, a,
b is its fixed contact.
第1図はデュアル接続例であり、端子112につながる
抵抗REは、端子113を通る配線で短絡されており、
また端子114はフローティングとなっている。従って
入力信号源1からの信号は、増幅用IC部2の増幅器3
,4によりそれぞれ増幅され、負荷5へ送られる。この
ときの利得GV、は・
で決定される。FIG. 1 shows an example of dual connection, in which the resistor RE connected to the terminal 112 is short-circuited by the wiring passing through the terminal 113.
Further, the terminal 114 is floating. Therefore, the signal from the input signal source 1 is transmitted to the amplifier 3 of the amplification IC section 2.
, 4 and sent to the load 5. The gain GV at this time is determined by .
第2図はBTL接続接続高り、ここでスイッチ12が固
定接点す側にあれば、端子112につながる抵抗REは
使用状態にある。また端子114と115は配線でショ
ートされており、この糸路は使用状態にある。従って入
力信号源1から3の信号は、増幅用IC部2の増幅器3
と4で増幅され、負荷5へ送られる。このときの利得G
v2はで決定される。FIG. 2 shows the BTL connection, and if the switch 12 is on the fixed contact side, the resistor RE connected to the terminal 112 is in use. Further, the terminals 114 and 115 are short-circuited by wiring, and this yarn path is in a used state. Therefore, the signals from the input signal sources 1 to 3 are transmitted to the amplifier 3 of the amplification IC section 2.
and 4, and sent to load 5. Gain G at this time
v2 is determined by .
第1図、第2図のように、帰還回路の抵抗RA。As shown in FIGS. 1 and 2, the resistance RA of the feedback circuit.
RB + RE 、R9+ RFを全て開−IC部2内
に内蔵させることにより、利得G■1は、(1)式より
rRp +R8JとR5の抵抗比率で決まり、利得GV
2は、(2)式よりrR3+RE 十Rp JとrRs
+REJの抵抗比率、及びr (RA+Rs )(RE
+ RS+ RA / R8) Jと「RB−RF」
の抵抗比率で決まる。ところでICのように同一条件下
でつくられた各抵抗の値は、それぞれ同じようにばらつ
くから、相対的に上記各抵抗比率のばらつきは相殺され
、従って上記利得Gvl。By incorporating all of RB + RE and R9 + RF in the open-IC section 2, the gain G1 is determined by the resistance ratio of rRp + R8J and R5 from equation (1), and the gain GV
2 is rR3+RE 10Rp J and rRs from equation (2)
+REJ resistance ratio, and r (RA+Rs)(RE
+ RS+ RA/R8) J and “RB-RF”
It is determined by the resistance ratio of By the way, since the values of each resistor produced under the same conditions as in an IC vary in the same way, the variations in the respective resistance ratios are relatively canceled out, and therefore the gain Gvl.
GV2は一定化される。GV2 is made constant.
換言すれば、前記従来例の如く帰還回路の抵抗RE、R
A、RB等を外付けにすると、該外付は抵抗とIC部2
内の抵抗ばらつきは相異するから利得がばらつく。一方
、現在のIC製造法において、抵抗値の絶対値を制御す
ることは困難であるが、抵抗値の比率(相対比)を制御
することは容易であるから、正確化された利得が得られ
る。In other words, as in the conventional example, the resistances RE and R of the feedback circuit
When A, RB, etc. are externally connected, the external devices are connected to the resistor and IC section 2.
Since the resistance variations within the two terminals are different, the gain varies. On the other hand, in current IC manufacturing methods, it is difficult to control the absolute value of the resistance value, but it is easy to control the ratio (relative ratio) of the resistance value, so accurate gain can be obtained. .
またIC部2は、デュアル接続とする場合もBTL接続
とする場合も同様の構成とし、外部で配線操作してやれ
ばよいから、ICの設計、製作以上説明した如く本発明
によれば、デュアル接続、BTL接続いずれの場合にお
いても、利得のばらつきが少なく、かつ設計、製作等が
容易化された電力増幅用ICが提供できるものである。Further, the IC section 2 has the same configuration whether it is dual connection or BTL connection, and the wiring can be operated externally.As explained above, according to the present invention, dual connection, In either case of BTL connection, it is possible to provide a power amplification IC that has little variation in gain and is easy to design, manufacture, etc.
第1図、第2図は本発明の各実施例を示す回路図、第3
図、第4図は従来例を示す回路図である。
1・・・入力信号源、2・・・電力増幅用IC部、3゜
4・・・増幅器(オペアンプ)、5・・・負荷、111
〜119・・・外部導出端子、12・・・スイッチ、R
A。
RB r RE 、RF 、R9”’抵抗。
出願人代理人 弁理士 鈴江武彦Figures 1 and 2 are circuit diagrams showing each embodiment of the present invention, and Figure 3 is a circuit diagram showing each embodiment of the present invention.
4 are circuit diagrams showing a conventional example. DESCRIPTION OF SYMBOLS 1... Input signal source, 2... IC part for power amplification, 3° 4... Amplifier (op-amp), 5... Load, 111
~119...External lead-out terminal, 12...Switch, R
A. RB r RE , RF , R9”'Resistance. Applicant's representative Patent attorney Takehiko Suzue
Claims (1)
内に形成し、デュアル接続とする場合は前記各抵抗の一
部を不使用状態におき、BTL接続とする場合は前記各
抵抗を使用してなり、前記デュアル接続、BTL接続間
の使用切り換えは、スイッチ切り換え、配線の有無を選
択的に用いることで行なうことを特徴とする電力増幅用
IC。The resistors and amplifiers that determine the gain in BTL connection are formed in the same chip, and when dual connection is used, some of the resistors are left unused, and when BTL connection is made, the resistors are used. The power amplification IC is characterized in that switching between the dual connection and the BTL connection is performed by switching a switch or selectively using the presence or absence of wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1039811A JPH02218206A (en) | 1989-02-20 | 1989-02-20 | Ic for power amplification |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1039811A JPH02218206A (en) | 1989-02-20 | 1989-02-20 | Ic for power amplification |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02218206A true JPH02218206A (en) | 1990-08-30 |
Family
ID=12563352
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1039811A Pending JPH02218206A (en) | 1989-02-20 | 1989-02-20 | Ic for power amplification |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02218206A (en) |
-
1989
- 1989-02-20 JP JP1039811A patent/JPH02218206A/en active Pending
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