JPH0221824U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the frequency multiplier circuit of the present invention. FIG. 2 is a frequency multiplier circuit diagram that is an embodiment of the present invention. FIG. 3 is a signal waveform diagram of each part of the frequency multiplier circuit of FIG. 2. FIG. 4 is a diagram of a conventional frequency multiplier circuit. FIG. 5 is a diagram of a conventional frequency multiplier circuit. 1...Delay circuit, 2...Exclusive non-OR circuit,
3...Flip-flop circuit, 5...Conversion circuit,
6...Input terminal, 7...Output terminal.

Claims (1)

[Scope of utility model registration request] a delay circuit, a gate circuit that takes an exclusive non-OR of a basic input signal and a signal that the basic input signal has passed through the delay circuit, and inputting an output signal of the gate circuit to a first clock terminal; a first flip-flop circuit that outputs a first logic level at the positive edge of the output signal of the gate circuit and resets the basic input signal by inputting it to a first reset terminal; The second clock terminal outputs a second logic level at the positive edge of the output signal of the gate circuit, and the opposite logic level of the fundamental input signal input to the first reset terminal of the first flip-flop circuit. a second flip-flop circuit that applies a reset by inputting it to a second reset terminal; and a conversion circuit that inputs the outputs of each of the first and second flip-flop circuits and outputs a signal with a multiple frequency of the basic input signal. A frequency multiplier circuit characterized by being equipped with.