JPH02219245A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enlarge the sectional area of a gate electrode, and reduce gate resistance by a method wherein, after a first high melting point metal is worked in the form of a gate electrode, the circumference of the first high melting-point metal is covered with a dielectric film, and a second high melting point metal is selectively vapor-grown only on the first high melting point metal. CONSTITUTION:After a low concentration ion implanted layer 11 is formed by implanting silicon ion into a semiinsulative GaAs substrate 10, a first high melting point metal 12 is deposited by sputtering deposition method, and a photoresist 13 is formed at a gate electrode forming part position on the metal 12. On the whole surface, a dielectric film 15 is formed by CVD method, and thereon a photoresist 16 is formed. The photoresist is eliminated, and a second high melting point metal 17 is selectively vapor-grown on the first high melting point metal 12, by reducing WF6 with SiH4 gas. Thereby gate resistance can be reduced without deteriorating the dimensional accuracy of a gate electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a method for manufacturing a compound semiconductor device, and particularly to a method for manufacturing a compound semiconductor device using a high melting point metal as a gate electrode.

(b) Conventional technology In recent years, in the field of field effect transistors (FETs) using compound semiconductors, especially gallium arsenide (GaAs), devices using high-melting point metals for gate electrodes have been developed due to the simplicity of the manufacturing process.
It has attracted attention because of its ease of pattern miniaturization, and has been actively researched and developed. A low-resistance ion-implanted layer can be formed by performing high-concentration ion implantation and heat treatment using a gate electrode made of a high-melting point metal as a stopper mask. This ion implantation layer is made of GaAs.
When used in MESFET, it reduces the influence of surface depletion layer,
Moreover, parasitic series resistance can be reduced.

On the other hand, recently, a structure (LDD structure) in which an intermediate concentration ion implantation layer (n layer) is provided between a high concentration ion implantation layer (n layer) and a low concentration ion implantation layer (n layer) directly under the gate electrode has been developed. has been proposed (see 1986 IEICE General National Conference 56-7).

According to this LDD structure, the short channel effect can be suppressed and mutual conductance (gm) can be increased. The manufacturing method of MESFET with LDD structure is shown in Figure 3 (
The explanation will be based on a) to (e).

First, impurity ions are implanted into a semi-insulating GaAs substrate (30) to form an n-layer (31), and then a high melting point metal (for example, WSix) (32) is deposited by sputter deposition, and a photoresist ( 33) (Fig. 3(a)
)). Using the photoresist (33) as a mask, the high melting point metal (32) is processed into the shape of a gate electrode by anisotropic dry etching. Next, the entire surface is coated with SiO2 by CVD method.
(34) is formed (Fig. 3(b)). Furthermore, by anisotropic dry etching, S i O! (34) is etched, and a thin Sin is etched on both sides of the high melting point metal (32), and the side walls (
35), impurity ions are implanted from above to form an n-layer (36) (FIG. 3(C)). continue,
S10. by wet etching. After removing the sidewall (35), an n-layer (37) is formed by ion implantation, and heat treatment is performed to electrically activate the implanted impurity ions (FIG. 3(d)). Finally, the ohmic electrode (
38) to form a GaAs ME with an LDD structure.
The SFET is completed (Fig. 3(e)).

(c) Problems to be solved by the invention GaA using the above-mentioned conventional high melting point metal for the gate electrode
The manufacturing method of s MESFET has the following problems.

In order to improve the performance of GaAs MESFETs, it is necessary to shorten the gate length, but this reduces the cross-sectional area of the gate electrode and increases the gate resistance.

In order to reduce the gate resistance while keeping the gate length constant, it is conceivable to increase the film thickness of the refractory metal. but,
When processing a high melting point metal, if the film thickness of the high melting point metal is large, the dimensional accuracy of the gate length will deteriorate. This is because, in the case of dry etching, the amount of side etching is large, and furthermore, the etching mask (photoresist) is deformed by long etching. Therefore, there is a limit to the film thickness of the high melting point metal.

In addition to the above problems, in the LDD structure, the 5I02 side wall (
It is necessary to form side walls (35), which makes the process complicated.

(d) Means for Solving the Problems The present invention includes the steps of forming a low concentration ion implantation layer on a semiconductor substrate, and forming a first high melting point metal on a portion of the substrate where a gate electrode is to be formed. a step of forming a dielectric film on the substrate other than the first high melting point metal; a step of selectively vapor phase growing a second high melting point metal on the first high melting point metal; 2, forming a high concentration ion implantation layer using a high melting point metal as a mask.

(E) Effect After processing the first high melting point metal into the shape of the gate electrode, the first
The high melting point metal is covered with a dielectric film such as Sing, and the second high melting point metal is selectively grown in vapor phase only on the first high melting point metal, so the cross-sectional area of the gate electrode can be increased. It is possible to reduce the gate resistance.

Note that the second high melting point metal is not grown on the dielectric.

(F) Embodiment A first embodiment of the present invention will be explained based on FIGS. 1(a) to 1(f).

First, silicon ions were deposited on a semi-insulating GaAs substrate (semiconductor substrate) (10) at an acceleration voltage of 30 KeV and a dose of 3X.
10. After implanting at Cm -2 to form an n layer (low concentration ion implantation layer) (11), 3000 layers of WSix (first high melting point metal) (12) were deposited by sputter deposition, and then A photoresist (13) is formed at the site where the gate electrode is to be formed (FIG. 1(a)).

Next, W Si x (12) was processed into a gate electrode shape by anisotropic dry etching using the photoresist (13) as a mask, and silicon ions were etched at an acceleration voltage of 50 KeV and a dose using W S i x (12) as a mask. After forming an n-layer (intermediate concentration ion implantation layer) (14) by implanting with an amount of 7 x 10 "cm-", a 7 tresist (
13) (Fig. 1(b)).

1000 SiO2 (dielectric film) (15) is formed on the entire surface by CVD method, and a photoresist (16) is formed on this SrOt (15) (Fig. 1(C)).
.

Subsequently, WSi was formed by anisotropic dry etching.

Photoresist (16) until (12) is exposed, S+
Etch O*(15) and write W Si s (12
) on S r O * (15) (Fig. 1(d)
).

Furthermore, the 7 otoresist (16) was removed and the WF6 was
Tungsten (second high melting point metal) (17) is selectively grown on W S i x (12) by reduction with iH gas (FIG. 1(e)). At this time, the width of tungsten (17) is W Si x (12
) is larger than that of about 0.1μm (17°)
is formed. This eave (17') is formed on the dielectric material because it is also grown laterally.

Thereafter, SiO□ (15) is removed, and silicon ions are implanted at an acceleration voltage of 70 KeV and a dose of 2 x 1013 cm-' using the vapor-grown tungsten (17) as a mask to form an n-layer (high-concentration ion-implanted layer). )(
18) and heat-treated at 800°C for 20 minutes.

Finally, by forming an ohmic electrode (19), L
DD structure GaAs MESFET is completed (first
Figure (f)).

Next, a second embodiment of the present invention is shown in FIGS. 2(a) to (e).
The explanation will be based on.

First, silicon ions were accelerated onto a semi-insulating GaAs substrate (20) at a voltage of 30 KeV and a dose of 3 x 10 Ifcm.
-2 to form an n-layer (21), 3000 W Si x (22) is deposited by sputter deposition, and a photoresist (23) is formed on the area where the gate electrode is to be formed. (Figure 2(a)).

Next, W Si x (22) was processed into a gate electrode shape by anisotropic dry etching using the No. Implanted with an amount of 7X IQ” cm, the n-layer (24)
form.

Then, the entire surface was coated with 1000% by ECR plasma CVD method.
Forming human S i O2 (25) (Figure 2(b))
.

At this time, since the ECR plasma CVD method has good directionality, WSi x (22) and photoresist (23)
On the side wall of S i O! (1'5) hardly deposits.

Subsequently, brittle S + O! was deposited on the sidewalls of W S i x (22) and 7-otoresist (23). (25)
was removed by slight dry etching, and SiOt(25
) (Figure 2 (C)).

Next, WF is reduced by SiHa gas to selectively grow tungsten (27) on W Si x (22) in a 3000-degree phase. At this time, tungsten (27
) The width of the part not regulated by SiOz (25) is larger than that of the regulated part, and the width of the eaves (
27') is formed. After that, an n-layer layer (28) was formed by implanting silicon ions at an acceleration voltage of 70 KeV and a dose of 2 x 10 "cm-" using the vapor-grown tungsten (27) as a mask.
Heat treatment for 20 minutes is added (FIG. 2(d)).

Finally, after removing a predetermined portion of SiO (25) by dry etching, an ohmic electrode (29) is formed to form a GaAs MES made of LDDtlif.
The FET is completed (Fig. 2(e)).

In addition, in the embodiment shown in FIG. 1 described above, the ohmic electrode (19) may be formed using tungsten (17) as a mask as shown in FIG. According to this method, the number of patterning steps can be reduced by one, and the parasitic series resistance can be reduced.

Further, in each of the above embodiments, the first high melting point metal is WSix
However, W, Mo, TiW, WAl, etc. can be used.

Furthermore, in each of the above embodiments, WF is SiH.

Tungsten (17) (27
), but instead of SiH+ gas, H2, Si
, H, Si, H, can be used.

Furthermore, it is clear that the method of the present invention can be applied to a GaAs MESFET that does not have an n-layer and uses a normal high-melting point metal for the gate electrode.

(G) Effects of the Invention As is clear from the above description, the present invention can reduce the gate resistance without impairing the dimensional accuracy of the gate electrode.

Furthermore, when the present invention is applied to an LDD structure, there is no need to form sidewalls.

[Brief explanation of the drawing]

FIGS. 1(a) to (f), FIGS. 2(a) to (e), and FIG. 4 are manufacturing process diagrams for explaining the present invention in detail;
FIGS. 3(a) to 3(#) are manufacturing process diagrams for explaining the conventional technology. (10)(20)...Semi-insulating GaAs substrate (semiconductor substrate), (11)(21)...N layer (low concentration ion implantation layer), (12)(22)・WS i x ( first high melting point metal), (13) (23)... photoresist, (14) (24)... n layer (intermediate concentration ion implantation layer), (15) (25)... 5iO7 (dielectric film),
(16)...Photoresist, (17)(27)...
・Tungsten (second high melting point metal), (18) (28
)...n4 layer (high concentration ion implantation layer), (19) (2
9)...Ohmic electrode.

Claims (1)

[Scope of Claims] 1. A step of forming a low concentration ion implantation layer on a semiconductor substrate, a step of forming a first high melting point metal on a portion of the substrate where a gate electrode is to be formed, and the first high melting point metal. a step of forming a dielectric film on the substrate other than metal; a step of selectively vapor-growing a second high-melting point metal on the first high-melting point metal; 1. A method of manufacturing a semiconductor device, comprising: forming a high concentration ion implantation layer as a mask. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of forming an intermediate concentration ion implantation layer using the first high melting point metal as a mask. 3. The second high melting point metal is tungsten, and WF
_6 to H_2, SiH_4, Si_2H_6, Si_3
3. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is formed by vapor phase growth using a reducing gas such as H_8.