JPH0221942U - - Google Patents
Info
- Publication number
- JPH0221942U JPH0221942U JP10067088U JP10067088U JPH0221942U JP H0221942 U JPH0221942 U JP H0221942U JP 10067088 U JP10067088 U JP 10067088U JP 10067088 U JP10067088 U JP 10067088U JP H0221942 U JPH0221942 U JP H0221942U
- Authority
- JP
- Japan
- Prior art keywords
- digital signal
- order
- circuit
- clock
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000926 separation method Methods 0.000 claims description 5
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 238000012544 monitoring process Methods 0.000 claims description 4
- 230000005540 biological transmission Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Time-Division Multiplex Systems (AREA)
Description
第１図は本考案によるデイジタル信号分離回路
の実施例を示すブロツク構成図、第２図は従来の
デイジタル信号分離回路のブロツク構成図、第３
図は直列／並列変換回路の詳細説明図、第４図は
第１図の動作を説明するためのタイムチヤートで
ある。
１，４……直列／並列変換回路、２……クロツ
ク制御回路、３，７……順序監視回路、５……選
択回路、６……選択制御回路、８……シフトレジ
スタ（６段）、９……Ｄ―フリツプフロアプ（６
個）、１０……１／６分周器、ａ，ｇ……高位デ
イジタル信号、ｂ，ｈ……クロツク、ｃ，ｊ，ｉ
……低位デイジタル信号、ｄ，ｋ……低位デイジ
タル信号順序監視用信号、ｅ，ｌ……制御指示信
号、ｆ……制御されたクロツク、ｍ……選択制御
信号、ｎ……＃６へのデータ、ｐ……１／６クロ
ツク、＃１〜６……並列順序。
FIG. 1 is a block configuration diagram showing an embodiment of a digital signal separation circuit according to the present invention, FIG. 2 is a block configuration diagram of a conventional digital signal separation circuit, and FIG.
The figure is a detailed explanatory diagram of the serial/parallel conversion circuit, and FIG. 4 is a time chart for explaining the operation of FIG. 1. 1, 4...Serial/parallel conversion circuit, 2...Clock control circuit, 3, 7...Sequence monitoring circuit, 5...Selection circuit, 6...Selection control circuit, 8...Shift register (6 stages), 9...D-Flip Flop (6
), 10...1/6 frequency divider, a, g...High-order digital signal, b, h...Clock, c, j, i
...low-order digital signal, d, k ... signal for monitoring the order of low-order digital signals, e, l ... control instruction signal, f ... controlled clock, m ... selection control signal, n ... to #6 Data, p...1/6 clock, #1 to 6...parallel order.
Claims (1)
ジタル信号に分離するデイジタル信号分離回路に
おいて、前記高位デイジタル信号をクロツク信号
によりシフトすることによりシフトレジスタに格
納していき、前記クロツクの分周クロツクによつ
て前記シフトレジスタの格納データをＤ―フリツ
プフロツプに保持することによつて直列／並列変
換し、前記Ｄ―フリツプフロツプ出力を低位デイ
ジタル信号として出力する直列／並列変換回路と
、前記低位デイジタル信号の並列順序を監視し、
正規の並列順序よりずれた場合、そのずれに対応
する情報を出力する監視回路と、正規の並列順序
の低位デイジタル信号のときは、クロツク信号を
前記直列／並列変換回路にそのまま与え、前記監
視回路から情報が出力されたときはその情報が示
す時間だけクロツク送出を停止するクロツク制御
回路とから構成したことを特徴とするデイジタル
信号分離回路。 In a digital signal separation circuit that separates a synchronously multiplexed high-order digital signal into a low-order digital signal, the high-order digital signal is stored in a shift register by being shifted by a clock signal, and the above-mentioned signal is stored in a shift register by shifting the high-order digital signal using a clock signal. A serial/parallel conversion circuit that performs serial/parallel conversion by holding data stored in the shift register in a D-flip-flop and outputs the D-flip-flop output as a low-order digital signal, and monitors the parallel order of the low-order digital signals. death,
A monitoring circuit that outputs information corresponding to the deviation when the clock signal deviates from the normal parallel order; and a monitoring circuit that outputs information corresponding to the deviation when the clock signal deviates from the normal parallel order; 1. A digital signal separation circuit comprising: a clock control circuit that stops clock transmission for a time indicated by the information when the information is output from the digital signal separation circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10067088U JPH0221942U (en) | 1988-07-29 | 1988-07-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10067088U JPH0221942U (en) | 1988-07-29 | 1988-07-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0221942U true JPH0221942U (en) | 1990-02-14 |
Family
ID=31328954
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10067088U Pending JPH0221942U (en) | 1988-07-29 | 1988-07-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0221942U (en) |
-
1988
- 1988-07-29 JP JP10067088U patent/JPH0221942U/ja active Pending
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