JPH0221941U

JPH0221941U -

Info

Publication number: JPH0221941U
Application number: JP10066788U
Authority: JP
Priority date: 1988-07-29
Filing date: 1988-07-29
Publication date: 1990-02-14

Description

[Brief explanation of drawings]

第１図は本考案によるデイジタル信号分離回路
の実施例を示す図、第２図および第３図は第１図
の回路の動作を説明するための図、第４図は第１
図のタイムチヤート、第５図は従来の分離回路の
一例を示す図である。１……２４段シフトレジスタ回路（図はｎ＝３
）、２，３，４……メモリ付並列／直列変換回路
、５……クロツク制御回路、６……監視回路、７
……分離回路、ａ……バイト多重された高速高位
デイジタル信号、ｂ……クロツクｆ_０、ｃ……読
み出しクロツクｆ_０／３、ｄ……入力クロツクｆ
_０、ｅ……レジスタ内の信号、ｆ，ｇ，ｈ……分
離された低位デイジタル信号。 FIG. 1 is a diagram showing an embodiment of the digital signal separation circuit according to the present invention, FIGS. 2 and 3 are diagrams for explaining the operation of the circuit in FIG.
The time chart in the figure, FIG. 5, is a diagram showing an example of a conventional separation circuit. 1...24-stage shift register circuit (n=3 in the figure)
), 2, 3, 4...Parallel/serial conversion circuit with memory, 5...Clock control circuit, 6...Monitoring circuit, 7
... Separation circuit, a... Byte multiplexed high-speed high-order digital signal, b... Clock f ₀ , c... Readout clock f ₀ /3, d... Input clock f
₀ , e...signals in registers, f, g, h...separated low-order digital signals.

Claims

[Scope of utility model registration request]

In a digital signal separation circuit that separates a byte-multiplexed high-speed high-order digital signal into byte-based low-order digital signals, 8×n bits of the high-order digital signal are stored by shifting the high-order digital signal using a clock. The 8×n stage shift register circuit and the latch clock having a frequency of 1/8 of the clock
The contents of the ×n-stage shift register circuit are stored in a memory in bytes, and the contents of the memory are shifted and read out using a shift clock obtained by dividing the frequency of the clock to 1/n, thereby separating the contents in bytes. n parallel/serial conversion circuits that output low-order digital signals; monitor the low-order digital signals separated into bytes output from the n parallel/serial conversion circuits; When the digital signal is mixed with bits of a lower digital signal separated into other bytes, a monitoring circuit outputs information for eliminating the mixing, and the clock is sent to the 8×n stage shift register circuit. , the latch clock and shift clock are respectively supplied to the parallel/serial conversion circuit with memory, and the low-order digital signal separated into bytes is not mixed with bits of low-order digital signals separated into other bytes. and a clock control circuit that supplies the clock as it is to the 8×n stage shift register circuit and, when receiving information from the monitoring circuit, stops sending out the clock for a time indicated by the information. A digital signal separation circuit characterized by: