JPH02220097A - Image data display system - Google Patents

Abstract

PURPOSE:To output image data which is generated by optional reduction, enlargement, rotation and deformation to a graphic display device or character display device in real time without using any processor by inputting the coordinate conversion coefficient of a window. CONSTITUTION:An address (Xmin,Ymin) on a bit map memory 11 corresponding to the left upper coordinates of the window and the reduction rate of an image plane are inputted as address initial values to address generating circuits 15 and 16. The clock which is obtained by a clock generating circuit 12 is inputted to an X-directional address generating circuit 15 to generate a memory address (X address) synchronized with an X-directional screen scan. A Y-directional address generating circuit 16 generates a memory address (Y address) synchronized with a Y-directional screen scan. Consequently, the start coordinate values and reduction rate of the window are inputted to the address generating circuit to output image data in a window with an optional reduction (enlargement) rate directly from the bit map memory in real time.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an image data display method in an image data display device such as a graphic display (prior art); When displaying, if all the image data is displayed, detailed parts will not be visible, so it is necessary to cut out and display a part of the image data.Second.
As shown in the figure, the area on the display screen where image data is displayed is called a viewboard, and the area on the bitmap memory of the corresponding image data is called a window.

The image data in the window is displayed on the display screen, so if you change the start position of the read address in the bitmap memory and move the window, the figure on the screen will move, and if you change the read interval of the address and move the window. By changing the size of , you can enlarge or reduce the displayed figure.

Conventionally, when displaying image data in an arbitrary area of a bitmap memory on a display screen, a method as shown in FIGS. 9 and 10 has been adopted.

FIG. 9 shows a method in which image data in a window of a bitmap memory is temporarily stored in a frame memory in one-to-one correspondence with a display screen, and then displayed on a display from the frame memory. In FIG. 9, a bitmap memory 91 stores image data. CPU
92 is first.

The address of the bitmap memory 91 is generated, and the image data in the corresponding window is read from the bitmap memory 91 and stored in the frame memory 93. The frame memory 93 has a one-to-one correspondence with the display screen. The clock generation circuit 94 generates a reference clock that is the basis for scanning the display screen, and in response to this clock, the synchronization signal generation circuit 95 generates a vertical/horizontal synchronization signal (SYN) and a horizontal retrace signal (H) for the display screen. , generates a vertical retrace signal (V), etc.

The display counter 96 counts the display lines on the screen based on the horizontal retrace signal (H) and the vertical retrace signal (V). C
The PU 92 inputs the clock of the clock generation circuit 94 and the count value of the display counter 96, generates an address corresponding to the display position on the screen in synchronization with the display scan of the display screen, and reads image data from the frame memory 93. , the parallel-serial conversion circuit 97 converts the read image data into a serial image signal synchronized with the clock of the clock generation circuit 94, and the mixing circuit 98 converts the serial image signal and the synchronization signal of the synchronization signal generation circuit 95. (SYN) and outputs it to the display.

FIG. 10 shows an address generation circuit that operates in synchronization with the screen display, which generates in real time the address on the bitmap memory where the image data to be displayed on the display screen exists, and the image data read out from the p1-map memory. This is a method that directly outputs the video signal as a video signal. Similarly to FIG. 9, the clock generation circuit 102 generates a reference clock, and in response to this clock, the synchronization signal generation circuit 103 generates a vertical/horizontal synchronization signal (SYN), a horizontal retrace signal (H), and a vertical retrace signal (H) for the display screen. Generates a return signal (V), etc. The address generation circuit 104 is connected to the clock generation circuit 102.
inputs the clock and the horizontal/vertical retrace signal of the synchronization signal generation circuit 103, and generates in real time an address on the bitmap memory 101 corresponding to the display position on the screen in synchronization with the display scan of the display screen. A bit selector 105 that reads image data from the bitmap memory 101 sequentially selects bits in the image data read from the bitmap memory 101 under the control of the address generation circuit 104 to generate a serial video signal, and outputs the bits to the mixing circuit 1.
06 mixes the serial image signal and the synchronization signal (SYN) and outputs the mixture to the display. FIG. 11 shows a specific example of the address generation circuit 104, and for convenience, only the X address generation circuit portion is shown. Register 1102
, the value of the X coordinate at the top left of the window is initialized in synchronization with the horizontal retrace signal. Then, synchronized to the clock,
The adder 1101 adds the value indicating the predetermined address interval (enlargement/reduction ratio) and the output value of the register 102, and the operation of storing it in the register 102 is repeated. At this time, the output of the register 102 is Indicates the bitmap memory address (X address) synchronized with scanning. Similarly, X addresses can also be generated, and these X addresses and X addresses are combined and applied to the bitmap memory 101.

[Problem to be solved by the invention]

In the method shown in Figure 9, the arrangement of screen display data is the same as the display screen.
Since it supports one-to-one display, a single display circuit can be easily constructed without requiring high-speed elements, so it has the advantage of being inexpensive. It requires data to be stored in the frame memory, which has the disadvantage of slow response.

On the contrary, the method shown in FIG. 10 outputs the image data directly from the bitmap memory, so a very fast response speed can be obtained. However, if an address generation circuit as shown in FIG. 11 is used to generate addresses in synchronization with screen display, the screen magnification is limited to an integer multiple, making it impossible to freely specify a window. In order to make arbitrary windows possible, it is necessary to generate addresses at decimal intervals. Conventionally, the only way to do this was to use a processor capable of numerical calculations, but general processors have limited speed. It has the disadvantage that it is too slow and requires a very fast processor such as a DSP, resulting in a very high cost.

An object of the present invention is to provide a method for displaying image data in an arbitrary window on a bitmap memory at high speed using an inexpensive circuit.

[Means to solve the problem]

In order to achieve the above object, the image data display method of the present invention includes a built-in rate multiplexer whose division ratio is controlled by inputting the decimal part of the address interval designation data. Address generation means capable of generating addresses on the bitmap memory corresponding to the display position above at decimal intervals is provided, and the image data read from the bitmap memory is displayed on the display screen based on the address generated by the address generation means. It is characterized by being displayed directly on top.

[For production]

In the present invention, as in the method shown in FIG. 10, an address on the bitmap memory where data to be displayed exists is generated in real time by an address generation means synchronized with the screen display, and the address on the bitmap memory is outputted from the bitmap memory. Data is displayed directly on the display screen, but addresses are generated in synchronization with the display on the screen by using an address generation means that allows address intervals to be specified using decimal numbers. Supports windows with enlargement and reduction ratios.

〔Example〕

First, the address generation circuit used in the present invention will be explained.

FIG. 3(a) is a schematic diagram of the present address generation circuit, in which adders 31. Rate multiplexer 32 and register 33
Consisting of The ratio of the display area (window) on the bitmap memory in which image data is stored to the display area (viewboard) on the screen is the enlargement/reduction ratio of the image data. The address interval designation data corresponds to this reduction ratio, and its data structure is assumed to consist of an integer part and a decimal part so that it can correspond to a window with any enlargement or reduction ratio. The integer part of this address interval specification data is input to the adder 31, and the decimal part is input to the rate multiplexer 3.
2 input. The adder 31 adds the integer part of the address interval designation data to the output of the register 33 when the output of the rate multiplexer 32 is "O", and adds the integer part of the address interval designation data to the output of the register 33 when the output of the rate multiplexer 32 is "1". The integer part of the address interval designation data and the "1" output of the rate multiplexer 32 are added.

The output of this adder 31 is loaded into the register 33 at the next clock. The rate multiplexer 32 is a type of splitter, and its splitting ratio is controlled by the decimal part of the address interval designation data.

FIG. 3(b) shows a circuit example of the rate multiplexer 32, in which 321 is a 4-bit binary counter;
2 is an AND-OR circuit. The binary counter 321 is counted up by a clock, and one cycle is 24 pulses (16 pulses).
When inputted to the AND-OR circuit 322 together with J, the corresponding A
The output of the ND-OR circuit 322 becomes "1" only during a period that matches the decimal part J, .about.J, within one period (24 pulses) of the counter 321.

An example of the operation of the present address generation circuit shown in FIG. 3(a) is shown in FIGS. 4 and 5.

FIG. 4 shows an example of operation when the water ratio is 7.3 (hexadecimal). The adder 31 adds 7" to the output (a) of the register 33 when the output (c) of the rate multiplexer 32 is "0", and adds 7" to the output (a) of the register 33 when the output (C) of the rate multiplexer 32 is n 1 n. , the output of register 33 (a
) and "7+1=8" is output. The output of this adder 31 is loaded into the register 33 at the next clock.

In this example, the output (c) of the rate multiplexer 32 outputs "1" only three times within one period (24 clocks) of the counter 321, so the average increase rate of the register value (a) is Cea). As shown (7* (2'-3)+
(7+1) umbrella 3)/2'=7+372'=7.3(16
In addition, the error at this time is always less than 1, as shown in (f).

Figure 5 shows the reduction ratio = 0.4 (hexadecimal), or the enlargement ratio 11.
This is an example of operation when 0.4 (hexadecimal)=4.

As in the case of the reduction ratio of 7.3 in FIG. 4, when the output (0) of the rate multiplexer 32 is "O", the adder 31 adds "0" to the output (a) of the register 33.d) When the output (C) of the rate multiplexer 32 is "1", the value obtained by adding "1" to the output (a) of the register 33 is output, so the counter 32 of the rate multiplexer 32
"1" is added only four times within one period (24 clocks) of 1 (d), and the average increase rate of the register value (a) is (01(2'-), as shown in (e). 4) + (1)
-4)/2'=4/2'=0.4 (hexadecimal), and the error at this time is 1 or less as shown in (f).

As described above, by using the address generation circuit shown in Figure 3, the integer part is added each time in either enlargement or reduction, and the decimal part is added at a timing such that the accumulated error does not exceed 1. Since they are added, addresses at arbitrary intervals can be generated while maintaining an error of 1 or less.

Embodiments of the image data display method of the present invention will be described below.

FIG. 1 is a block diagram of a first embodiment of the image data display method of the present invention. In FIG. 1, 15 and 16 are the address generation circuits explained in FIG. 3, 15 is the address generation circuit in the X direction, and 16 is the address generation circuit in the Y direction. This is an address on the bitmap memory 11 corresponding to the display position on the screen synchronized with the scanning of the display screen. Bitmap memory 1
1 stores image data. The clock generation circuit 12 is a circuit that generates a reference clock that is the basis for scanning the display screen, and the synchronization signal generation circuit 13 receives this clock and generates a vertical/horizontal synchronization signal (SYN) and a horizontal retrace signal (H ), vertical synchronization signal (V), etc. The mixing circuit 14 is a circuit that mixes a synchronization signal (SYN) output from the synchronization signal generation circuit 13 with the image data read out from the bitmap memory 11 by the address generation circuits 15 and 16 in synchronization with the scanning of the display screen. .

The address generation circuits 15 and 16 have the address (Xmin, Y in) on the bitmap memory 11 corresponding to the upper left coordinates of the window and the corresponding dot on the bitmap memory as the initial address value. The interval, that is, the reduction ratio of the screen is input. The clock obtained by the clock generation circuit 12 is input to the X-direction address generation circuit 15 and at the same time, the synchronization signal generation circuit 13! is input, and generates a horizontal retrace signal (H), a superimposed retrace signal (V), and a horizontal/superimposed timing signal (S Y N). The X-direction address generation circuit 15 generates Xm for each horizontal retrace signal (H).
1n is loaded and the screen reduction rate (dot spacing) is added for each clock input to generate a memory address (X address) synchronized with screen scanning in the X direction. The X-direction address generation circuit 16 loads Y win for each vertical line signal (V), adds the screen reduction rate (dot interval) according to the horizontal retrace signal (H), and performs screen scanning in the Y direction. Generate a synchronized memory address (Y address). The outputs from these two address generation circuits 15 and 16 are combined and
, a memory address on the bitmap memory 11 corresponding to the display position synchronized with screen scanning in the Y direction, and this is input to the bitmap memory 11. As a result, image data within a window synchronized with screen scanning is sequentially read out from the bitmap memory 11. The mixing circuit 14 mixes a horizontal/vertical synchronizing signal (SYN) with the image data from the bitmap memory 11.
Output to the display as a video signal.

As described above, by inputting the window start coordinate value and reduction rate to the address generation circuit, the image data in the window at any reduction (enlargement) rate can be output directly from the bitmap memory in real time without using a processor. can do.

FIG. 6 is a block diagram of a second embodiment of the image data display system of the present invention, showing an embodiment used in addition to a general display circuit. In FIG. 6, 61 is a general character and graphic display circuit, and in addition to the video signal (Video), a dot clock (Dot) is used for synchronizing the image data display addition circuit 62.
Horizontal synchronization (H) and vertical synchronization (V) signals are output. The image data display addition circuit 62 includes an address generation circuit 621. which generates an address on the bitmap memory in synchronization with display scanning of the screen. It is comprised of a bitmap memory 622 in which image data is stored, and a video signal mixing circuit 623 that mixes the image data output from the bitmap memory 622 with the video signal output from the character/graphic display circuit 61.

The address generation circuit 621 is constructed by combining four basic blocks 621-1 to 621-4, as shown in FIG. FIG. 8 is a detailed diagram of one basic block, which is composed of an addition base 81, a rate multiplexer 82, and a register 83. When specifying one display area corresponding to FIG. 3, the coordinates on the display screen are (xt y), the corresponding address (coordinates) on the bitmap memory 622
Assuming (x, y), the affine transformation is expressed as . Therefore, in normal display without transformation and 6 rotations in which the display window is specified by the transformation coefficient a □ ~ aas, a
ll=all=screen reduction rate, a1a=as□=0, (a
z□t aaz) = coordinate value of the upper left corner of the window.

Therefore, with one address generation circuit 621, screen enlargement,
In addition to reduction, deformed display through rotation and linear transformation is also possible.

Hereinafter, the X coordinate on the 0 display screen to explain the operations in FIGS. 6 and 7 is the character/graphic display circuit 61.
It becomes O when a horizontal synchronizing signal (H) is output from , and increases by one for each dot clock (Dot). Also,
The Y coordinate becomes 0 when the vertical synchronization signal (V) is output, and increases by 1 each time the horizontal synchronization signal (H) is output. The address generation circuit 621 generates a vertical synchronization signal (V)
When received, the initial value a of X is set in the basic block 621-1.
, 1.621-3 basic block is loaded with the initial value a3□ of Y. Since the horizontal synchronization signal (H) is also input to the address generation circuit 621 at the same time, 621-2, 621
The same value is loaded into the -4 basic block, and the initial values of the X and Y addresses are output. Dot Clock (Dot
) is input, the basic block 621-2 adds the X component a11 of X to the output, and the basic block 621-4 adds the X component a□8 of Y to the output. Then, when the horizontal synchronization signal (H) is input, 621-1, 621-3
The basic blocks 621-1 and 621-5 each add the Y components of X and Y, and the basic blocks 621-1 and 621-5 load the outputs as initial values. As a result, the basic block 621
-2,621-4 output X.

The address of the bitmap memory 622 synchronized with the display scanning of the character/graphic display circuit 61 is obtained as Y. By inputting this address to the bitmap memory 622 and mixing the image data output from the bitmap memory 622 with the video signal output from the display circuit 61 in the mixing circuit 623, the character/graphic display circuit 61 The image data in the bitmap memory 622 is displayed superimposed on the output video signal.

As described above, by inputting the coordinate transformation coefficients of the window, image data at any reduction (enlargement, rotation, and transformation) can be output to a graphic display device or character display device in real time without using a processor. . Further, when adding one circuit 62, it is sufficient to extract the synchronization signal from the existing graphic display device or character display device, and there is an advantage that no major modification is required.

〔Effect of the invention〕

As explained above, according to the image data display method of the present invention, image data in an arbitrary window on a bitmap memory can be displayed with a simple configuration without using a processor, and one When zooming or moving the display area, display can be performed in real time by simply providing desired window information (coordinates, reduction ratio). Further, even when applied to a conventional graphic display device or character display device, modification to extract the synchronization signal is sufficient, and there is an advantage that no major modification is required.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a first embodiment of the image data display method of the present invention, FIG. 2 is a diagram showing the relationship between the window on the bitmap memory and the view board on the display screen, and FIG. 3 is a diagram of the first embodiment of the image data display method of the present invention. 4 and 5 are diagrams illustrating an example of the operation of the address generation circuit of FIG. 7 is a block diagram of the second embodiment of the image data display method, FIG. 7 is a block diagram of the address generation circuit of FIG. 6, FIG. 8 is a detailed diagram of the basic block of FIG. 7,
9 and 10 are diagrams showing an example of the configuration of a conventional image data display system, and FIG. 11 is a detailed diagram of an address generation circuit used in the first o'yJ. 11...Bitmap memory, 12...Clock generation circuit. 13... Synchronization signal generation circuit, 14... Mixing circuit. 15.16...Address generation circuit, 31...Adder, 32...Rate multiplexer, 33...Register. *1r! lJ Fig. 3 c (L) Fig. 6 H ++ ++ 1 Fig. 7 Fig. 8 Fig. 9 Fig. 10

Claims (1)

[Claims] (1) In a method of reading image data from an arbitrary area on a bitmap memory and displaying it on the display screen, a built-in rate multiplexer whose frequency division ratio is controlled by inputting the decimal part of the address interval specification data is used. Address generation means capable of generating addresses on the bitmap memory corresponding to the display position on the screen at decimal intervals in synchronization with display scanning is provided, and the bitmap memory is generated based on the addresses generated by the address generation means. An image data display method characterized by displaying image data read out directly on a display screen.