JPH02220144A - Functional verification circuit simulator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to a simulator for verifying an integrated circuit device in which digital circuits and analog circuits coexist.

2. Description of the Related Art Simulators for performing various verifications including functional verification of integrated circuits such as LSIs have conventionally performed circuit simulations at the transistor level even in digital circuit sections.

Note that even simulators that verify broader blocks than at the transistor level can only handle element models or function blocks such as filters.

Problems to be Solved by the Invention Therefore, even when verifying an LSI that includes a mixture of digital circuits and analog circuits that include multi-gate logic sections, simulation cannot be performed unless all of the circuits are at the transistor level. Competency verification took a lot of time.

The present invention aims to realize a circuit simulator that can significantly improve the circuit verification speed of the entire analog-digital mixed circuit.

Means for Solving the Problems In order to achieve the above-mentioned object, the simulator of the present invention is a simulator of a circuit device in which digital circuits and analog circuits are mixed, and in which at least a part of the digital circuit is regarded as one block. Specify the input terminal and output terminal of the simulator, load the functional description that describes data indicating the signal to be applied to the input terminal and the signal obtained from the output terminal into the simulator, and output the signal to the output terminal described in the above functional description. This signal is then used to simulate an analog circuit.

Operation With the above configuration, verification within the block specified by the functional description of the digital circuit section is not performed at the transistor level, and the output signal corresponding to the input signal specified by the functional description is sent to the output terminal of the block. The analog circuit performs an operation simulation according to the signal obtained at the output terminal of the block. Since transistor-level simulation is not performed for blocks designated in this way, the time required for functional simulation of the digital section in a mixed circuit of digital circuits and analog circuits can be significantly reduced.

Embodiment In a circuit simulator 30 shown in FIG. 1, a netlist is input into the simulator 30, which describes various specifications such as element names and connection relationships used in an LSI (Large-Scale Integrated Circuit) to be verified. The list reading unit 31 includes a standard model reading unit 32 that reads a netlist for a standard model, a user-specified functional description reading unit 33 that inputs functional descriptions such as those shown in Tables 1 and 2, and stores functional descriptions. The user library 34 is also provided with a user library 34 for

Tables 1 and 2 are functional descriptions of the necessary inputs and outputs of the digital circuit 50 of the circuit to be verified as shown in FIG. 2, for example, divided into blocks. The digital circuit 50 is composed of a detailed circuit including transistors, etc., and this is represented as a block, and its input terminals 1 to 3,
The focus is only on output terminals 4 to 6.

A transient analysis control section 40 that performs control for simulating the transient operation of the digital circuit 50 includes a standard model operation analysis section 41 and a functional description operation analysis section 42.

Similar to other known LSI circuit simulators, the netlist check section 51. AC to analyze the AC characteristics of Li
analysis unit 52, a DC analysis unit that analyzes the DC characteristics of the LSI;
It is provided with a result output section 54 for displaying simulation verification results on a CRT or printing them on a printer, and a circuit simulator main control section 55.

Table 1 FMODEL digl INPUT, 1 2 3 4 OUTPUT 5 6 Table 2 MoDEL NAME HIGHLEVEL Low LEVEL THRESHOLD RISE TIME FALL TAME 1g1 5V (Old potential) OV (L potential at O) 2.5V (input signal threshold Hold potential) 5 (Rise time of output signal) 5 (Fall time of output signal) if (LEVEL(lo) = = old GHto Lo)s
et output (Oo, tll, 10): In the above, old and IIIGH indicate high level, and Lo and Low indicate low level.

Table 3 Y=O (0≦t<10) y=t-10 (10≦t×15) The operation of the above simulator will be explained.

For example, assume that a netlist of a circuit including a digital circuit 50 and an analog circuit 60 as shown in FIG. 2 has been input to the simulator.

At this time, it is assumed that the digital circuit 50 is stored in the user file 34 with the file name digl.

By storing the input information shown in Table 1 for the circuit shown in FIG. 2 in the user file 34, the simulator regards nodes 1 to 6 as the I10 nodes of the functional description model, and uses the functional description during transient analysis. The above nodes 1 to 6 are stored in the user file 34 as flags used for execution.

The format of the functional description is conceptually the same as the functional description used in logic simulation, and the functional description is performed as shown in Table 2 for the expected input/output pattern as shown in FIG. The following if statement in Table 2 indicates that "if pin 10 falls from Hl to LO, the output of the Oo bin will start rising 10 ns later." When compared with Fig. 3, 10nS is the value from t0 to tI, and RISE 'rIME 5ns is the value from t+ to t
The values up to t are shown.

After the simulator reads the netlist, the functional description in Table 2 is read from the file with the same name as the circuit name digl, converted as an output signal of the time function representing the waveform in Table 3, compiled, and stored in the user library 34. Stored.

For analysis, either install a control section in the transient analysis section as shown in Figure 2 and have it perform normal matrix calculations, or
Allow the user to choose whether to proceed to the operation described in the function description. In the netlist based on the standard model, normal calculations are performed, and if convergence is achieved at each step, the behavior analysis section of the standard model is extracted. In the functional description netlist, the transient analysis control unit 40 calls the operation of the compiled functional description from the user library 34 and sends the values scheduled in Table 2 to the output node 4 of the digital circuit 50.
, 5.6 directly. And this output node 4,
5. A simulation is performed by applying the value output in step 6 to the analog circuit 60, and the operational function of the analog circuit 60 is verified.

As described above, according to the present invention, the digital part in an analog/digital mixed circuit is not treated at the transistor level, but as a functional block as shown in Figure 2.On the other hand, the block configuration of the conventional simulator as shown in Figure 1 can be used. Among them, a functional description reading section and a functional description behavior analysis section are newly added to the netlist reading section and the transient analysis section, respectively, and the simulator 30 shown in FIG. Once recognized, the content of the functional description is read and compiled, the entire netlist is divided into the functional description part and others and stored in the functional description analysis part, and during analysis, the operation of the functional description part and other standard circuits is analyzed at each step. respectively. The function description unit digitizes the input signal in the timing chart as shown in Figure 3.The function description operation analysis unit digitizes the input signal
By setting the scheduling of output signals due to rLo changes as a time function in the functional description behavior analysis section, the signal transmission time in the digital circuit section can be significantly reduced, and the circuit verification speed of analog circuits including multi-gate logic can be greatly improved. It is something that makes you

Effects of the Invention As detailed above, when verifying an integrated circuit that includes a mixture of digital and analog circuits, the simulator uses the digital circuit section specified in the functional description not as details at the transistor level, but as a single functional block. By handling the block and outputting the signal specified by the function description to the output terminal of the block and applying this output to the analog circuit to verify the analog circuit, it is now possible to simulate the digital circuit at high speed. Therefore, the required signal can be transmitted to the analog circuit at high speed,
As a result, verification of analog circuits can be speeded up.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a circuit diagram showing an example of a circuit in which digital circuits and analog circuits are mixed, and the digital circuit is divided into blocks. FIG. 3 is a waveform diagram showing an example of input signals and output signals in a digital circuit that is divided into blocks. 1.2.3... Input node 4.5.6... Output node 30... Simulator 31... Netlist reading unit 32... Standard model reading unit 33... User specified function description reading Section 34...User library 40...Transient analysis control section 41...
・Standard model behavior analysis unit 42...Functional description behavior analysis unit 50...Blocked digital circuit 60...Analog circuit

Claims (1)

[Claims] (1) In a simulator of a circuit device in which digital circuits and analog circuits are mixed, at least a part of the digital circuit is regarded as one block, the input terminal and output terminal of the block are specified, and the voltage is applied to the input terminal. signal,
A function characterized in that a functional description describing data indicating a signal obtained at an output terminal is loaded into the simulator, a signal is output to the output terminal described in the functional description, and an analog circuit is simulated using this signal. Verification circuit simulator.