JPH02220161A - Interruption accepting circuit - Google Patents

Abstract

PURPOSE:To accept an interruption at a high speed by using a random access memory a (RAM) to store a desired identification (ID) code and a deciding means to compare the identification code of an external interruption request with the identification code stored in a memory. CONSTITUTION:A RAM 11 which stores a desired ID code is added to a circuit part containing a setting switch or a reference ROM in order to decide an internal or external interruption request. A deciding means MPU compares the ID code of the external interruption request with an ID code stored in a memory 11 to attain a software programming operation. Thus an internal or external interruption request is discriminated with a soft system constitution. Then the waste time is eliminated with an internal interruption request and an interruption can be accepted at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to an interrupt acceptance circuit that processes vector interrupts in a computer system, and particularly relates to an interrupt acceptance circuit that can distinguish between internal interrupt requests and external interrupt requests. .

B6 Summary of the Invention The present invention provides, in an interrupt reception circuit that processes vector interrupts of a computer system, a random access memory that stores a desired identification code, and a determination means that compares the identification code of an external interrupt request with the identification code in the memory. By providing this, it is possible to determine whether an internal interrupt request is an external interrupt request, there is no wasted time in the case of an internal interrupt request, and the processing speed of interrupt reception is increased, thereby providing a technology that improves total performance. It is.

C1 Prior Art FIG. 3 is a block diagram showing an example of a computer system, in which a master module group 311.31-2.31-3 containing a microprocessor (hereinafter abbreviated as MPU) is shown.
... and a slave module group 32-1 configured as an interface for various input/output devices or storage devices, etc.
32-2 to 32n... are connected by a multi-master bus 33.

FIG. 4 is a configuration diagram showing an example of hardware when interrupt processing is performed between the master module and slave module shown in FIG. 3.

In FIG. 4, the left side shows hardware that processes interrupts of one master module, and the right side shows a hardware group that processes interrupts of a slave module group. The operation of processing a vectored interrupt using the 71-ware having the configuration shown in the figure is as follows.

In the figure, slave interrupt controller 42-1゜42-2
．． 42-3... are arranged in the slave modules 32-1, 32-2... shown in FIG.
The multi-mask bus 43 is the same as the multi-master bus 33 described above.

Each slave interrupt controller 42-1.42-2.4
2-3... receives an interrupt request from n interrupt elements, detects from which interrupt element the interrupt request is generated, and stores the vector (1
A byte of data indicating the address on the interrupt program corresponding to the element requesting the interrupt is generated. For example, when slave interrupt controller 42-1 receives an interrupt request from any interrupt element, it outputs an interrupt request signal to interrupt level setting jumper 45 via multi-mask bus 43 and external interrupt element signal line 44a. The external interrupt element signal lines 44a are provided in a number corresponding to the number n of external slave modules, and are used to identify which external slave module requests an interrupt.

An internal slave interrupt controller 46 is also connected to the interrupt level setting jumper 45 . This internal slave interrupt controller 46 controls interrupts from the slave inside the master module, and has internal interrupt element signal lines 44b corresponding to the number of interrupt elements, and receives an interrupt request signal. and outputs the interrupt vector.

When an interrupt is received from an external or internal slave, the interrupt level setting jumper 45 reports the request to the mask interrupt controller 47. At this time, the interrupt level setting jumper 45 determines which interrupt is to be prioritized by considering a predetermined interrupt priority given to each slave in advance, and signals the level (0 to n) corresponding to the selected slave. An interrupt request signal is output to the mask interrupt controller 47 via the line.

The mask interrupt controller 47 sends the interrupt request signal to P.
Output to MU48.

The PMU 48 executes an interrupt acknowledge cycle, and when the interrupt is ready, the local bus controller 4
9, an interrupt acknowledge signal is outputted to the masked interrupt controller 47 and the internal slave interrupt controller 46, and further outputted to the external system bus controller 50.

The external system bus controller 50 is provided with an external vector/internal vector setting switch 51. The setting switch 51 is used to select whether the interrupt control is for the internal slave alone or for both the internal slave and the external slave.When interrupt control for the internal slave alone is selected, the switch operation causes the external system to be controlled. The bus controller 50 does not output an interrupt acknowledge signal to the signal line 52 to the multi-master bus 43, but outputs "Low" to the buffer 53 and the inverter 54. Therefore, the buffer 53 closes its gate, and the buffer 53 closes its gate.
5 opens the gate. When the gate of buffer 55 opens,
Internal slave interrupt controller 46 designated by an identification code (hereinafter referred to as ID code) to be described later
The vector output from
It is taken into the MPU 48. When interrupt control for both an internal slave and an external slave is selected, two types of processing are performed: accepting an interrupt from the external slave and accepting an internal interrupt. FIG. 5 is a time chart showing these timings.

(1) When accepting an interrupt from an external slave, the external system bus controller 50 receives an interrupt acknowledge signal from the MPU 48 to
After gaining control of the multi-master bus 48 (this is done for other master modules) via At the same time, the gate of the buffer 5°8 is opened via the signal line 57, and the mask interrupt controller 47 selects any of the levels 0 to n output from the interrupt level setting jumper 45. The slave interrupt controller 42 of each slave receives the interrupt signal and outputs an ID code (3-bit data, 23=8) that identifies which slave the interrupt is from. -1.42-2.
42-3... The slave interrupt controller (42-1 in this example) corresponding to the ID code is
This signal recognizes that the interrupt of the own slave has been accepted, and furthermore, by receiving the interrupt acknowledge signal, the vector corresponding to the interrupt element requesting the interrupt in the own slave is multi-masked. The data is output to the buffer 53 via the bus 43. Since the gate of the buffer 53 is opened by the external system bus controller 50, this vector is taken into the MPU 48 as is. Note that at this time, the gate of the buffer 55 is closed.

(2) When accepting an internal interrupt, when an interrupt acknowledge signal is transmitted from the MPU 48 to each control section, as shown in FIG.
The external system bus controller 50 starts outputting the D code and gains control of the multi-master bus 43.

The decoder 59 shown in FIG. 4 receives this ID code,
When determining whether the interrupt is an internal slave interrupt or an external slave interrupt, and determining that the interrupt is an internal slave interrupt, a command to that effect is given to the external system bus controller 50.

Since this command has priority over the settings made by the setting switch 5I, when the external system bus controller 50 receives the second interrupt acknowledge signal that is re-outputted after the MPU 48 acquires control of the multi-master bus 43, the corresponding The controller 50 performs the same “
“Low” output, etc., and the internal slave interrupt is M
Accepted by PU48.

D1 Problems to be Solved by the Invention In the above conventional circuit, the setting switch 5! When the external interrupt vector is set to the internal/external slave interrupt side to enable reading of the external interrupt vector, the timing sequence for reading the internal interrupt vector is as shown in FIG. In this case, even though there is no need to acquire control of the external system bus 50 when reading the internal interrupt vector, control of the external system bus 50 is uniformly acquired because it cannot be determined whether it is an internal interrupt or an external interrupt. It looks like this. To accept external interrupts, use the interrupt controller 42-1.42 on the external slave side.
-2... It is determined which interrupt element the interrupt request comes from by checking the registers, but this operation has to rely on software, which not only increases the load on the MPU but also wastes time. , it takes extra time to read the internal interrupt vector, causing performance degradation.

On the other hand, if the setting switch 51 is set to the internal slave interrupt side, it becomes impossible to read the internal interrupt vector.

In order to correct this drawback, a contrivance has been proposed in which a portion corresponding to the external system bus controller 50 and its setting switch 51 shown in FIG. 4 is configured as shown in FIG. 7. In this device, the ID code (cascade address) of the judgment criterion is stored in the ROM 70 in advance,
It decodes the ID code output from the masked interrupt controller, compares it with the contents of ROM 70, determines whether it is an internal interrupt or an external interrupt, and reads the interrupt vector from the internal bus or external bus. . Although this method requires time to compare ID codes, it does not have much of an impact compared to the time it takes to gain control of the multi-mask bus. However, with this method, an ID code that is recognized as an external interrupt must be prepared in the ROM 70 in advance, so when the interrupt level is changed using the interrupt level setting jumper, the ROM must be replaced with a corresponding ROM. Therefore, the ROM must be replaced every time the interrupt level is changed, making it difficult to build a flexible system.

The present invention was created in view of these problems, and
To provide an interrupt reception circuit that can distinguish between internal and external interrupt requests through flexible system construction, eliminates wasted time in the case of internal interrupt requests, speeds up interrupt reception processing, and improves total performance. It is an object.

80 Means for Solving the Problems The means for solving the above problems in the present invention are provided in a master module connected to an external slave module to a multi-master bus, and whether an interrupt request is an external interrupt request or an internal interrupt request. After determining the external interrupt request, the interrupt acceptance circuit reads the interrupt vector in the second interrupt acknowledge cycle from the microprocessor. The interrupt reception circuit includes a determination means for comparing the identification code of the interrupt reception circuit with the identification code of the interrupt reception circuit.

F0 action The interrupt reception circuit of the present invention uses a setting switch or a reference ROM to determine whether an internal interrupt request or an external interrupt request is required.
Random access memory (hereinafter abbreviated as RAM) that stores a desired ID code in the circuit section where the
The determining means compares the ID code of the external interrupt request with the ID code in the memory to enable programming by software.

The RAM of the present invention is connected to the external system bus controller shown in the conventional example, and its ID code is set for external interrupt requests, and all other requests can be processed as internal interrupt requests. Internal interrupt requests are given priority even if they are not limited by hardware such as
In addition, it is always ready to accept interrupt requests from both internal and external sources.

By using RAM, it is possible to use software, and moreover, it is possible to construct a system more flexibly than when using ROM. The determining means may be provided integrally as a peripheral circuit of the RAM.

G. Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a configuration diagram of an embodiment of the present invention.

The interrupt acceptance circuit of this embodiment is applied in the master module explained in FIG. 4, and the external system bus controller 10 in the figure corresponds to the controller 50 of the same name in FIG. It receives an interrupt acknowledge signal and controls whether or not to relay it to the multi-master bus, and also controls sending of the interrupt vector from the multi-master bus to the MPU using an intermediate buffer. R.A.
M11 is designated with an address (ADRS) from multiplexer 12 that compares the ID code and MPU address,
The data outputs (DO to D7) are input to the external system bus controller 10 via the OR gate I3. The data output is also connected to the MPU data bus (DO-D7) via buffer I4, and a match between the two is detected. The gate of the buffer 14 is closed by a write signal from the MPU, and the write signal is also input to the write enable terminal of the RAM II. Further, the vector ID rewrite selection signal and the interrupt acknowledge cycle signal are negative selected and instructed by the NOR gate 15 to the C8 terminal of the RAMI 1. Incidentally, these constitute the determination means of the present invention as a peripheral circuit of the RAM 1l.

FIG. 2 is a time chart of each signal in this embodiment.

This will be explained below with reference to FIG.

The operation of accepting external interrupts in this embodiment is as follows.

(1) In the initialization program after the MPU is reset, enter the ID code of the external interrupt request corresponding to the level set by the interrupt level setting jumper in RAMI
Write it in.

(2) An interrupt request is generated from the slave interrupt controller connected to the multi-mask bus, and is notified to the MPU through the mask interrupt controller.

(3) The MPU executes the first interrupt acknowledge cycle and freezes the state of the interrupt controller.

(4) The masked interrupt controller that receives this interrupt acknowledge cycle outputs an ID code.

(5) When this ID code matches the ID code of the external interrupt request stored in RAMI I, a bus use request signal is output to the multi-master bus.

(6) When the external system bus controller IO obtains control of the multi-master bus, one
A second interrupt acknowledge signal is output, freezing the state of the slave interrupt controller and terminating its interrupt acknowledge cycle.

(7) Execute a second interrupt acknowledge cycle and read the interrupt vector from the slave interrupt controller on the multi-master bus.

(8) The MPU executes processing according to the read interrupt vector.

Further, the operation of accepting an internal interrupt in this embodiment is as follows.

(1) In the initialization program after the MPU is reset, the ID code of the external interrupt request corresponding to the level set by the interrupt level setting jumper is stored in the RAM.
Write it down in I.

(2) An internal interrupt request is generated and notified to the MPU via the masked interrupt controller (the internal interrupt request may be an internal slave interrupt controller).

(3) The MPU executes the first interrupt acknowledge cycle and freezes the state of the interrupt controller.

(4) The masked interrupt controller that receives this interrupt acknowledge cycle outputs an ID code.

(5) Since this ID code does not match the ID code of the external interrupt request stored in the RAM 11, the interrupt acceptance cycle is executed only internally.

(6) In the second interrupt acknowledge cycle, read the interrupt vector from the internal masked interrupt controller (if the interrupt request is from the internal slave interrupt controller, read from the internal slave interrupt controller).

(7) The MPU executes processing according to the read interrupt vector.

In this way, in this embodiment, it is possible to determine whether it is an internal interrupt request or an external interrupt request, and in the case of an internal interrupt request, a waiting time is required until the ID code is output from the masked interrupt controller. However, since there is no need to acquire control of the external multi-mask bus, wasted time is eliminated and interrupt reception is processed faster.
Meanwhile, other masks can process on the multi-master bus, improving total performance.

Note that since a RAM is used in the ID code comparison section, there is no need to replace or rewrite the ROM even if the interrupt level jumper setting is changed.

As described in detail of the H1 invention, according to the present invention, it is possible to determine whether an internal interrupt request is an internal interrupt request or an external interrupt request with a flexible system construction, and there is no wasted time in the case of an internal interrupt request, and the interrupt acceptance processing can be performed easily. It is possible to provide an interrupt acceptance circuit that speeds up the process and improves total performance.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a time chart of the embodiment, Fig. 3 is a block diagram of a computer system, Fig. 4 is a block diagram of interrupt processing hardware, and Fig. 5 is a block diagram of an embodiment of the present invention. FIG. 6 is a time chart of the conventional example, and FIG. 7 is a configuration diagram of the conventional example. 10.50.70...Outside! '(System bus controller, ll...Random access memory (RAM),
12... Multiplexer, 13... OR gate, I
4...Buffer, 15...NOR gate, 33.4
3... Multi-master bus, 45... Interrupt level setting jumper, 46... Internal slave interrupt controller, 47... Mask interrupt controller, 48...
M.P.U. 49...Local bus controller. Figure 1: 2 people outside the ward Figure 2: Issuance of the present invention Time schedule for IJ Mart Figure 7

Claims (1)

[Claims] (1) A second interrupt acknowledgment from the microprocessor is provided within the master module that connects the external slave module to the multi-master bus, and after determining whether the interrupt request is an external interrupt request or an internal interrupt request.
An interrupt reception circuit that reads an interrupt vector in cycles, characterized by comprising a random access memory that stores a desired identification code, and a determination means that compares the identification code of an external interrupt request with the identification code in the memory. Interrupt reception circuit.