JPH02220430A - Semiconductor substrate and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent occurrence of dust when a semiconductor substrate is handled by coating the semiconductor substrate with resist with the exception of at least a peripheral part and the side face of an outer circumference and removing compound semiconductor layers at the above peripheral part and the side face of the outer circumference which are not covered with resist through etching treatment, thereby removing resist. CONSTITUTION:There is a compound semiconductor (GaAs) layer 3 on an Si single crystal wafer 2. Then the peripheral part of a substrate 1, the side face of an outer circumference, the rear of the substrate are free from the GaAs layer 3 and then a wafer 2 comes out on the surface. Then resist is applied on the semiconductor substrate (GaAs/Si substrate) with spin coating and its substrate is exposed through a prescribed mask pattern and is developed. Subsequently, the GaAs layer which is not covered with a resist layer is removed by the use of an etchant and after washing it with water, the resist layer that still remains is removed with an alkali developing solution and the semiconductor substrate 1 is obtained. In this way, a carrying arm, a holder, and the like do not come into contact with the above semiconductor layer and then an Si part that comes out on the surface comes into contact with its layer. This configuration decreases occurrence of dust and improves a yield of LSIs as well as light emitting devices that are manufactured into semiconductor substrates.

Description

[Detailed Description of the Invention] [Summary] Gallium arsenide (Ga) is deposited on a silicon (Si) single crystal wafer.
As), gallium aluminum arsenide (GaAIAs)
The purpose of the present invention is to provide a semiconductor substrate having a -V group compound semiconductor layer formed thereon, such as silicon single crystal, and a method for manufacturing the same, which does not generate dust when handling the substrate. A semiconductor substrate in which a compound semiconductor layer is formed on a wafer is configured such that the silicon single crystal wafer is exposed at least on the peripheral edge, back surface, and outer peripheral side surface of the substrate.

[Industrial application field]

The present invention produces gallium arsenide (GaAs), gallium aluminum arsenide (Ga) on a silicon (Si) single crystal wafer.
The present invention relates to a semiconductor substrate on which a ■-■ group compound semiconductor layer such as ARAs) is formed, and a method for manufacturing the same.

With the increase in computer speed in recent years, ultra-high-speed processing LSI
There is an increasing demand for this, and attempts are being made to use GaAs elements, which enable faster processing than Si elements. Furthermore, light emitting devices (L
Progress is also being made in manufacturing EDs (EDs, lasers) using compound semiconductors such as GaAs. A GaAs substrate cut from a single crystal ingot has drawbacks, such as being smaller, more brittle, having lower thermal conductivity, and being more expensive, than a Si substrate. Therefore, as an inexpensive and large-area substrate, Si
There is a strong demand for a GaAs on 5i (GaAs/Si) substrate in which a GaAs single crystal layer is formed on a single crystal wafer (Si substrate).

[Conventional technology]

To form a GaAs layer on a Si wafer, MOCV
A buffer layer (A RGaA
s-GaAs superlattice) or directly (e.g., top-convex, Akita = "S! GaAs superlattice, etc.)"
"Grow S film and create devices on it", Nikkei Microdevice, January 1986 issue, pp. 113-127
,reference).

GaAs or Ga1As I on a conventional S1 wafer
- The semiconductor substrate on which the V group compound semiconductor layer is formed is
i The front side of the wafer is entirely covered with GaAs (or Ga
p! -Almost no GaAs (or GaAj!As) layer is formed on the back side of the blade. However, when forming such a compound semiconductor layer, 8
The material that goes around the back side of the wafer is GaAs (GaA j
! As) growth (attachment).

[Problem to be solved by the invention]

GaAs or GaA I As has inferior mechanical strength and is very brittle compared to Si single crystal, so it is used in LSI
GaAs (
The GaA I As ) layer is damaged and dust is generated. In particular, the generation of dust increases as the diameter of the substrate increases and the weight increases.

An object of the present invention is to provide a semiconductor substrate with a compound semiconductor layer using a Si single crystal wafer that does not generate dust when the substrate is handled, and a method for manufacturing the same.

[Means to solve the problem]

According to the present invention, in a semiconductor substrate in which a compound semiconductor layer is formed on a Si single crystal wafer, the silicon single crystal wafer is exposed at least on the peripheral edge, back surface, and outer peripheral side of the substrate. The method for manufacturing the substrate is to form a compound semiconductor layer on the entire surface of a silicon single crystal wafer, and then cover at least the peripheral right side and outer peripheral side of the semiconductor substrate with a resist, and then cover the uncovered peripheral edge with a resist. The second step is to remove the compound semiconductor layer on the portion and outer peripheral side surface by etching, and then remove the resist.

Furthermore, according to another aspect of the present invention, in a semiconductor substrate in which a compound semiconductor layer is formed on a Si single crystal wafer, a silicon nitride layer formed on the silicon single crystal wafer is formed on at least a peripheral portion and an outer peripheral side surface of the substrate. A method for manufacturing the semiconductor substrate includes selectively forming a silicon nitride layer on the peripheral edge and outer peripheral side of a silicon single crystal wafer, and covering the silicon nitride layer. This method of manufacturing a semiconductor substrate is characterized in that a compound semiconductor layer is selectively formed on the central portion of a silicon single crystal wafer that is not covered.

[For production]

According to the present invention, the Si single-crystal wafer is exposed on the peripheral edge, back surface, and outer peripheral side of the semiconductor substrate, so that when a transfer arm, holder, etc. comes into contact with the substrate during substrate transfer, etc. , the exposed Si portion comes into contact without contacting the compound semiconductor layer. Therefore, GaAs or GaA I, which causes dust,
Damage to the compound semiconductor layer such as As can be avoided. As a result, the generation of dust is significantly reduced compared to the conventional method, and the yield of LSIs and optical devices manufactured on semiconductor substrates can be improved.

Further, according to another aspect of the present invention, since the peripheral portion and the outer circumferential side surface of the semiconductor substrate are made of a silicon nitride layer, damage to the compound semiconductor layer, which is a cause of dust generation, can be similarly avoided. Note that it is preferable to form a silicon oxide layer under the silicon nitride layer when manufacturing the substrate;
This is to prevent large warpage from occurring in the single crystal wafer; warpage causes crystal defects and is also unfavorable in terms of device fabrication. Furthermore, GaAs (or GaAIAS)
When forming the compound semiconductor layer, there is selectivity in that the compound semiconductor layer grows on the S1 single crystal but does not grow on the silicon nitride layer. If it is a silicon oxide layer, some growth will occur on it, which is not preferable.

〔Example〕

Hereinafter, the present invention will be described in detail by way of examples with reference to the accompanying drawings.

Example 1 As shown in FIGS. 1 and 2, a semiconductor substrate 1 according to the present invention has a compound semiconductor (Ga
There is a GaAs layer 3 on the peripheral edge of the substrate 1, the outer peripheral side surface, and the back surface of the substrate, so that the wafer 2 is exposed.

The semiconductor substrate 1 according to the present invention is manufactured as follows.

First, a Si single crystal wafer (100 sides; cut at an angle of 2 degrees in the 011 direction) 2 is prepared, and its surface is cleaned.

An amorphous GaAs layer (thickness: 10% m) is formed on the wafer 2 by the MOCV method under the following conditions.

Si wafer temperature: 450°C Gallium source: (CH3)3 Ga/L (L70c
bubbling at c/min) Arsenic source: AsH*/H2 (380cc/min
, 50%Ha) Carrier gas: I(2(1200
cc/min) MOCVD equipment internal pressure crab 7 (iTor
rSubsequently, after raising the Si wafer temperature to 700°C,
Under the following conditions? A GaAs epitaxial layer (thickness: 3(1-)) is formed by JOCV D.

Gallium source: (CI(3)3 Ga/Ha(H,
Bubbling at 14cc/min) Arsenic saw: x, :AsHs/H2 (200cc/
min, 50%H,) Carrier gas: Hz (12
00cc/m1n) Pressure: 76 Torr Then, the obtained substrate 1 was subjected to annealing heat treatment (900°C,
15 minutes) to form a single crystal GaAs layer 3.

Resist (
For example, Tokyo Ohka Kogyo's positive type resistor) 0FPR-8
00) is applied with a spin cord, the entire back surface of the substrate is exposed to light from a high-pressure mercury lamp, and only the peripheral edge of the substrate surface is exposed through a predetermined mask pattern and developed. In this way, the resist is removed from the back surface and peripheral edge of the substrate, leaving the resist layer at the center of the surface of the substrate.

Next, the GaAs layer that is not covered with the resist layer is etched using an etching solution (an aqueous solution containing concentrated sulfuric acid (96%), hydrogen peroxide (21%), and water in a mixing ratio of 3:1:1).
Remove by etching at ℃ (etching speed 2~6m/
m1n).

After washing with water, the remaining resist layer is removed using an alkaline developer, followed by washing with water and drying to obtain the semiconductor substrate 1 shown in FIGS. 1 and 2.

FIG. 3 shows a state in which the manufactured semiconductor substrate (GaAs/Si substrate) 1 is held upright in a quartz holder (susceptor) 4 for washing with water. Holder 4 holds GaAs layer 3 of substrate 1
It is held in contact with the Si exposed portion on the peripheral edge.

In the above embodiments, a positive resist is used, but a negative resist (for example, OMR-8 manufactured by Tokyo Ohka Kogyo Co., Ltd.) is used.
3) can be used instead. In this case, the back surface and peripheral portion of the substrate are left unexposed.

It is also possible to form a GaA i^S layer instead of the GaAs layer using the MOCVD method, in which case (CH,), Ga,^1(C)1. ),
and ^sH, using Hz as the carrier gas. Then, for etching of the GaA IlA layer, NH,0)1
+H2O2+H20 liquid is used.

Furthermore, the pattern of the resist layer is shown in FIGS. 4(a) to (e).
It is also possible to obtain the power of the compound semiconductor (GaAs) layers 3A to 3E shown in FIG. In FIG. 4(a), the exposed portion of the S1 wafer 2 is enlarged at the locations (4 locations) where the claws (protrusions) of the holder (susceptor) contact the substrate 1, and in FIG. 4(b), the exposed portion of the S1 wafer 2 is enlarged. The exposed portion of the Si wafer was extremely hot at the three contact points. In this way, the area of the compound semiconductor layers 3A and 3B can be increased by making the other portions of the peripheral portion smaller. In FIG. 4(C), the outer shape of the compound semiconductor layer 3C is determined according to the chip size of the LSI or optical device, and the yield at the peripheral portion is improved.

Furthermore, in FIG. 4(d), the compound semiconductor layer 3D is made into a strub shape in line with the chip cutting line in the subsequent process.
In FIG. 4(e), the case of FIG. 4(d) is further advanced and the compound semiconductor layer 3E is formed into a chip shape.

In these cases, by preventing the board from warping,
Reduces the force required to fix the substrate onto the susceptor, reducing the cause of substrate wear and dust generation, and
By removing the compound semiconductor around the chip,
Generation of dust after cutting into chips can be reduced.

Example 2 A compound semiconductor substrate according to another embodiment of the present invention has a compound semiconductor (GaAs) layer on the central portion of a Si single crystal wafer, and a silicon nitride layer is exposed on the peripheral portion and outer peripheral side surface. Such a compound semiconductor substrate is manufactured as follows.

First, the same S1 single crystal wafer as in Example 1 is prepared and cleaned. The wafer is thermally oxidized to coat the entire surface with silicon oxide (S102
) layer (thickness: 50 nm) is formed. Silicon nitride (S'3N4) is deposited on this silicon oxide layer by thermal CVD.
Form a layer (thickness: 50 nm).

Next, a negative resist is spin coated, the center of the S1 single crystal wafer is exposed, and a resist layer is formed on the wafer's periphery and side surfaces.

Using the resist layer as a mask, the uncovered central silicon nitride layer and the underlying silicon oxide layer are etched away using a hydrofluoric acid etching solution. Therefore, the central portion of the Si single crystal wafer is exposed, and the peripheral portion and side surfaces are covered with a silicon oxide layer and a silicon nitride layer.

After removing the resist layer, MOCV was performed under the same conditions as Example 1.
A GaAs layer is formed directly on an exposed Si single crystal wafer by method D, and annealed (500° C., 15 minutes) is performed. At this time, GaAs is not formed on the silicon nitride layer. In this way, a predetermined GaAs/Si substrate is obtained.

In Example 2, the GaAs layer (compound semiconductor layer) shown in FIGS. 4(a) to (e) can be formed similarly to Example 1, and in particular, the GaAs layer (compound semiconductor layer) shown in FIGS. 4(d) and (e) can be formed. In this case, G
It is possible to suppress the occurrence of warping of the substrate during aAs formation.

MB instead of the MOCVD method in Examples 1 and 2 above
Similar GaAs (GaA1 fAs) using the E method
layers can be formed. For example, a Si single crystal wafer is heated to 600°C, the Ga/As ratio is set to 6/1, and the pressure is set to 5.
The GaAs layer can be formed as xlO-''Torr.

〔Effect of the invention〕

As explained above, according to the present invention, a semiconductor substrate in which a GaAs (GaAI I!As) layer is formed on a Si single crystal wafer has no GaAs layer on the peripheral edge and side surfaces, and is made of a Si wafer or a silicon nitride layer. is in contact with the holder (jig), eliminating the generation of GaAs dust. Therefore, semiconductor devices such as LSI,
Yield and reliability of light emitting devices are improved.

[Brief explanation of the drawing]

1 is a plan view of a semiconductor substrate according to the present invention, FIG. 2 is a partial cross-sectional view of the semiconductor substrate of FIG. 1, and FIG. 3 is a diagram showing the semiconductor substrate of FIG. 1 held by a holder. FIGS. 4(a) to 4(e) are plan views of a semiconductor substrate having compound semiconductor layers formed in various patterns. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Silicon single crystal wafer, 3.3A to 3E... Compound semiconductor layer, 4... Holder Plan view of semiconductor substrate of the present invention FIG. 1 Partial sectional view of semiconductor substrate Figure Figure 3... Compound semiconductor (GaAs) 1 Figure (α) Figure (b) Figure (e)

Claims (1)

[Claims] 1. A semiconductor substrate in which a compound semiconductor layer is formed on a silicon single-crystal wafer, characterized in that the silicon single-crystal wafer is exposed at least at the peripheral edge, back surface, and outer peripheral side of the substrate. semiconductor substrate. 2. Selectively forming a silicon nitride layer on the peripheral edge and outer peripheral side of the silicon single crystal wafer, and selectively forming a compound semiconductor layer on the central portion of the silicon single crystal wafer that is not covered with the silicon nitride. A method for manufacturing a semiconductor substrate, characterized in that: