JPH02220449A - Field effect transistor and its manufacturing method - Google Patents

Abstract

PURPOSE:To improve the title transistor in gain and cutoff frequency by a method wherein a metal gate electrode is filled into a part between insulating films on a source region and a drain region on both sides. CONSTITUTION:A dummy gate 7 is removed; after that, a Schottky metal film 10 is formed; after that, a metal film 12 is formed by a plating method and its surface is flattened; then, an ion milling operation is executed from the upper part of a wafer; the metal film 12 and the Schottky metal film 10 are etched back. This etching operation is stopped in a state that only a part stranded on an SiO2 film 9 is removed and that the metal film is left only in a part sandwiched between SiO2 films 9 on both a source region and a drain region; then, a gate electrode filled into a part between the SiO2 films 9 is obtained. Thereby, a part in which the metal gate electrode is stranded on an insulating film is eliminated; a MIS capacity is removed; the length of the gate electrode can be shortened because it is not patterned by an exposure operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a metal-semiconductor field effect transistor used as a basic element constituting various semiconductor devices and a method for manufacturing the same.

[Conventional technology]

Typical parameters representing the performance of this type of field effect transistor (FET) include mutual conductance g and current cutoff frequency FT. In order to improve these, it is effective to shorten the gate length. However, conventional methods using light exposure have a limit of 0.5 μm, and to achieve a shorter gate length, electron beam (E) is required.

B.) and X-rays had no choice but to be used. However, there were problems in terms of safety and throughput, and therefore the replacement gate method was developed as a method of shortening the gate length through light exposure with good throughput.

S A I N T (Self-Aligned I
plantation I'orN-1ayer
According to this method, which is typified by Technology), the gate length can be made shorter than the minimum pattern during exposure, and the gate length can be shortened to 0.1 to 0.2 μm.

[Problem to be solved by the invention]

However, according to the above-mentioned replacement gate method, although the gate length itself can be made shorter than the minimum pattern during exposure by using a dummy gate, the minimum pattern is limited by exposure when patterning the gate metal. Therefore, its length is generally about 0.7 to 1.0 μm. For this reason, the gate metal largely rides on the insulating film, and the parasitic capacitance i (Mis capacitance) generated between the metal, the insulating film, and the semiconductor increases, greatly reducing the gain of the FET. In addition, this MIS capacitance increases the gate capacitance, lowers fT, and deteriorates high frequency characteristics, making it unsuitable as an FET for use in, for example, a high frequency circuit of IGHz or higher.

[Means to solve the problem]

In the field effect transistor of the present invention, a metal gate electrode is embedded between insulating films formed on source/drain regions on both sides.

In addition, in order to realize such a structure, the manufacturing method of the present invention involves forming a Schottky metal film as in the conventional method after removing the dummy gate, and then forming a metal film using a plating method to flatten the top surface. , then these metal films are
Ion milling is used to scrape away the portions that are on top of the insulating film until they disappear.

[Effect]

Since there is no part where the metal gate electrode rides on the insulating film, the MIS capacitance is reduced.

Furthermore, the final length of the gate electrode is determined in a self-aligned manner by the interval between the insulating films. In other words, since the electrode is not patterned by exposure to light, its length can be shortened without being limited by the minimum pattern by exposure, and a new mask may not be required for its formation. do not have.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to FIG. 1 of the accompanying drawings. The figure is a cross-sectional view of the process, but the scale is not accurate.

In the figure, after a 0 layer 2 is formed by implanting 81 ions into the surface of a semi-insulating substrate 1 made of GaAs, an annealed SiN film (about 1500 Å thick) 3,
Lower resist film (approximately 13000A) 4 and S50 2 film (approximately 300A)
0A) 5 are sequentially formed ((a) in the same figure).

Next, a resist pattern 6 is formed for patterning the dummy gate (FIG. 6(b)).

RIE (Rea) using this resist pattern 6 as a mask
Active Ion Etching)
The O2 film 5 is etched ((C) in the same figure).

Next, the lower resist film 4 is etched using the SiO2III 5 as a mask. At this time, a T-shaped dummy gate 7 is formed by making an undercut. After that, St ions are implanted into the source/drain region in the n layer 8.
((d) in the same figure).

Next, an S io 2 film 9 is formed by sputtering (FIG. 4(e)).

Thereafter, by removing the dummy gate, a gate opening is formed (FIG. 6(f)).

Ti (1000%
A) / Pt (500A) /Au (100OA
) A Schottky metal film 10 having a three-layer structure is formed ((g) in the same figure).

Next, a resist pattern 11 is formed ((h) in the same figure).
). Conventionally, this resist pattern 11 was used as it was as a mask for patterning the Schottky metal @10 by lift-off, and a gate electrode was formed.

In this embodiment, plating is performed using this resist pattern 11 as a mask, and a gold (Au) film (approximately 600%
0 to 100 OOA) 12 (see figure (i)).

Since plating progresses isotropically, the top surface becomes flat.

After that, the resist pattern 11 is coated with an organic solvent such as acetone.
After removing the wafer, ion milling is performed from the top of the wafer.
The AuH 12 and Schottky metal film 10 are etched back. If the metal film is stopped when the portions that are on top of the 5i02 film 9 are removed and these metal films remain only in the portions sandwiched between the Sio2 films 9 on both the source and drain regions, the Sio2 film 9 will be removed. A gate electrode is obtained buried in between ((j) in the same figure).

Thereafter, an ohmic electrode (not shown) is formed on the n-layer 8 in the same manner as in the prior art, and the FET is completed.

In the above embodiment, the resist pattern 11 is conventionally used for final patterning of the gate electrode as described above, and therefore, its opening length is the minimum dimension possible by exposure. However, in the above embodiment,
Since the dimensions of the gate electrode are ultimately determined in a self-aligned manner by the spacing between the SiO2 films 9, it is not necessarily necessary to use the resist pattern 11 with such a minimum dimension.

In this invention, it is important to form a flat metal film by filling the recess of the gate opening, and for this reason, in the above embodiment, a gold plating method was used. For example, it is possible to use aluminum (1) instead of gold, but the metal film buried in this part has the role of increasing the cross-sectional area of the gate electrode and reducing its resistance, so it is not conductive. A high value is desirable.

It goes without saying that the materials of each part and the film forming method are not limited to the examples described above. For example, in the above embodiment, the active layer (operating layer) is formed by ion implantation into the substrate made of GaAs, but an epitaxially grown active layer may also be used.

〔Effect of the invention〕

As described above, the present invention has the effect of reducing the parasitic MIS capacitance and improving the gain and cutoff frequency because the gate electrode riding on the insulating film is removed in a self-aligned manner. It is particularly useful for FETs used in high-frequency circuits, and is extremely effective for use in low-noise amplifiers of IGHz or higher, for example.

[Brief explanation of the drawing]

FIG. 1 is a process sectional view showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... N layer, 7... Dummy gate, 8... N layer layer, 9... SiO2 film, 10...
- Schottky metal film, 12...Au film. Patent applicant: Sumitomo Electric Industries, Ltd. Representative patent attorney Yoshiki Hase
Salt 1) Tatsuya Figure 1

Claims (1)

[Claims] 1. In a metal-semiconductor field effect transistor in which a Schottky metal gate electrode is in contact with the active layer between the source and drain regions, the gate electrode is an insulator formed on the source and drain regions. A field effect transistor characterized by being embedded between films. 2. In a method for manufacturing a metal-semiconductor field effect transistor using the substitution gate method, a step of forming an insulating film on the source/drain region using a dummy gate formed on the active layer in the gate region as a mask, and removing the dummy gate. After that, a Schottky metal is deposited on the entire surface and a Schottky junction is formed between the active layer in the gate region exposed on the dummy gate trace, and a plating method is used to form a Schottky junction on the Schottky metal film. A process of forming a metal film so that the upper cavity is filled and the top surface is almost flat, and ion milling is applied to the entire surface of these metal films to flatten them from above, forming an insulating film over the source and drain regions. A method for manufacturing a field effect transistor, comprising the step of leaving these metal films only in between.