JPH02220462A - Semiconductor device - Google Patents

Abstract

PURPOSE:To realize a high integration by a method wherein a trench formed in an upper layer conductive region just above one part of a lower layer conductive region is filled with a conductive film formed so as to be brought into contact with side faces of the upper layer conductive region and with the surface of the lower layer conductive region. CONSTITUTION:When an Al wiring part 7 as an upper layer conductive region is connected to an n<+> type impurity region 4 as a lower layer conductive region, a trench used to expose the n<+> type impurity region 4 is formed in the Al wiring part 7 and in a phosphosilicate glass(PSG) film which are situated just abobe one part of the n<+> type impurity region 4. Then, the trench is filled with a selective chemical growth conductive film 8 so as to be flat; the two regions are connected at an identical potential on side faces of the Al wiring part 7 and on the surface of the n<+> type impurity region 4. Thereby, when a fine contact region is formed, a high integration is realized. When a wiring body whose step coverage is good is formed, a deterioration in an electromigration life is improved; high reliability is guaranteed.

Description

[Detailed Description of the Invention] [Summary] At least two conductive regions that overlap vertically (in the case where the upper conductive region is made of a wiring body provided on an insulating film and the lower conductive region is made of a semiconductor layer provided on a silicon substrate) , when both the upper and lower conductive regions are made of wiring bodies, when the upper and lower conductive regions are both made of semiconductor layers provided on a silicon substrate, etc.), the upper conductive region directly above a part of the lower conductive region A trench is provided that exposes the lower conductive region (including the case where there is an insulating film underneath), and then a selective chemical vapor deposition conductive film or the like is flatly buried in this trench, and at least one of the upper conductive regions is exposed through the conductive film. High integration by connecting the three regions to the same potential on the side surfaces and at least the top surface of the lower conductive region and forming fine contact regions 1
A semiconductor device that makes it possible to form a semiconductor integrated circuit with high reliability by forming a wiring body with good step coverage and improved electromigration.

[Field of Industrial Application] The present invention relates to MIS and bipolar semiconductor devices, and in particular, in a semiconductor device having at least two vertically overlapping conductive regions, the present invention facilitates connection between an upper conductive region and a lower conductive region, and facilitates high integration and 9 Concerning semiconductor devices that enable the formation of highly reliable semiconductor (IF, integrated circuits) As the process progresses, two conductive regions are formed overlapping each other, and there are cases where it is desired to connect both regions at the same potential due to the layout. Wiring with poor step coverage results in poor electromigration and poor lifespan (
However, the problem that the upper layer conductive region and the lower layer conductive region There is a need for a means for connecting regions with fine contact regions and with good step coverage.

[Prior Art] FIG. 6 is a first schematic side sectional view of a conventional semiconductor device. In the figure, 51 is a p-type silicon (Si) substrate;
52 is a p-type channel stopper region, 53 is a field oxide film, 54 is an n-type impurity region, 55 is a blocking oxide film, and 56 is a phosphosilicate glass (PSG) film 57 is an A1 wiring. In this conventional semiconductor device, the A1 wiring 57, which is an upper conductive region, and the n0-type impurity region 54, which is a lower conductive region, are directly connected through a fine contact window, resulting in extremely poor step coverage.
There was a problem that electromigration deteriorated the lifespan and high reliability could not be guaranteed.

FIG. 7 is a second schematic side sectional view of a conventional semiconductor device. In the figure, 51 is a p-type silicon (Si) substrate;
52 is a p-type channel stopper region, 53 is a field oxide film, 54a is an n+ type source region, 541) is an n + type drain region 55 is a blocking oxide film, 56 is a phosphosilicate glass (PSG) film, 57a is a source wiring , 57b is a drain wiring, 57c is a substrate contact wiring, 58 is a p-type substrate contact region, 59 is a gate oxide film, and 60 is a gate electrode. In this conventional semiconductor device, the n+ type source region 54a, which is the upper conductive region, and the p − type silicon (Si) substrate 51, which is the lower conductive region, are not directly connected. are connected by a source wiring 57a, and the p-type silicon (Si) substrate 51 is connected to a substrate contact wiring 57c via a p-type substrate contact region 58 provided separately from the n-type source region 54a. There is. There was also the problem that high integration could not be achieved.

[Problems to be Solved by the Invention] The problems to be solved by the present invention are, as shown in the above-mentioned two conventional examples, in a semiconductor device having at least two vertically overlapping conductive regions, an upper conductive region and a lower conductive region. Regarding the connection of conductive regions, it has been difficult to realize a semiconductor device in which a fine contact region is formed to enable high integration, and a wiring body with good step coverage is formed with improved electromigration to enable high reliability. [Means for Solving the Problem] The above problem is a semiconductor device having at least two vertically overlapping conductive regions, in which an upper conductive region directly above a part of a lower conductive region has a lower conductive region. The problem is solved by a semiconductor device according to the present invention, in which a trench is provided that exposes the upper conductive region, and the trench is filled with a conductive film provided in contact with at least the side surfaces of the upper conductive region and at least the upper surface of the lower conductive region.

[Function] That is, in the semiconductor device of the present invention, as shown in FIG. 1, in a semiconductor device having at least two vertically overlapping conductive regions, the lower conductive region A trench exposing the lower conductive region is provided in the upper conductive region and the phosphosilicate glass (PSG) film directly above a part of the conductive region, and then a selective vapor-deposited conductive film or the like is flatly buried in this trench, and the conductive film is then passed through the conductive film. The three regions are connected to the same potential at least on the side surface of the upper conductive region and at least on the upper surface of the lower conductive region. Therefore, it is possible to realize a semiconductor integrated circuit which is highly integrated by forming fine contact regions and has high reliability by forming a wiring body with improved electromigration and good step coverage.

[Example] The present invention will be specifically explained below with reference to illustrated embodiments.

FIGS. 1(a) and 1(b) show the first part of the semiconductor device of the present invention.
FIG. 2 is a schematic side sectional view of the second embodiment of the semiconductor device of the present invention, and FIGS. 3(a) and 3(b) are schematic diagrams of the third embodiment of the semiconductor device of the present invention. 4 is a schematic side sectional view of a fourth embodiment of the semiconductor device of the present invention, and FIGS. 5(a) to 5(d) are process sectional views of an embodiment of the manufacturing method of the present invention. It is.

The same objects are designated by the same reference numerals throughout the drawings.9 Figure 1 shows a first embodiment of the present invention using a p-type silicon (Si) substrate, where (a) is a side sectional view and (b) is a side sectional view. 1 schematically shows a plan view. 1 is a p-type silicon (Si) substrate of about 1015 cm-3, 2 is a p-type channel stopper region of about 1017 cm-3, 3 is a field oxide film of about 600 nm, and 4 is an n-type silicon substrate of about 10" cm-3. Type impurity region, 5 is about 501 block oxide film, 6 is 800n-
A phosphosilicate glass (PSG) film with an IP rating of 7 and an IP rating of 1.
1 wiring, 8 is a buried conductive M, (select f) chemical vapor phase growth conductive film, and 9 is an approximately 200 nm glabella insulating film (plasma chemical vapor deposition film).

In the figure, regarding the connection between the AI wiring 7 which is the upper layer conductive region and the n0 type impurity region 4 which is the lower layer conductive region, the A1 wire 7 and the phosphosilicate glass (PSG) directly above a part of the n0 type impurity region 4 are shown. A trench exposing the n-doped impurity region 4 is provided in the film 6, and then a selective chemical vapor deposition conductive film 8 is flatly buried in the trench, and the side surface of the AI wiring 7 is formed through the selective chemical vapor deposition conductive film 8. The three regions are connected to the same potential on the upper surface of the n0-type impurity region 4. Therefore, high integration becomes possible by forming fine contact regions. Further, by forming a wiring body with good step coverage, deterioration in electromigration life can be improved and high reliability can be guaranteed. Furthermore, in the contact region, the A1 wiring 7 and the A1 wiring 7 are completely cut and connected by the selective chemical vapor deposition conductive film 8, so the movement of the metal ions of AI can be stopped in this contact region. The structure is extremely resistant to electromigration, ensuring even higher reliability.

FIG. 2 shows a schematic side sectional view of a second embodiment of the semiconductor device of the present invention. 1 is about 10 cm p-
3 is a field oxide film of about 600 nm, and 6 is a phosphosilicate glass (PS) of about 8001.
G) Membrane 7 is the first layer of AI wiring of about 500n, 8
is a buried conductive film (selective chemical vapor deposition conductive film) 9 is 60
Interlayer insulating film (plasma chemical vapor deposition film) of about 01, 1
0 indicates the second layer A1 wiring of about 1-Peng.

In the figure, connections between multilayer interconnections are formed. −
Regarding the connection between the layer A1 wiring 7 and the second layer A1 wiring 10, -
A trench exposing the first layer AI wiring 7 is provided in the second layer A1 wiring 10 and the interlayer insulating film 9 directly above a part of the layer A1 wiring 7, and then a selective chemical vapor deposition conductive film 8 is formed in this trench.
is buried flatly, and the three regions are connected to the same potential on the side surface of the second layer A1 wiring 10 and the top surface of the -th layer AI wiring 7 via this selective chemical vapor deposition conductive film 8.
The aforementioned effects have been achieved. At the same time, a selective chemical vapor deposition conductive film 8 is also formed on the second layer AI wiring 10 to form a wiring body that is resistant to stress migration. FIG. 3 is a schematic side sectional view of a third embodiment of the semiconductor device of the invention, in which (a) shows a case in which a source wiring is provided, and (b) shows a case in which a source wiring is not provided. 1 is 1015C "p-type silicon (Si) of about 3
Substrate, 2 is a p-type channel stopper region of about 10 COl, 3 is a field oxide film of about 600 nm, 4a is an n-type source region of about 102oCI11-3 (7), and 4b is an n-type drain region of about 10 cm. , 5 is a block oxide film of about 50 ns, 6 is 800 ns
A phosphosilicate glass (PSG) film of about nm size, 7a is 1. g
The source wiring of about 1.1 liters, 7b is 1. um train wiring, 8 is a buried conductive film (selective chemical vapor deposition conductive film)
11 is a gate oxide film of about 20 nm, 12 is a gate oxide film of about 300 nm.
A gate electrode with a diameter of about nm, and 13 a substrate contact electrode.

In the figure, an n+ type source region 4 which is an upper conductive region
a and a p-type silicon (Si) substrate 1 which is a lower conductive region.
Regarding the connection, a p-type silicon (Si)
A trench exposing the substrate 1 is provided, and then a selective chemical vapor phase grown conductive film 8 is buried flatly in this trench, and an n+ type source region 4 is formed through the selective chemical vapor grown conductive film 8.
Three regions are connected to the same potential on the side surface of a and the side surface and top surface of the p-type silicon (Si) substrate 1. Therefore, as shown in the conventional example, a substrate contact region is also formed in a part of the n+ type source region 4a without providing a special substrate contact region, resulting in an extremely highly integrated structure. In (a), a source wiring is provided, but in (b), the substrate potential is applied to the back side of the p-type silicon (Si) substrate 1, and no source wiring is provided, which increases the degree of freedom in wiring layout. We can expect even higher integration.

FIG. 4 shows a schematic side sectional view of a fourth embodiment of the semiconductor device of the present invention. 1 is a p-type silicon (Si) substrate of about 1016C1l-3, 5 is a block oxide film of about 5 () nm, and 6 is a phosphosilicate glass (about 8001).
PSG) film, 7 is A1 wiring of about 1 unit, 8 is a buried conductive film (selective chemical vapor deposition conductive film), 14 is 1020C
Peng-3 n-type buried layer, 15 is 10110l7
n-type collector region of '16 is 10110l7'
17 is a p-type base region of about 1017cm-3, 18 is a p-type base contact region of about 1020c13, 19 is an n-type emitter region of about 10'l or C13, and 20 is a base layer. 21 represents a polycrystalline silicon film for forming an emitter.

In the figure, regarding the connection between the n-type collector region 15 which is the upper layer conductive region and the n-type buried layer 14 which is the lower layer conductive region, the n-type collector region 15 directly above a part of the n-type buried layer 14 is A trench exposing the n-type buried layer 14 is provided, and then a selective chemical vapor deposition conductive film 8 is flatly buried in this trench.
The three regions are connected with low resistance at the side surface of the n-type collector region 15 and the side surface and top surface of the n-type buried layer 14 via the n-type collector region 15. Therefore, compared to conventional connections using impurity diffusion layers, it is possible to form highly integrated and high-speed semiconductor devices.

Next, an embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 5(a) to 5(d).

Figure 5(a) By applying conventional techniques, p-type silicon (S)
i) A p-type channel stopper region 2 field oxide film 3, an n+ type impurity region 4, a blocking oxide film 5,
A phosphosilicate glass (PSG) film 6 and the like are formed.

FIG. 5(b) Next, about 111 layers of AI are sputtered on the entire surface, and about 20 layers of plasma chemical vapor deposition film 9 is grown to serve as a mask layer.Next, the A1 wiring 7 is patterned using normal photolithography technology. do.

FIG. 5(C) Next, using a normal photolithography technique, the plasma chemical vapor deposition film 9, the A1 wiring 7, the phosphosilicate glass (PSG) film 6, and the block directly above a part of the n-type impurity region 4 are removed. A trench is opened in the secondary oxide film 5 to serve as a contact region reaching the n+ type impurity region 4.

FIG. 5(d) Next, a selective chemical vapor deposition conductive film 8 is buried flatly in this trench, and through this selective chemical vapor deposition conductive film 8,
The connection between the A1 wiring 7 and the n+ type impurity region 4 is completed. In addition, the selection f growing on the A1 wiring 7 edge other than the trench
The vapor phase grown conductive film 8 may be removed by etching by another photolithography process.
Although the trench is formed after patterning the A1 wiring, a method may also be used in which the trench is formed before the patterning of the A1 wiring and the selective chemical vapor deposition conductive film 8 is buried therein.

As shown in the embodiments above, according to the semiconductor device of the present invention, in a semiconductor device having at least two vertically overlapping conductive regions, the connection between the upper conductive region and the lower conductive region is directly above a part of the lower conductive region. A trench exposing the lower conductive region is provided in the upper conductive region, and then a selective vapor-deposited conductive film or the like is flatly buried in the trench, and at least the side surfaces of the upper conductive region and at least the top surface of the lower conductive region are coated through the conductive film. 9 Therefore, high integration is possible by forming fine contact regions, and high reliability is achieved by forming wiring bodies with good step coverage and improved electromigration. can also be made possible.

[Effects of the Invention] As described above, according to the present invention, in MIS and bipolar semiconductor devices having at least two vertically overlapping conductive regions, the upper conductive region and the lower conductive region can be connected by a fine contact region or Since it can be formed using a wiring body with improved electromigration and good step coverage, it is possible to obtain an extremely excellent semiconductor integrated circuit having both high integration and high reliability.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) show the first part of the semiconductor device of the present invention.
FIG. 2 is a schematic side sectional view of the second embodiment of the semiconductor device of the present invention, and FIGS. 3(a) and (b) are the third embodiment of the semiconductor device of the present invention.
FIG. 4 is a schematic side sectional view of a fourth embodiment of the semiconductor device of the present invention, and FIGS. 5(a) to (d) are an embodiment of the manufacturing method of the present invention. FIG. 6 is a first schematic side sectional view of a conventional semiconductor device, and FIG. 7 is a second schematic side sectional view of a conventional semiconductor device. In the figure, 2 is a p-type silicon (Si) substrate, 2 is a p-type channel stopper region, 3 is a field oxide film, 4 is an n-type impurity region, 4a and 4b are n-type source regions, n-type drains 5 is a block oxide film, 6 is a phosphosilicate glass (PSG) film, 7 is an AI wiring (-layer A1 wiring), 7a and 7b are source wiring and drain wiring, 8 is a buried conductive film (selective chemical vapor 9 is the eyebrow insulating film (plasma chemical vapor deposition film), 10 is the second layer A1 wiring, 11 is the gate oxide film, 12 is the gate electrode, 13 is the substrate contact electrode, 14 is the n-type Buried layer, 15 is an n-type collector region, 16 is a p-type isolation region, 17 is a p-type base region, 18 is a p-type base contact region, 19 is an n-type emitter region, 20 is an underlying oxide film, 21 indicates a polycrystalline silicon film for forming an emitter.

Claims (5)

[Claims] (1) A semiconductor device having at least two vertically overlapping conductive regions, in which a trench exposing the lower conductive region is provided in an upper conductive region directly above a part of the lower conductive region, and the trench is connected to the upper conductive region. A semiconductor device characterized in that the semiconductor device is embedded with a conductive film provided in contact with at least a side surface of the lower conductive region and at least an upper surface of the lower conductive region. (2) The semiconductor according to claim 1, wherein the upper conductive region is made of a wiring body provided on an insulating film, and the lower conductive region is made of a semiconductor layer provided on a silicon substrate. Device. (3) The semiconductor device according to claim 1, wherein both the upper and lower conductive regions are formed of wiring bodies. (4) The semiconductor device according to claim 1, wherein both the upper and lower conductive regions are made of semiconductor layers provided on a silicon substrate. (5) The semiconductor device according to claim 1, wherein the conductive film is made of a selective chemical vapor deposition film.