JPH02220524A - Digital signal processing circuit - Google Patents

Abstract

PURPOSE:To make the circuit scale small and to reduce the cost by providing a multiplexing circuit, multiplexing an auxiliary signal to an idle slot in the output of a synchronizing circuit, and applying row conversion. CONSTITUTION:Synchronizing circuits 1-3 having a synchronizing memory capacity corresponding to an (m)-bit length of multiplexing signals 110, 111 after row conversion receive timing pulses 107-109. The pulses 107-109 are generated in a timing pulse generator 4 and required for synchronization/multiplexing. Then the circuits 13 synchronize (m)-row of information signals 101-103 asynchronous with each other and inputted to a multiplex circuit 5 as signals 104-106 taking the row conversion into account. Then an auxiliary signal is inserted to the input signal and an idle slot to be multiplexed is provided simultaneously with synchronization. The (m)-row signal is selected sequentially at the circuit 5 by using a control signal 118 from synchronized (m)-row signals 104-106 as soon as the auxiliary signal is multiplexed to form (n)-row signal as row conversion to form the multiplexed signals 110, 111. Thus, any independent row conversion circuit is required and the circuit is made small in size.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital signal processing circuit, and particularly to a digital signal processing circuit used in a digital wireless communication line.

[Conventional technology]

In digital wireless communication lines such as microwave bands,
After converting the asynchronous m-column bipolar signals input from the digital multiplexing terminal equipment into unipolar signals using a code converter, synchronization is performed using a synchronization circuit provided for each column, and the radio section is monitored and controlled. Auxiliary signals such as a frame synchronization signal, a supervisory control signal, and a pattern check signal, which are necessary for the modulation, are time-division multiplexed and sent to the modulation device.

The number n of columns of multiplexed signals to be input to a modulation device differs depending on its modulation method. For example, if the modulation method is a quadrature phase modulation method, n=2, and if the modulation method is a 16-value quadrature amplitude modulation method, n=4. When this number of columns n is different from the number of columns m described above, the multiplexed signal of m columns is column-converted to n columns.

FIG. 2(a) is a block diagram of an example of a conventional digital signal processing circuit that performs synchronization, multiplexing, and column conversion.
FIG. 2(b) is a time chart for explaining the operation of the conventional example shown in FIG. 2(a).

In the conventional example shown in FIG. 2(a), m=3. This is for the case where n=2, and operates as explained below.

Mutually asynchronous information signals 101 to 103 input from a digital multiplexing terminal device (not shown) and converted from bipolar to unipolar by a code converter (not shown) are input to synchronization circuits 6 to 7, respectively. do. In the synchronization circuits 6 to 8, a clock pulse 116 with a duty ratio of 50% and various timing pulses necessary for synchronization are inputted from the timing pulse generation circuit 9 to generate three asynchronous information signals l.

1 to 103 are synchronized and output as signals 113 to 115 (see FIG. 2(b)). This is a well-known technique.

The synchronized three columns of signals 113 to 115 are multiplexed with various auxiliary signals in the multiplexing circuit 10 under the control signal 117 from the timing pulse generation circuit 9. Incidentally, empty slots for inserting and multiplexing auxiliary signals are provided in the synchronization circuits 6 to 8. The multiplexed three-column signals 113 to 115 are column-converted from three columns to two columns in the column conversion circuit 11, and the two-column multiplexed signals 110, 111 are
and the clock pulse 112 of the multiplexed signals 110 and 111 are output.

[Problem to be solved by the invention]

The above-mentioned conventional digital signal processing circuit performs the synchronous multiplexing operation and the column conversion operation in separate circuits, which increases the circuit scale, which is disadvantageous in terms of miniaturization and cost reduction. There is.

[Means to solve the problem]

The digital signal processing circuit of the present invention synchronizes m (m is a natural number of 3 or more) columns of digital information signals between columns, and provides empty slots in each column for multiplexing auxiliary signals. and a multiplexing circuit that multiplexes the auxiliary signal into the empty slot output from the synchronization circuit and converts the auxiliary signal into n (n is a natural number greater than or equal to 2 and less than m) columns.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1(a) is a block diagram of an embodiment of the present invention, and FIG. 1(b) is a time chart for explaining the operation of the embodiment shown in FIG. 1(a).

The embodiment shown in FIG. 1 is for column conversion of 3 columns/2 columns.

Synchronization circuits 1 to 3 each have a memory capacity for synchronization equivalent to the 3-bit length of the multiplexed signals 110 and 111 after column conversion, and perform synchronization/multiplexing that takes into account column conversion of 3 columns/2 columns at the same time as synchronization. By inputting the various timing pulses 107 to 109 (see FIG. 1(b)) necessary for
Signals 104 to 10 with synchronization of 103 and consideration of column transformation
Note that an empty slot for inserting and multiplexing an auxiliary signal is also provided at the same time as synchronization.

The synchronized three columns of signals 104 to 106 are generated in the multiplexing circuit 5 by sequentially selecting the three columns of signals simultaneously with the multiplexing of the auxiliary signals under the control signal 118 from the timing pulse generation circuit 4. By rearranging the signals in the column, 3
The column is converted into two columns, resulting in multiplexed signals 110 and 111 (see FIG. 1(b)). Multiplexed signals 110, 111
and these clock pulses 112 are sent to a modulator (not shown) of a modulation device.

〔Effect of the invention〕

As explained in detail above, according to the digital signal processing circuit of the present invention, column conversion can be realized by a multiplexing circuit without using an independent column conversion circuit that was conventionally required, and the circuit scale is reduced. This has the effect of being economical and also advantageous for downsizing.

[Brief explanation of the drawing]

FIG. 1(a) is a block diagram of an embodiment of the present invention, FIG. 1(b) is a time chart for explaining the operation of the embodiment shown in FIG. 1(a), and FIG. 2(a) is a block diagram of an example of a conventional digital signal processing circuit, and FIG. 2(b) is a block diagram of an example of a conventional digital signal processing circuit.
It is a time chart for explaining the operation of the conventional example shown in FIG.

Claims (1)

[Claims] A synchronization circuit that synchronizes m (m is a natural number of 3 or more) columns of digital information signals between columns and provides empty slots in each column for multiplexing auxiliary signals, and an output of this synchronization circuit. a multiplexing circuit that multiplexes the auxiliary signal into the empty slot in the slot and converts the auxiliary signal into n (n is a natural number greater than or equal to 2 and less than m) columns.