JPH02222033A - Multiplier - Google Patents

Abstract

PURPOSE:To obtain a product output having the same number of bits as the multiplication undergone a rounding arithmetic operation by adding the n-th bit of a product to the lowest rank bit of a part having the next clock cycle set at 0 via the gating control. CONSTITUTION:0 is inputted in (m) bits into an AND gate 11 after the n-th bit of a multiplier, and a 1st input signal of a (m+1)-th AND gate 12 is set at 1 when the first 0 is inputted. Thus the gate 12 is opened and the n-th bit Pn of a product stored in a (2m+1)-th DFF 18 is outputted to the output of the gate 12. Then the output signal of a 1st AND gate is set at 0, and the output of an OR gate 12 is equal to Pn to serve as an input signal of a 1st full adder 14. In this case, an adder 14 adds the Pn for calculations following the (n+1)-th bit of a product. The (n+1)-th - (m+n)-th bits of a product are secured at output of the (m+n)-th bit of the product and equal to a product of the bit number (m) undergone a rounding arithmetic operation.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a multiplier used in a digital signal processing circuit.

2. Description of the Related Art Many systems have been proposed in the past for digital multipliers that perform multiplication of digital data. They can be roughly divided into parallel multipliers.

Serial parallel multiplier, ROM multiplier.

Parallel multipliers are fast, but the circuit size is large. ROM multipliers are also fast, but as the number of bits in the multiplier and multiplicand increases, the circuit scale becomes extremely large. Series-parallel multipliers have the advantage of slow calculation speed but relatively small circuit scale.

A conventional series-parallel multiplier will be explained below.

FIG. 3 is a circuit diagram of this conventional multiplier.

In FIG. 3, 1 is the first to m-th AND gate, 2
are the first to m-1th full adders, and 3 is the first to m-1th full adders.
4 is the mth to m-2th D flip-flops.

The operation of the multiplier configured as described above will be described below.

In the initial state, all D flip-flops 3 are reset. The first (lowest) pix of the multiplicand, which is a positive number, is used as the second input signal of the first to m-th AND gates 1
+ to mth (most significant) bit X, respectively. Now, for each unit clock, a positive multiplier is input in order from the least significant bit, and then O's are input in the same number as the number of bits m of the multiplier. The output signals of the first to m-th AND gates 1 are X Iyl, X 2 Y+, . . .
1, and when the first bit (1≦≦n) of the multiplier is input, X + Y−, X 2 Yh+ ・
...X - Y k. In other words, 1st to mth AND
The output of the gate operator is the partial product of the multiplication. The first to (m-1)th full adders 2 and the first to (m-1)th D flip-flops 3 add these partial products while sequentially shifting the bits every unit clock. However, the carry output signal of the full adder is not directly sent to the upper full adder, but is sent to the D flip-flops 4 from − degree m to 2 m−2.
and is added as a carry input signal to the addition of the upper digits at the next unit clock. In this way, products are obtained at the output of the first full adder starting from the least significant bit.

FIG. 4 is a schematic diagram showing the operation of a conventional series-parallel multiplier when m=4+n=3. In FIG. 4, from clock O to clock 6, that is, from the initial state to the time when six unit clocks are input, the first to fourth clocks are input.
The partial products applied to the AND gate are shown. +
indicates the addition by the full adder, and -m- indicates the flow of the carry signal. Further, Pl to P7 represent products that are sequentially output. It can be seen from FIG. 4 that the output of this multiplier is the sum of partial products.

Problems to be Solved by the Invention However, in the conventional configuration described above, if m bits, which is the same as the multiplicand, is required as the number of bits for the product, rounding operations must be performed again on the output m+n bit product. There was a problem in that hardware had to be added for this purpose.

SUMMARY OF THE INVENTION The present invention is intended to solve the above-mentioned conventional problems, and an object of the present invention is to provide a multiplier that is rounded and can obtain a product with the same number of bits as the multiplicand.

Means for Solving the Problems To achieve this object, the multiplier of the present invention uses a multiplier that is input n-bit serial data and m-bit "°0" as a common first input signal, 1st to mth A in which the first to mth bits of the multiplicand, which is input m-bit parallel data, are respectively second inputs;
an ND gate, a second m-1 unit delay device, and the second m-1 unit delay device;
-1 unit delay unit output signal is the first input signal, n
an (m+1)-th AND gate whose second input signal is a timing signal in which bits "'0" and then "1" and m-1 bits "0" are given in synchronization with the serial data; The output signal of the AND gate is used as the first input signal, and the output signal of the m+1-th AND gate is used as the second input signal.
an OR gate whose input signal is an input signal, the output signal of the OR gate is a first input signal, the output signal of the first unit delay device is a second input signal, and the output signal of the m-th unit delay device is the output signal of the m-th unit delay device. a carry input signal, a first full adder whose output is supplied to the 2m-1 unit delay device, and output signals of the second to m-1 AND gates, respectively, as first input signals; The output signals of the second to m-1 unit delay units are respectively second input signals, and
second to m-1 full adders, each of which takes the output signal of the unit delay device as a carry input signal and supplies the output thereof to the first to m-2 unit delay device, respectively; and the m-th AN
an (m-1)th unit delay unit which takes the output signal of the D gate as an input signal; and (m-1) unit delay units which take the carry output signals of the first to (m-1)th full adders as carry input signals, respectively.
It has a configuration consisting of m-2 unit delay devices.

Operation According to the present invention, the n-th bit of the product is added to the least significant bit of the O portion in the next clock cycle by gating control with the above-described configuration.

In other words, the m bits from the n+1st bit to the m+nth bit of the product are filled with the value added to the nth bit, and a rounded product with the same number of bits as the multiplicand is obtained. be able to.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows a circuit diagram of a multiplier in an embodiment of the present invention. In Figure 1, 11 is the 1st to mth
It is an and gate. Serial data Y, ~Yn of n bits (n bits) (n is any positive integer) which is a multiplier, followed by "0" of m bits are serially input in common to one input terminal of each gate, and the other An m-bit parallel signal X I" given.Also, the second
The outputs of the ~m-1th AND gate 11 are the 2nd ~ mth AND gates, respectively.
−1 is applied to one input terminal of the full adder 15. Second
The outputs of the ~mth~1 full adders 15 are the 1st~m-2th full adders 15, respectively.
The signal is applied to the other input terminals of the first to (m-2) full adders 14.15 via the D flip-flop 16, which is a unit delay unit.

The output of the m-th AND gate 11 is applied to the other input terminal of the m-1 full adder 15 via the m-1 D flip-flop 16. First full adder 14. The carry output signals of the second to m-1 full adders 15 are the first to m-1 full adders 15, respectively.
It is applied to each carry input terminal via the 2m-2 D flip-flop 17. The output of the first full adder 14 is output as a serial multiplication signal, and is further applied to the (m+1)th AND gate 12 via the (2m-1)th D flip 7'70 tube 1B. At the other input terminal of the AND gate 12, the nth bit of the multiplier is "0", then "1", and then m-
A timing signal in which 1 bit becomes 0'' is applied in synchronization with the common serial input of the AND gate circuit 11, and this AND signal is applied to the OR circuit 13.The output of the OR circuit 13 is It is applied to an adder 14.

The operation of the multiplier of this embodiment configured as described above will be explained below.

In the initial state, all D flip-flops are set. The multiplier of this embodiment operates in the same way as a conventional multiplier until the n-th bit of the multiplier Y, ˜Y, is serially input and the n-th bit of the product is output. As shown in FIG. 1, m bits of “0” are input to the AND gate 11 following the n-th bit of the multiplier. When the first O of these m bits of 0 is input, m+1 A
Since the timing signal which is the first input signal of the ND gate 12 becomes "1", this gate 12 is opened, and the output of this gate 12 is connected to the 2m-1th D flip-flop 18.
The n-th bit Pn of the product stored in is output.

The output signal of the first AND gate becomes "0" since the first input signal of this gate is "OII".
The output of the R gate 12 becomes Pn, which becomes the first input signal of the first full adder 14. At this time, the first full adder 14 outputs the (n+1)th bit of the product Pn4. Since the calculation is performed, P is added to the calculation of the (n+1)th and subsequent bits of the product. Then, when the m+nth bit of the product is output, if the n+1st bit to the m+nth bit of the product are taken, this becomes the product of the rounded bit number m.

FIG. 2 is a schematic diagram showing the operation of the multiplier of this embodiment when m = 4s n = 3. Comparing this with FIG. 4, it can be seen that P3 is added to the calculations after P4.

As described above, according to this embodiment, by adding D flip-flop AND gates and OR gates to the configuration of the conventional series-parallel multiplier, rounding operations can be performed with an extremely simple configuration. You can obtain a product with the same number of bits as the multiplicand.

Effects of the Invention According to the present invention having the above characteristics, by adding an extremely simple circuit configuration to a conventional series-parallel multiplier, it is possible to obtain a product output with the same number of bits as the multiplier after performing a rounding operation. can. Furthermore, since the rounding operation is performed at the same time as the product calculation, the calculation time does not become long, which has a great practical effect.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a multiplier according to an embodiment of the present invention, FIG. 2 is a schematic diagram showing the operation of the same embodiment, FIG. 3 is a circuit diagram of a conventional multiplier, and FIG. It is a schematic diagram showing operation. 11...1st to m-th AND gates, 12...
・m+1st AND gate, 13 ・OR gate,
14...First full adder, 15...Second to m-th full adder, 16...First to m-th full adder.
1 D flip-flop, 17... mth to 2nd
m-2 D flip-flop, 18...2nd m-
1 D flip-flop. Name of agent Patent attorney Shigetaka Awano Haka1 figure 2 X4 X3X2 Xt I+Pk /4r N h P2

Claims (1)

[Claims] A multiplier that is input serial data of n bits (n is any positive integer) and m bits (m is any positive integer)
The first to mth bits of the multiplicand, which is the input m-bit parallel data, are the second input signals, respectively.
The output signal of the AND gate, the second m-1 unit delay unit, and the second m-1 unit delay unit is used as the first input signal, and n-bit “0”, then “1”, and m-1 bit of"
0'' is applied in synchronization with the serial data, the m+1-th AND gate has a second input signal as a timing signal, and the m+1-th AND gate has the output signal of the first AND gate as the first input signal; an OR gate that takes the output signal of the AND gate as a second input signal, the output signal of the OR gate as the first input signal, the output signal of the first unit delay device as the second input signal, and an m-th The output signal of the unit delay device is taken as a carry input signal, and the output signal of the first full adder is supplied to the 2m-1 unit delay device, and the output signals of the second to m-1 AND gates are respectively The first input signal is the output signal of the second to m-1th unit delay device, and the second input signal is the output signal of the second to m-1th unit delay device.
second to m-1 full adders, each of which takes the output signal of the unit delay device as a carry input signal and supplies the output thereof to the first to m-2 unit delay device, respectively; and the m-th AN
an (m-1)th unit delay unit which takes the output signal of the D gate as an input signal; and (m-1) unit delay units which take the carry output signals of the first to (m-1)th full adders as carry input signals, respectively.
A multiplier comprising: m-2 unit delay units.