JPH02222151A - Semiconductor integrated device - Google Patents

Abstract

PURPOSE:To obtain a stable lead and to improve the yield rate of devices by filling a groove reaching an embedded layer from the surface of a semiconductor element with a metal, and forming the lead. CONSTITUTION:An (n) epitaxial layer 3 is overlapped on an Si semiconductor substrate 1 having an n<+> embedded layer 2. The layer is isolated with a groove (isolating layer) 11. A (p) base layer 4 and an (n) emitter layer 5 are attached, and an electrode is attached. A groove 10 reaching the embedded layer 2 is provided from the surface and filled with Al 9 by vapor deposition and the like. Therefore, defective diffusion such as a lead in an impurity diffused layer is not formed, and the manufacturing yield rate is improved.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention is directed to forming semiconductor elements such as bipolar transistors or diffused MOS devices on a semiconductor substrate, and forming a high The present invention relates to a semiconductor integrated device including a buried layer with an impurity concentration.

[Conventional technology]

Traditionally, bipolar transistor or diffused type MO
In a semiconductor integrated device including semiconductor elements such as S devices, for example, a collector resistor is used for a bipolar transistor, a base resistor is used for a bipolar pnp transistor, and a drain is used for a diffused type MOS device. In order to lower the resistance, these semiconductor elements are provided with a buried layer with a high impurity concentration between them and the semiconductor substrate. An example of a semiconductor integrated device including a bipolar (NPN) transistor will be described below.

FIG. 2 shows the conventional semiconductor integrated device of bipolar and np type.
FIG. 3 is a cross-sectional view of an n-transistor portion. 1 is a semiconductor substrate,
3 is an n-type shrimp layer, 4 is a p-type base layer, 5 is an n-type emitter layer, 6 is an emitter electrode, 7 is a base electrode, and 8 is a collector electrode. 2 is an n-type buried layer with a high impurity concentration provided between the shrimp layer 3 and the semiconductor substrate 1 and has a low specific resistance value. Reference numeral 9 denotes an extraction lead between the buried layer 2 and the collector electrode 8, which is formed of an n-type diffusion layer and is called a collector diffusion layer. Like the buried layer 2, the collector diffusion layer 9 has a low specific resistance value. 2 to 9 form one bipolar number npn l-randisk.

11 is a separation layer provided between adjacent elements 20; p
It is a shaped diffusion layer.

[Problem to be solved by the invention]

However, in the semiconductor integrated device described above, in order to form the collector diffusion layer which is the lead between the buried layer and the collector electrode of the bipolar/NPN L-transistor, it is necessary to diffuse impurities at a high concentration and for a long time. There are problems due to high cost and high cost. In addition, it is necessary to form the collector diffusion layer to a deep part of the buried layer, but in the deep part of the diffusion layer, impurity diffusion is poor and the specific resistance value is difficult to decrease.As a result, the resistance of the lead lead increases and the element There is a problem that the characteristics of Similar problems exist with bipolar/pnp transistors, diffused type MOS devices, and the like.

Furthermore, the isolation layer provided between adjacent semiconductor elements requires the formation of a deep diffusion layer from the surface of the semiconductor integrated device to the semiconductor substrate. There is a problem that the display) becomes larger and the integration density of the semiconductor integrated device becomes lower.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a semiconductor integrated device which is low in cost, does not deteriorate the characteristics of semiconductor elements, and has a high integration density.

[Means to solve the problem]

In order to solve the above problems, a bipolar fold transistor or a diffused type M transistor formed on a semiconductor substrate of the present invention
In a semiconductor integrated device in which a semiconductor element such as an OS device has a buried layer with a high impurity concentration between the semiconductor substrate and the semiconductor substrate, 1) a groove is dug from the surface of the semiconductor element to the buried layer and formed in the groove; 2) A groove is dug between the adjacent semiconductor elements from the surface of the semiconductor integrated device to the semiconductor substrate, and this groove forms a separation layer between the semiconductor elements. Rub to form.

[Effect]

In the semiconductor integrated device of the present invention, a trench is dug from the surface of the semiconductor element to the buried layer by a method such as etching, and a metal portion is formed in the trench by a method such as sputtering or vapor deposition. An electrode is further formed on top of this metal part. In this way, this metal part forms an extraction lead between the buried layer and the electrode. The specific resistance value of lead leads made of metal parts formed by methods such as sputtering or vapor deposition is extremely low and stable, and unlike lead leads made of conventional impurity diffusion layers, the specific resistance value may decrease due to poor diffusion of impurities. There will be no problems that will not go down. In this way, the problem of deterioration of the characteristics of the semiconductor element due to the resistance value of the lead lead is alleviated.

Furthermore, the width of the separation layer between adjacent semiconductor elements was approximately 10 μm in the conventional semiconductor integrated device using a diffusion layer, but in the present invention, the width of the separation layer between adjacent semiconductor devices can be reduced to approximately 3 μm by etching or other methods. Since it is possible to dig a groove and use this groove as a separation layer, it is possible to form a separation layer with a width of about 14 mm.

〔Example〕

As an embodiment of the semiconductor integrated device of the present invention, a bipolar
An example of a semiconductor integrated device including a npn) transistor will be explained. FIG. 1 shows a bipolar semiconductor integrated device according to the present invention.
FIG. 3 is a cross-sectional view of an npn transistor portion. 1 is a semiconductor substrate, 3 is an n-type shrimp layer, 4 is a p-type base layer, and 5 is an n-type layer.
shaped emitter layer, 6 is an emic electrode, 7 is a base electrode,
8 is a collector electrode (indicated as electrode in FIG. 1). 2
is an n-type buried layer with a high impurity concentration provided between the shrimp layer 3 and the semiconductor substrate 1, and has a low specific resistance value.

Reference numeral 10 denotes a trench extending from the surface of the bipolar npn transistor to the buried layer 2, which is dug by a method such as etching. A metal portion 9 is formed in this groove 10ζ by a method such as sputtering or vapor deposition. An electrode 8 is further formed on top of this metal part 9. In this way, this metal portion 9 forms a lead-out node between the buried layer 2 and the electrode 8. As the material used for the metal part 9, A and l are usually used. The specific resistance value of metal parts formed by methods such as sputtering or vapor deposition is extremely low and stable compared to the specific resistance value of semiconductor impurity diffusion layers. Therefore, there is no problem that the specific resistance value does not decrease due to poor diffusion of impurities. In this way, the problem of deterioration of transistor characteristics caused by the resistance value of the lead lead is eliminated.

Reference numeral 11 denotes a separation layer between adjacent elements 20, and a groove reaching from the surface of the semiconductor integrated device to the semiconductor substrate 1 is dug by a method such as etching, and this groove is used as a separation layer.

In this case, it is possible to dig a trench with a width of about 3 μm, whereas a conventional separation layer by diffusion has a width of about 10 μm, which can be reduced to about 10 μm.

〔Effect of the invention〕

According to the present invention, a groove extending from the surface of the semiconductor element to the buried layer is dug for an extraction lead between the buried layer and the electrode by a method such as etching, and a metal portion is formed in this groove by a method such as sputtering or vapor deposition. Since the conventional manufacturing method that requires a high concentration and long time diffusion process is abolished, the cost reduction effect is significant.

In addition, in the structure of the present invention in which this metal part is used as an extraction lead, the resistance between the buried layer and the electrode is extremely low and stable, and the extraction lead, which was a problem with the conventional structure based on the diffusion layer, is eliminated. This eliminates the problem of deterioration in semiconductor device characteristics caused by the failure to lower the resistance, and greatly improves the manufacturing yield.

Furthermore, the width of the separation layer between adjacent semiconductor elements was approximately 10 μm in the separation layer formed by diffusion in the conventional semiconductor integrated device, but in the semiconductor integrated device of the present invention, a trench with a width of approximately 3 μm was formed by a method such as etching. By using this groove as a separation layer, it is possible to form a separation layer with a width of about 100 mL, thereby increasing the integration density of a semiconductor integrated device by about 30 times.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a bipolar NPN transistor portion as an example of a semiconductor integrated device of the present invention, and the figure is a cross-sectional view of a bipolar NPN transistor portion as an example of a conventional semiconductor integrated device. ...Semiconductor substrate...Buried layer...Electrode...Metal part (output lead)...Groove...Groove (separation layer)

Claims (1)

[Scope of Claims] 1) A semiconductor integrated device in which a semiconductor element such as a bipolar transistor or a diffused MOS device formed on a semiconductor substrate has a buried layer with a high impurity concentration between it and the semiconductor substrate, 1. A semiconductor integrated device characterized in that a groove is dug from a surface of a semiconductor element to a buried layer, and a metal portion formed in the groove forms an extraction lead for the buried layer. 2) The semiconductor integrated device according to claim 1, characterized in that a groove is dug between adjacent semiconductor elements from the surface of the semiconductor integrated device to the semiconductor substrate, and this groove forms a separation layer between the semiconductor elements. semiconductor integrated devices.