JPH022226A - Optical output stabilizing circuit - Google Patents

Optical output stabilizing circuit

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Publication number
JPH022226A
JPH022226A JP63143342A JP14334288A JPH022226A JP H022226 A JPH022226 A JP H022226A JP 63143342 A JP63143342 A JP 63143342A JP 14334288 A JP14334288 A JP 14334288A JP H022226 A JPH022226 A JP H022226A
Authority
JP
Japan
Prior art keywords
optical
output
mark rate
circuit
optical output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63143342A
Other languages
Japanese (ja)
Other versions
JP2643988B2 (en
Inventor
Haruo Yamashita
治雄 山下
Tomoyuki Otsuka
友行 大塚
Ryuichi Kondo
竜一 近藤
Hidetoshi Naito
内藤 英俊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
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Fujitsu Ltd
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Filing date
Publication date
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Priority to JP63143342A priority Critical patent/JP2643988B2/en
Publication of JPH022226A publication Critical patent/JPH022226A/en
Application granted granted Critical
Publication of JP2643988B2 publication Critical patent/JP2643988B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Optical Communication System (AREA)

Abstract

PURPOSE:To prevent deterioration in the optical output waveform against the fluctuation of the combination of mark rates by detecting each mark rate of 2 systems of data strings and using a sum signal of the detection signal so as to adjust a reference voltage, varying the bias current of a light emitting diode to adjust the optical output. CONSTITUTION:A mark rate detection circuit 16 consists of low pass filter comprising a resistor R1 and a capacitor C1 and a mark rate detection circuit 17 consists of low pass filter comprising a resistor R2 and a capacitor C2. An optical output detection circuit 15 consists of a photodiode PD, a resistor R and a capacitor C to extract a mean value and when the optical level is increased, an output VPD is lowered, and the optical level is decreased. When the optical level is decreased, the relation is opposite to above and then the constant control (APC) of the optical level is implemented in this way. The reference voltage of the APC is given by an offset circuit 19. The sum of outputs VMD1, VMD2, of the mark rate detection circuits 16, 17 revises the reference voltage to correct the mark rate.

Description

【発明の詳細な説明】 〔発明の概要〕 光3値伝送方式における光出力安定化回路に関し、 2系統のデータ列のそれぞれのマーク率の組合せの変動
に対しても光出力波形の劣化を起さない光出力安定化回
路を提供することを目的とし、自動パワー制御回路を持
つ発光素子を備えて、第1のデータ列で光出力を一方向
に変え、第2のデータ列で逆方向に変えて、光出力上で
第1.第2のデータ列を多重化する光3値伝送方式にお
ける光出力安定化回路において、第1のデータ列のマー
ク率を検出する回路と、第2のデータ列のマーク率を検
出する回路と、これらの検出回路の出力の加算回路を備
え、該加算回路の出力で前記自動パワー制御回路の基準
電圧を調整してマーク率補償するように構成する。
[Detailed Description of the Invention] [Summary of the Invention] Regarding an optical output stabilization circuit in an optical ternary transmission system, the optical output waveform is deteriorated even when the combination of mark rates of two data streams changes. The purpose of the present invention is to provide a light output stabilizing circuit which is equipped with a light emitting element having an automatic power control circuit, and which changes the light output in one direction with the first data string and in the opposite direction with the second data string. Change the light output to 1st. In an optical output stabilization circuit in an optical ternary transmission system that multiplexes a second data string, a circuit that detects a mark rate of a first data string, a circuit that detects a mark rate of a second data string; An adder circuit for the outputs of these detection circuits is provided, and the reference voltage of the automatic power control circuit is adjusted using the output of the adder circuit to compensate for the mark rate.

〔産業上の利用分野〕[Industrial application field]

本発明は、光3値伝送方式における光出力安定化回路に
関する。
The present invention relates to an optical output stabilizing circuit in an optical three-value transmission system.

2系統のデータ列を光出力上で多重化する光3値伝送方
式(M −T P C: Modified Time
 Polarity Contro1)がある。第5図
にその概要を示す。
Optical ternary transmission method (M-TPC: Modified Time) that multiplexes two data streams on optical output.
Polarity Control 1). Figure 5 shows the outline.

(a)は原データで2系統のデータ列D1とD2からな
る。本例ではデータ列DIは10110.データ列D2
は10010であり、実線間がこれらのデータの1ビツ
トの間隔である。(b)はこれらを多重化した送信デー
タ(光出力M−TPC)で、データ列D1の各1ビツト
間隔の前半(奇数スロット)が1なら正パルス、0なら
0、そしてデータ列D2の各1ビツト間隔の後半(偶数
ビット)が1なら負パルス、0なら0として得られる。
(a) is the original data and consists of two systems of data strings D1 and D2. In this example, the data string DI is 10110. Data string D2
is 10010, and the interval between solid lines is 1 bit of these data. (b) is the transmission data (optical output M-TPC) obtained by multiplexing these.If the first half (odd slot) of each 1-bit interval of the data string D1 is 1, it is a positive pulse, if it is 0, it is 0, and each of the data string D2 is If the second half (even numbered bit) of one bit interval is 1, a negative pulse is obtained, and if it is 0, a 0 is obtained.

なお光出力M−TPCでは上記正パルスは光出力が大、
0は中、負パルスは小(または0)である。(C)は受
信出力から再生されるクロックで位相0のCLKlと位
相πのCLK2からなり、これらはデータ列Di、D2
からπ/2ずれている。クロックCLKIの立上りで(
b)の光出力M−TPCを読み、正なら立上げ、0なら
立下げると(d)のデータDIが得られ、CLK2の立
上りで光出力M−TPCを読んで負なら立上げ、0なら
立下げると(d)のデータD2が得られ、こうして送信
データ(a)の復調出力(d)が得られる。
In addition, in the optical output M-TPC, the above positive pulse has a large optical output,
0 is medium, negative pulse is small (or 0). (C) is a clock regenerated from the received output, consisting of CLKl with phase 0 and CLK2 with phase π, which are the data strings Di, D2
It deviates from π/2. At the rising edge of clock CLKI (
Read the optical output M-TPC in b), and if it is positive, raise it, and if it is 0, lower it, and the data DI in (d) is obtained.Read the optical output M-TPC at the rising edge of CLK2, and if it is negative, raise it, and if it is 0, then it will fall. When the signal falls, data D2 (d) is obtained, and thus the demodulated output (d) of the transmitted data (a) is obtained.

本発明はか\る光3値伝送方式における、マーク率によ
る光出力の変動をな(す回路に係るものである。
The present invention relates to a circuit for varying the optical output depending on the mark rate in such an optical three-value transmission system.

〔従来の技術〕[Conventional technology]

光2値伝送方式では、マーク率変動を考慮した光出力安
定化回路は知られている。しかし光3値伝送方弐では、
2系統のデータ列の任意のマーク率の組合せに対して補
償する光出力安定化回路は未だ提案されていない。これ
は、光2値伝送が一般的で、光3値など光多値伝送方式
の開発は十分進んでいない為でもある。しかし、多チャ
ンネルのテレビ信号を多重化して光デイジタル伝送を行
なう等の場合、より多くのチャンネルのテレビ信号の伝
送方式として光多値伝送方式は重要であり、つれて光多
値伝送方式における光出力安定化回路は重要である。
In the optical binary transmission system, an optical output stabilization circuit that takes mark rate fluctuations into consideration is known. However, in the optical three-level transmission method,
An optical output stabilization circuit that compensates for any combination of mark rates of two data streams has not yet been proposed. This is also because optical binary transmission is common, and the development of optical multilevel transmission systems such as optical ternary has not progressed sufficiently. However, in cases such as multiplexing multi-channel television signals and performing optical digital transmission, the optical multilevel transmission system is important as a transmission method for television signals of more channels, and as the optical multilevel transmission system Output stabilization circuits are important.

マーク率による光出力波形の変化を第6図に示す。(a
)はデータ列DIとD2のマーク率MRが共に1/2の
場合、(b)はデータ列D1のマーク率が172より大
、(C)は同1/2より小の場合で、データ列D2はい
ずれの場合もMR=1/2とする。なおマーク率は、各
データ列Di、D2について所定期間のオン/オフ比を
とったものである。(a)ではデータD2の1は0、デ
ータD1の1は1とすると、(b)では全体が下ってつ
ぶれた状態になり、(C)では全体が上がって消光比が
劣化する(D2の1が0にならない)。これはAPCに
より平均光出力が同じであるように制御されているため
で、マーク率が共に1/2のときは(d)に示すように
予定の状態にセット(Diの1が1.0は0.5、D2
の1は0になるように入力をセット)にセットされてい
ても、Dlのマーク率が大になると、平均光出力を不変
にすべ(Fz力方向のシフトが生じて(b)の状態にな
り、逆にDlのマーク率が小になるとやはり平均光出力
を不変にすべくF、方向へのシフトが生じて(C)の状
態になる。
FIG. 6 shows changes in the optical output waveform depending on the mark rate. (a
) is when the mark ratio MR of data strings DI and D2 are both 1/2, (b) is when the mark ratio of data string D1 is larger than 172, and (C) is when the mark ratio is smaller than 1/2. D2 is set to MR=1/2 in both cases. Note that the mark rate is the on/off ratio for a predetermined period for each data string Di, D2. In (a), the 1 of data D2 is 0, and the 1 of data D1 is 1. In (b), the whole goes down and collapses, and in (C), the whole goes up and the extinction ratio deteriorates (D2's 1). (1 does not become 0). This is because the average light output is controlled by APC to be the same, and when both mark rates are 1/2, the planned state is set as shown in (d) (1 of Di is 1.0 is 0.5, D2
1 is set to 0), when the mark rate of Dl becomes large, the average optical output remains unchanged (a shift in the Fz force direction occurs, resulting in state (b)). On the other hand, when the mark rate of Dl becomes small, a shift in the F direction occurs in order to keep the average optical output unchanged, resulting in the state (C).

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

本発明は、光3値伝送方式において、2系統のデータ列
のそれぞれのマーク率の組合せの変動に対しても光出力
波形の劣化を起さない光出力安定化回路を提供すること
を目的とするものである。
SUMMARY OF THE INVENTION An object of the present invention is to provide an optical output stabilizing circuit that does not cause deterioration of the optical output waveform even when the combination of mark rates of two data streams changes in an optical three-value transmission system. It is something to do.

〔課題を解決するための手段〕[Means to solve the problem]

第1図に本発明の構成を示す。10は発光素子で、光出
力を生じる。11.12はデータ列DI。
FIG. 1 shows the configuration of the present invention. 10 is a light emitting element that produces light output. 11.12 is the data string DI.

D2により駆動され、発光ダイオード10を駆動する。D2 and drives the light emitting diode 10.

13は光出力検出回路、14は発光ダイオード10のバ
イアス電流を制御する回路、15は該回路14へ基準電
圧を供給する電圧源である。
13 is a light output detection circuit, 14 is a circuit for controlling the bias current of the light emitting diode 10, and 15 is a voltage source for supplying a reference voltage to the circuit 14.

これらの13.14.15は発光ダイオード10に対す
るAPC(八utomatic Power Cont
rol C1rcuit)回路を構成する。16.17
は、データ列D1、D2の各マーク率を検出する回路で
ある。18は加算回路で、マーク率検出回路16.17
の出力を加算し、その結果により基準電圧15を調整す
る。
These 13.14.15 are the APC (8 automatic power control) for the light emitting diode 10.
rol C1rcuit) circuit. 16.17
is a circuit that detects each mark rate of the data strings D1 and D2. 18 is an addition circuit, mark rate detection circuit 16.17
, and adjust the reference voltage 15 based on the result.

〔作用〕[Effect]

本発明では2系統のデータ列Di、D2の各マーク率を
回路16.17で検出し、この検出信号の加算(物理的
な意味では減算)信号で基準電圧15を調整し、発光ダ
イオード10のバイアス電流を変えて光出力を調整する
。調整後の光出力(相対光出力)の−例を次表に示す。
In the present invention, each mark rate of the two data strings Di and D2 is detected by the circuits 16 and 17, and the reference voltage 15 is adjusted by the addition (subtraction in a physical sense) signal of this detection signal, and the reference voltage 15 is Adjust the optical output by changing the bias current. An example of the adjusted light output (relative light output) is shown in the table below.

表   1 単位:dBr この表に示すようにデータ列D1とD2のマーク率が共
に1/8.1/4.・・・・・・7/8で等しいときは
基準電圧の補正はしない(相対光出力は0.Odlr)
Table 1 Unit: dBr As shown in this table, the mark rates of data strings D1 and D2 are both 1/8.1/4.・・・・・・When the ratio is equal to 7/8, the reference voltage is not corrected (relative light output is 0.Odlr)
.

Dlのマーク率がD2のマーク率より高くなるとその程
度に従って相対光出力を大にし、逆にDlのマーク率が
D2のマーク率より小になると相対光出力を小にする。
When the mark rate of Dl becomes higher than the mark rate of D2, the relative optical output is increased according to the degree, and conversely, when the mark rate of Dl becomes lower than the mark rate of D2, the relative optical output is decreased.

これにより光出力波形のつぶれ、消光比の劣化を回避す
ることができる。
This makes it possible to avoid distortion of the optical output waveform and deterioration of the extinction ratio.

第5図(b)および第6図(d)などから明らかなよう
に、正(増大側)パルスとなるデータ列D1のマーク率
が高いと平均光出力は大になり、負(減少側)パルスと
なるデータ列D2のマーク率が高イと平均光出力は小に
なる。APCはこれを一定化するので、第6図(b)(
C)のようにOレベル(データ列Di、D2がOのとき
の光出力)が変動して、平均パワーが一定になるように
する。マーク率補償は該Oレベルが不変になるようにす
る。勿論、この制御はマーク率(の組合せ)に対してだ
け行なわれ、電源電圧変動、経年変化、その他の光出力
変化に対して行なわれるのではな(、該電源電圧変動な
どによる光出力変化などはAPCにより除かれる。
As is clear from FIG. 5(b) and FIG. 6(d), when the mark rate of the data string D1, which is a positive (increasing side) pulse, is high, the average optical output becomes large, and when it is negative (decreasing side) When the mark rate of the data string D2 that becomes a pulse is high, the average optical output becomes small. Since APC makes this constant, Figure 6(b) (
As shown in C), the O level (optical output when the data strings Di and D2 are O) is varied so that the average power becomes constant. Mark rate compensation ensures that the O level remains unchanged. Of course, this control is performed only on (combinations of) mark rates, and not on power supply voltage fluctuations, secular changes, and other optical output changes (such as optical output changes due to power supply voltage fluctuations, etc.). is removed by APC.

〔実施例〕〔Example〕

第2図に本発明の実施例を示す。マーク率検出回路16
は抵抗R8とキャパシタCIのローパスフィルタで構成
し、これにデータ列D1の反転信号DIを加える。出力
VMDIは第3図(b)の如くなる。
FIG. 2 shows an embodiment of the present invention. Mark rate detection circuit 16
is composed of a low-pass filter including a resistor R8 and a capacitor CI, and an inverted signal DI of the data string D1 is added thereto. The output VMDI is as shown in FIG. 3(b).

同様にマーク率検出回路17は抵抗R2とキャパシタC
2のローパスフィルタで構成し、これにデータ列D2の
反転信号D2を加える。出力■HDtは第3図(C)の
如くなる。これらはマーク率に対して逆の傾きを持つが
、RCの値を調整して傾きの絶対値は等しくする。この
ようにすると、データ列D1とD2の各マーク率が等し
ければ加算制御信号ΔVMIII + ΔVMDZは0
、DI(7)?−”率が大なら負、Dlのマーク率が小
なら正、とすることができる。なおΔV M D I 
r ΔvMozはマーク率がl/2の時を基準にした時
の変動量を示す。
Similarly, the mark rate detection circuit 17 includes a resistor R2 and a capacitor C.
2 low-pass filters, and an inverted signal D2 of the data string D2 is added thereto. The output ■HDt is as shown in FIG. 3(C). Although these have slopes opposite to the mark rate, the absolute values of the slopes are made equal by adjusting the value of RC. In this way, if the mark rates of data strings D1 and D2 are equal, the addition control signal ΔVMIII + ΔVMDZ becomes 0.
, DI(7)? −” If the rate is large, it can be negative, and if the mark rate of Dl is small, it can be positive. Note that ΔV M D I
r ΔvMoz indicates the amount of variation when the mark rate is 1/2 as a reference.

光出力検出回路13はホトダイオードPDと、平均値を
取出すための抵抗RおよびキャパシタCで構成し、出力
VPDは第3図(a)の如くなる。即ち光レベルが増大
すると出力■、は下り、従ってオペアンプOPの出力が
下り、トランジスタQの導通度が下ってバイアス電流I
、が減少し、光レベルが下る。光レベルが減少したとき
はこの逆であり、こうして光レベルの一定化制御(AP
C)が行なわれる。このAPCの基準電圧はオフセット
回路19が与える。マーク率検出回路16.17の出力
■。I+  vMD!の和はこの基準電圧を変更し、マ
ーク率補正を行なう。
The optical output detection circuit 13 is composed of a photodiode PD, a resistor R for taking out an average value, and a capacitor C, and the output VPD is as shown in FIG. 3(a). In other words, as the light level increases, the output (2) decreases, so the output of the operational amplifier OP decreases, the conductivity of the transistor Q decreases, and the bias current I decreases.
, decreases and the light level falls. The opposite is true when the light level decreases, and thus constant light level control (AP
C) is performed. An offset circuit 19 provides a reference voltage for this APC. Mark rate detection circuit 16.17 output ■. I+vMD! The sum changes this reference voltage and performs mark rate correction.

光出力検出回路13の出力の傾きは加算制御信号の傾き
に合わせる。光検出回路の出力が光レベル増大で減少す
る(これを正の方向とする)なら、加算制御信号も正の
方向で変化し、逆に光検出回路の出力が光レベル増大で
増大する(負の方向)なら、加算制御信号も負の方向で
変化する。これは抵抗Rとキャパシタqにより行なう。
The slope of the output of the optical output detection circuit 13 is matched to the slope of the addition control signal. If the output of the photodetector circuit decreases as the light level increases (this is taken as a positive direction), the addition control signal also changes in the positive direction, and conversely, the output of the photodetector circuit increases as the light level increases (this is taken as a negative direction). direction), the addition control signal also changes in the negative direction. This is done using a resistor R and a capacitor q.

第4図に本発明の他の実施例を示す。本例ではデータ列
D1は電界効果トランジスタQ、のゲートに加えられ、
またデータ列D2は電界効果トランジスタQ、のゲート
に加えられ、マーク率検出および加算はこれらのトラン
ジスタと抵抗R3〜R6、キャパシタC3で行なわれ、
加算信号はノードN1に得られ、抵抗R1を通してオペ
アンプOPIの一人力に加えられる。基準電圧15は該
オペアンプの十人力に加えられ、このオペアンプの出力
がフィルタを通してオペアンプOP3の一人力に加えら
れる。光検出回路の出力は、電圧フォロアOP zを構
成するオペアンプOP2を介して上記オペアンプOP3
の一人力に入り、このオペアンプOF3の出力がトラン
ジスタQ2を制御し、ひいてはレーザダイオード10の
発光を制御する。
FIG. 4 shows another embodiment of the invention. In this example, the data string D1 is applied to the gate of the field effect transistor Q,
Further, the data string D2 is applied to the gate of the field effect transistor Q, and mark rate detection and addition are performed by these transistors, resistors R3 to R6, and capacitor C3.
The summation signal is obtained at node N1 and is applied to the output of operational amplifier OPI through resistor R1. A reference voltage 15 is applied to the output of the operational amplifier, and the output of this operational amplifier is applied to the output of the operational amplifier OP3 through a filter. The output of the photodetection circuit is sent to the operational amplifier OP3 via the operational amplifier OP2 that constitutes the voltage follower OPz.
The output of the operational amplifier OF3 controls the transistor Q2, which in turn controls the light emission of the laser diode 10.

このオペアンプOP、でマーク率による基準電圧の調整
が行なわれ、そしてオペアンプOP3で該調整された基
準電圧を用いたAPCが行なわれる。データ列DI、D
2によるレーザダイオード100発光制御は10  R
:+  Q+、10  Rb−Q2の径路で行なわれる
The operational amplifier OP adjusts the reference voltage according to the mark rate, and the operational amplifier OP3 performs APC using the adjusted reference voltage. Data string DI, D
Laser diode 100 emission control by 2 is 10 R
:+Q+, 10 Performed on the path Rb-Q2.

〔発明の効果] 以上説明したように本発明によれば、APC回路を備え
、2系統のデータを光出力で多重化して伝送する光3値
伝送方式で生じる、各系統のマーク率の差による光出力
波形の劣化を防止でき、多チャンネルTV信号の伝送な
どに有効である。
[Effects of the Invention] As explained above, according to the present invention, the difference in mark rate between each system, which occurs in an optical ternary transmission system that includes an APC circuit and multiplexes and transmits two systems of data using optical output, It can prevent deterioration of the optical output waveform and is effective in transmitting multi-channel TV signals.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の原理説明図、 第2図は本発明の実施例を示す回路図、第3図は第2図
の動作説明用の特性図、第4図は本発明の他の実施例を
示す回路図、第5図は光3値伝送方式の説明図、 第6図はマーク率による光出力波形劣化の説明図である
。 第1図で10は発光素子、DIは第1のデータ列、D2
は第2のデータ列である。
Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a circuit diagram showing an embodiment of the invention, Fig. 3 is a characteristic diagram for explaining the operation of Fig. 2, and Fig. 4 is another embodiment of the invention. A circuit diagram showing an example, FIG. 5 is an explanatory diagram of an optical three-value transmission system, and FIG. 6 is an explanatory diagram of optical output waveform deterioration due to mark rate. In FIG. 1, 10 is a light emitting element, DI is the first data string, and D2
is the second data string.

Claims (1)

【特許請求の範囲】 1、自動パワー制御回路(13、14、15)を持つ発
光素子(10)を備えて、第1のデータ列(D1)で光
出力を一方向に変え、第2のデータ列(D2)で逆方向
に変えて、光出力上で第1、第2のデータ列を多重化す
る光3値伝送方式における光出力安定化回路において、 第1のデータ列のマーク率を検出する回路(16)と、
第2のデータ列のマーク率を検出する回路(17)と、
これらの検出回路(16、17)の出力の加算回路(1
8)を備え、 該加算回路の出力で前記自動パワー制御回路の基準電圧
(15)を調整してマーク率補償するようにしてなるこ
とを特徴とする光出力安定化回路。
[Claims] 1. A light emitting element (10) having an automatic power control circuit (13, 14, 15) is provided, the light output is changed in one direction by the first data string (D1), and the light output is changed in one direction by the first data string (D1). In an optical output stabilization circuit in an optical ternary transmission system that multiplexes the first and second data streams on the optical output by changing the data stream (D2) in the opposite direction, the mark rate of the first data stream is a detection circuit (16);
a circuit (17) for detecting the mark rate of the second data string;
An adder circuit (1) for the outputs of these detection circuits (16, 17)
8), wherein the reference voltage (15) of the automatic power control circuit is adjusted by the output of the adder circuit to compensate for the mark rate.
JP63143342A 1988-06-10 1988-06-10 Optical output stabilization circuit Expired - Lifetime JP2643988B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63143342A JP2643988B2 (en) 1988-06-10 1988-06-10 Optical output stabilization circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63143342A JP2643988B2 (en) 1988-06-10 1988-06-10 Optical output stabilization circuit

Publications (2)

Publication Number Publication Date
JPH022226A true JPH022226A (en) 1990-01-08
JP2643988B2 JP2643988B2 (en) 1997-08-25

Family

ID=15336558

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63143342A Expired - Lifetime JP2643988B2 (en) 1988-06-10 1988-06-10 Optical output stabilization circuit

Country Status (1)

Country Link
JP (1) JP2643988B2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50134705A (en) * 1974-04-15 1975-10-25
JPS51147984A (en) * 1975-06-14 1976-12-18 Fujitsu Ltd Method of stabilizing the outputs of semiconductor lasers
JPS5531323A (en) * 1978-08-29 1980-03-05 Fujitsu Ltd Automatic gain control system for optical communication reception system
JPS6238044A (en) * 1985-08-12 1987-02-19 Matsushita Electric Ind Co Ltd Automatic output control device for mark rate compensation

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50134705A (en) * 1974-04-15 1975-10-25
JPS51147984A (en) * 1975-06-14 1976-12-18 Fujitsu Ltd Method of stabilizing the outputs of semiconductor lasers
JPS5531323A (en) * 1978-08-29 1980-03-05 Fujitsu Ltd Automatic gain control system for optical communication reception system
JPS6238044A (en) * 1985-08-12 1987-02-19 Matsushita Electric Ind Co Ltd Automatic output control device for mark rate compensation

Also Published As

Publication number Publication date
JP2643988B2 (en) 1997-08-25

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