JPH02222860A - Alarm speech/time holder - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Background of the Invention] In recent years, people have been living according to schedules. People in important positions may have secretaries who remind them of important appointments, but most people use notebooks to write down upcoming dates. Sometimes people forget important appointments. To solve this problem, some people use alarm clocks or alarm watches, which remind the person of the time but do not do anything. It doesn't remind you what to do.Furthermore, an alarm clock or watch -
You can only set the time once per session. SUMMARY OF THE INVENTION It is an object of the present invention to provide a multi-time alarm clock/watch that utilizes speech storage and playback technology. This technology uses pre-stored voice messages as alarm signals that specifically remind people what to do when the appropriate time comes. There are different variations of alarm clocks depending on different alarm mechanisms. For example, an alarm clock can generate music, speech, animal sounds, etc.

These alarm sounds are completely fixed and cannot be changed after they are manufactured.

The present invention is different from what has been described above. The device is configured to generate a speech message previously stored by the user when the corresponding time has arrived.

U.S. Patent No. 4, 4 by Mr. Aibari et al.
No. 05.241 ``Electronic devices with timepiece function'' proposes replacing musical tones or beeps with pre-ordered messages as alarm signals for clocks or watches. However, in the Aybara device, the time and message stored in the memory section are set externally. This external setting switch selects the alarm memory part o ” to “3”
It consists of switches such as This method has the disadvantage that if the user forgets whether a certain part has already been stored, he has to check the stored parts one by one. The present invention differs from the Aibara patent in that the storage portion is automatically selected rather than externally determined. After the alarm signal is generated, the circuit is configured to automatically erase the used message and make the used memory portion reusable for new messages that need to be stored.

In the Aybara patent, the alarm time and speech information were stored together and could not be separated.

The present invention has separate parts for storing warning time and speech. The stored speech can be played back for use as a message machine.

SUMMARY OF THE INVENTION 1 The present invention relates to a resettable alarm clock using speech as an alarm signal.

This signal is combined and stored digitally in memory. When the alarm time arrives, the alarm clock outputs a signal to trigger the speech storage/playback device to generate pre-stored speech messages in chronological order.

For example, if the user of the device first says ``Party, 7 p.m.''
You can set a first message such as ``Meeting at 10am'' and then a second message such as ``Meeting at 10am''. In that case, the device first outputs the second message when the relevant time of 10 am arrives, and then outputs the first message when the relevant time of 7 pm arrives.

The comparison circuit included in the present invention operates to output randomly selected preset times and sounds on time.

[Description of Embodiments] FIG. 1 shows a block diagram configuring the present invention. Block l is a numeric type digital time display. Block 2 is a time holding circuit with a presettable alarm function, which circuit can be set to one or more times, regardless of any previously set time, and is valid if the circuit is not reset. retained as something.

When setting the alarm time, audio is also input from block 4, which converts the audio into an electrical signal and outputs it to block 3. Block 3 is a speech processing device that digitizes the audio signal into “o” and “l”;
The digital signal is output to block 6 and stored there. When the preset alarm time arrives,
Block 2 outputs a signal to trigger block 3.

Block 3 reads out the digital signal stored from block 6 and converts the digital signal into an analog signal for output by means of block 5. Block 5
The output of is an audible signal.

Time keeping circuit (clock/watch) 2 in Figure 1
The details are shown in FIG. The circuit has 8 wave numbers 327
It includes a crystal oscillator 201 with a frequency of 68 Hz, which frequency is divided by a frequency divider 202 to count seconds, minutes, and hours. clock/watch 2
allows you to reset four different times in any order. When the preset time arrives, the clock/watch sends out a signal. The entire cycle of clock/watch 2 is shown in FIG. In Figure 2 j2,
Decoder 211 converts the seconds, minutes, hours time signal into a seven segment hood for numeric type display 213. The terminal 351 is for supplying a positive power supply Vdd, and the terminal 350 is for supplying a negative power supply Vss.

In the present invention, the time keeping device 2 has two modes determined depending on the state of the input at the terminal 233. If the signal at terminal 233 is "0", the device can adjust the time in normal mode.

When terminal 233 becomes "1", the device goes into alarm mode and time can be set. In alarm mode, speech and preset alarm times are entered. Input 234 is for minute settings. A "0" at input 235 means inactive, while a "1" allows increments of 1 minute every 5 seconds up to 59 minutes. Terminal 23
3. The input means at 234 and 235 allow the desired time to be set or adjusted.

In alarm mode, when input 236 receives a positive pulse activation signal, time data is transferred from control circuit 205 to I1.
0 circuit 208 and then to RAM 210. The address of the time data is transferred to the speech memory (
memory). Meanwhile, a positive pulse activation signal at terminal 236 triggers the speech memory to store the audio. FIG. 3 shows a block diagram illustrating the speech storage and reproduction device 3 of FIG. 1 in detail. In the present invention, the technique of Continuously Variable Slope Delta Modulation (CV SD) is adapted for speech storage and playback devices. The device includes a CVSD circuit 34, an oscillator circuit 32, a control/interface circuit 31, an address generator and a DRAM interface 33. Each circuit is configured as follows.

In FIG. 3, line 301 is an input terminal for analog signals. External input signals are input here for decoding. The level of the input signal input to the inverting input terminal of the internal comparator can reach OdBm (1,1v). DC bias is supplied from Vrf 302 or externally. SF is a non-inverting V/I conversion input terminal.
Terminal 303 of r) connects a 0.3 microfarad capacitor 380 to Vdd for slope control of the integrator of the CVSD circuit. The input voltage Vdd of this terminal is in the range of 1.5V to 40mV. FI (filter input) 304 is a non-inverting input terminal of the integrator. F connected in series with the terminal 304 and the capacitor 380
The O (filter output) terminal 3o5 forms an integrator network. Vrf302 is 172 of the Vdd reference voltage, and it outputs a current of 5mA. 306 (O5
CI) and 307 (O3C2) are the two terminals of the oscillation circuit. Terminal 306 has a 160 to ohm resistor 382
is connected to terminal 307 to generate a frequency of 192KHz. Terminal 308 is for audio output. Address code inputs 311 and 312 determine the portion of memory for recording and playback audio. (Reproduction) terminal 313 is a reproduction control terminal triggered by a positive pulse to start reproduction. The (record) terminal 314 controls the recording portion triggered by a positive pulse. (Clear) terminal 315 is a clear control terminal for clearing the speech memory when triggered by a positive pulse. After recording and reproducing, the (STP) terminal 316 outputs a positive pulse signal and becomes L.
Drives ED.

Terminals 320-323 are for DRAM row address strobe signals, and terminals 320-323 are respectively referred to as CASI-CAS4.

Terminals 330 to 339 are for outputting the composite address and are directly connected to the DRAM address.

Terminal 340 (RAS) is connected to memory portions 600 to 603.
is connected to the column address of the DRAM containing the
This is for DRAM column address strobe signal. terminal 3
The input at 41 (WD) controls writing and reading of the DRAM. If WR is 'l''', the data is D
Read from RAM. If WR is "θ", data is written to DRAM. Terminal 309 (DO) is an output terminal for an encoded digital signal, and terminal 310 (DO) is an output terminal for an encoded digital signal.
DI) is an input terminal for the decoded digital signal.

The digital signal input is input to the CVSD synthesis circuit, converted to an analog signal, and output to the terminal 308 (AID). Terminal 340 is connected to ground level Vss, and terminal 351 is connected to power supply Vdd. Terminals 221 and 222 in FIG. 2 are crystal oscillators 223 and 3276
It is connected to an oscillation circuit 201 that generates a frequency of 8 Hz. The frequency is input to frequency divider 202 to generate seconds, minutes, and hours counts that are stored in read only memory (ROM) 207.

The splitter 202 also outputs a 64 Hz signal to the circuit 212 for latching and driving data.

Frequency divider 202 sends a clock signal to voltage doubler circuit 203 to double the supplied voltage. display 2
13 displays the time obtained in the circuit 212.

In FIG. 2, an input/output circuit (Ilo) 208 sends signals to a random access memory (RAM) and a programmable logic array (PLA) 206, receives signals from these, and stores and executes a time keeping command. . The control circuit 205 has terminals 233 (Sl), 234
It receives and receives signals from (S2), 235 (S3), and 236 (S4), and sets the time. The alarm control circuit 204 has terminals 230 (ALO) and 231 (Al
1), outputs a control signal to 232 (Al1).

When terminal 230 becomes a logic "1", the audio is activated. The address signal in m child 231 (ALL) is “θ
'' and the signal at terminal 232 (Al1) is ``0'', the device outputs the contents stored in section l (first section) of the RAM.

When address signal ALI is 1'' and Al1 is 0''',
The device outputs the contents of section 2 of RAM. Address signal ALL is “θ” and Al1 is “
If the address signal ALI is 1'', the device outputs the contents of section 3 (third section). If the address signal ALI is 1'' and Al1 is ``1'', the device outputs the contents of section 4 (fourth section).

The RAM 210 is composed of eight 8x4 matrices, four of which are used for command execution, and the remaining four matrices are divided into four sections 60.
It is divided into 0 to 603. Each section stores alarm mode time setting information. When power is supplied, all contents of the RAM become "O". When the alarm setting information is input, it is first determined whether alarm time information is preset in the first section 600.

If alarm time information is set in this section, the second section 601 is similarly determined.

If no alarm time information is stored in the first section, new alarm time information is stored in the first section 600 of the RAM. The same #a7=sequential alarm time information is also stored in the 2.3.4 sections 601, 602, and 603. If alarm time information is stored in all sections, the items stored in the fifth section will cause the display 210 to flash a "FFFF" message indicating that there is no longer free memory space. inform the person. It should be noted that the set alarm time information is not related to the order in which alarms are set.

Once the alarm time has been preset and the speech message has been stored, the contents of RAM 210 are compared minute by minute with the contents of time circuit 212. When both contents match, an alarm signal is outputted via the alarm control circuit 204, and the control circuit sends an output "1#' to the alarm energizing terminal ALO, and a different combination of address codes to the terminals ALL and Al1. i.e. the first section of memory 600
0.0 for the second section 601, 011 for the third section 602, 1.0 for the third section 602,
For the fourth section, output 1.0. By doing this, the speech information in memory is matched to the alarm time.

When the preset time arrives, that is, time up, A
LO-Al1 outputs a digital signal to the speech storage block 3 and outputs the corresponding speech information. Then R
The information stored in AM 210 is cleared and this already used memory section is made available for new alarm time information. However, if new speech information is not stored in place of the already stored speech information, the speech information is not deleted.

An application circuit of the present invention is shown in FIG. switch 3
When 69 is closed by external operation, a positive pulse is output to terminal 314 (record) and terminal 236, and the alarm time information and speech information storage/reproduction device starts storing.

The audio signal is input from the microphone 411 and is sent to the amplifier 4.
15 and is amplified by terminal 301 (A
I) J, m input and decoded output terminal 309
(DO) in sections 600-603 of memory. When the preset time arrives, time holding circuit 2 sends an energizing signal to terminal 313 (regeneration) via line 230 and from terminals 231 and 232 to terminal 311.
and 312. Speech storage and reproduction bag R3 reads address data from the memory via terminal 310 (Do). The audio signal for speech is
It is converted into an analog signal and output from the terminal 308, amplified by the amplifier 504 and finally sent to the speaker 50g.
is output from.

In Figure 4, terminals 313 (play) and 314 (record)
can be connected to switches 360 and 361, respectively. If switch 360 is turned on, a positive pulse is sent to counter 366 to set the address of the speech storage and playback device and input audio. If switch 3
When 61 is turned on, counter 366 sets the speech output address and outputs speech data. The main functions of switches 360 and 361 are to directly control the storage playback of speech from the outside and to check internal data in memory.

Switch 371 inputs a positive pulse to terminal 315 to reset the data in memory.

The above description merely describes the function of the various parts of the invention. An example of a usage state in which a preset is executed is shown in FIG. The memory 601 stores warning time information of, for example, 18:30 (block 71O), and also stores speech information corresponding to that time. Timer 212 checks whether the first section of memory already stores information. If nothing is remembered, (
Preset time information (at block 710) and preset speech (message) information (at block 711), such as "Dinner at Hilton Hotel at 7 p.m.", are stored in a first section of memory (at block 710).
block 702). Next, preset the alarm time to 8:30 a.m. (block 712), and preset the speech information "Discuss with Manager" (block 713).
, both information is stored in a second section of memory (block 703). Then set the alarm time and speech information “Planning meeting at 2:00 pm in conference room 230” in block 7.
14.715), set it to the third section of memory threshold, phone number 754321" block 716
．． 717) and storing it in a fourth section of memory (block 705). This means that all memory spaces have been stored.

Furthermore, the alarm time and message information will be displayed on the display.
Display F'' (block 706) indicates that the memory is full and no more information can be stored.

A usage flowchart for normal alarm operation is shown in Figure 6. When the clock indicates 8:30 a.m., the audio message "Talk to Manager" is spoken (block 801).

Thereafter, the preset times and messages stored in the second section are zeroed out (block 80).
2) A new alarm time and message can be entered into this second section of memory.

(block 803) and erases the fourth section of memory (block 804). At 2:00 p.m., the device sends an audio message: ``Planning meeting in conference room 230.''
(block 805) and erases the third section of memory (block 806). At 6:30 p.m., the device will issue a voice message saying “Dinner at 7 p.m.”
utter.

This allows the user to change clothes for dinner and arrange transportation.

If the user goes to a meeting at 2:00 p.m., 'Conference room 230
This allows the messages of the planning meeting to remain in the third section of memory without being erased. If another person is looking for the user, they can find out where the user is by turning on the play button.

This device can therefore also be used as a message machine.

The time keeping device of the present invention can be constructed with a 4 or 8 bit microcomputer chip. The speech storage and playback device designed by the inventor is capable of performing this function. 256K DRAM (format 4
Memory devices such as 1256) and amplifiers such as type 325 can be used as components. Other components of the embodiments of the present invention may also be used, and
Various modifications of the invention will readily occur to those skilled in the art.

It will be clear that the invention is not limited to the details described herein and that various changes and modifications may be made within the scope of the invention.

[Brief explanation of the drawing]

FIG. 1 is a functional block diagram of a multi-presettable speech alarm time keeping device according to the present invention, and FIG. 2 is a multi-presettable alarm clock/
A functional block diagram of the watch; FIG. 3 is a functional block diagram of the speech memory playback portion of the time keeping device; FIG. 4 is a circuit diagram of the application circuit of the speech memory playback portion of the time keeping device; FIG. 5 is a functional block diagram of the speech memory playback portion of the time keeping device; FIG. 6 is a flowchart showing how to program the alarm time and speed message in the above device. FIG. 6 is a flowchart showing the alarm operation order of the present invention. FIG, 2 FIG, 1 FIG, 3 1"-----"I I 81.1121 183.54 1 111〒--- O /A\ , +11-4--. FFFPI FIG, 5

Claims (1)

[Claims] 1. An oscillation circuit, a frequency divider, a display circuit that displays the current time, a presettable alarm circuit that can input multiple preset times, and a system that compares the preset time and the current time. presettable time keeping means having a comparator circuit for generating an alarm speech when a preset time has arrived; speech processing means for decoding a digital signal and converting it into an analog signal with a frequency response matching the speech signal; storage means for storing the digital signal generated by the speech processing means at a predetermined address; The storage means is a storage means capable of storing speech signals of variable length in divided arrangements corresponding to the number of the plurality of speech signals without partitioning the storage means, and a time-up signal of the preset time. Control means for outputting the digital signal stored in the storage means when triggered; peripheral control means for controlling the input of the speech signal and the output of the speech signal. alarm speech/time keeping device. 2. An alarm speech/time keeping device according to claim 1, characterized in that said presettable time method means is capable of presetting two or more times. 3. The alarm speech/time keeping device according to claim 1, wherein the output order of the speech signals is in chronological order but does not depend on the setting order of the preset alarm hours. 4. The alarm speech/time keeping device according to claim 1, wherein said speech processing means and said storage means randomly generate any speech signal stored in said storage means when said preset alarm time times up. A device characterized by being able to generate 5. An alarm speech/time keeping device according to claim 1, characterized in that said storage means has a plurality of sections capable of storing different speech messages or two or more groups of the same message. 6. The alarm speech/time keeping device of claim 1, wherein the speech input device converts an audio signal into an electrical signal. 7. Alarm speech/time keeping device according to claim 1, characterized in that external means are used to preset the alarm time, said external means consisting of a counter, an OR gate and two switches. 8. The alarm speech/time keeping device of claim 1, wherein said speech processing and storage means is controlled by an external operation to reproduce said analog signal as a message machine.