JPH02223100A - Data string generating circuit and memory test device using the same - Google Patents

Abstract

PURPOSE:To provide an address to a data string according to an address complement by generating a data string which takes a value larger than a median and a value smaller than the median alternately at each generation of a clock signal and changes to be converged to the median as much clock signal is being generated. CONSTITUTION:After a counter circuit 26 is reset by a reset signal RST given from a control circuit, the count is revised by one each with a clock signal CK given from the control circuit. An address complementing circuit 27 passes other bit data outputted from the counter circuit 26 as it is and the data is outputted when the least significant bit data outputted from the counter circuit is at a logic level, and inverts other bit data outputted from the counter circuit 26 and outputs it when the least significant bit data is at other logic level. Thus, the output data is converged to the median as the number of clock signals increases while taking a value larger than a median and a value smaller than the median alternately. Thus, the data string takes an address according to the address complement.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data string generation circuit that generates a data string that undergoes special changes, and a memory test device using the data string generation circuit.

[Prior Art] Conventionally, semiconductor memory, for example, RAM (Random
As a test method for mAccess) feeory), there is a method of changing the address to conbriment (Magazine [Electronic Materials J, January 1974 issue, pp58-
59).

Here, the address complement is the address A(1), A(2>,...A
(N) (however, A(X) is a larger address if X is larger) as A(1), A(N), A(2)
, A (N-1> ,...A (N/2-1), A(
N/2), or A
(N), A (1), A (N-1), A (2)
. . . A (N/2) and A (N/2-1) are alternately and complementarily input in this order.

Note that, hereinafter, the former will be referred to as an ascending address complement, and the latter will be referred to as a descending address complement.

Address complement dynamically changes the operation of the memory's address decoder in particular, since each bit of the memory's address decoder alternates between a logic "1" and a logic "0" each time an address is input. can be tested.

A memory test device to which conventional address complement is applied is shown in the block diagram of FIG. 2, and its test procedure is shown in the flow chart of FIG.

In FIG. 2, a test device main body 10 tests a memory 11. The test device main body 10 generates write data for the memory 11 and also generates an address for specifying a memory area of the memory 11. The write data is latched by the input data latch circuit 12 and provided to the memory 11. The address is latched by the address latch circuit 13 and given to the memory 11. Although not shown, the test device main body 10 also includes a memory 11.
A write/read control signal for instructing a write operation or a read operation is applied to. Further, the data read from the memory 11 is latched by an output data latch circuit 14 and provided to the test apparatus main body 10.

Note that the address and write data are provided from the test device main body 10 to the input data latch circuit 12 or the address latch circuit 13 via a common bus.

A basic write operation to the memory 11 involves outputting a write address in the first cycle and
The basic read operation for the memory 11 is as follows:
This is done by outputting a read address in the first cycle and causing it to be latched by the address latch circuit 13, and in the next cycle, data is read from the memory area of that address and latched by the output data latch circuit F414.

The test device main body 10 tests the memory 11 according to the test procedure shown in FIG. 3, which combines such basic write operations and read operations.

First, the test device main body 10 sets the parameter i to an initial value of 1.
After setting, address A(i) is output in the first cycle, data D is output in the next cycle, and address A(i) is output in the next cycle.
Write data D to the memory area of i) (step 10
0-102).

Next, in the first cycle, the complementary address IA(i) of address A(i) (an address in which the logic levels of all bits of address A(i) are inverted) is output, and in the next cycle, data D is output. Data D is written in the memory area at address TA(i) (steps 103 and 104).

Thereafter, the parameter i is incremented, and after confirming that the parameter i is not equal to the value N/2, which is half of the number N of addresses in the memory 11, the process returns to step 101 described above.
When the parameter l reaches the value N/2, the first loop process ends and the process proceeds to the second loop process (step 105
．． 106).

Therefore, this first loop process is a process of writing data D to all areas of the memory 11 by ascending address complement.

In the second loop process, the test device main body 10 first
After setting the parameter i to the initial value 1, output address A(i) in the first cycle, read data D from the memory area in the next cycle and test it, and invert data ID of the read data D. Write the data ID to the memory area that has just been output and read (step 1)
10-113).

Next, in the first cycle, the complementary address IA(i) of address A(i) is output, and in the next cycle, data D is sent out from that memory area for testing, and the inverted data ID of the read data D is output. Write the data ID to the memory area that has just been output and read (step 1)
14-116).

After that, the parameter i is incremented, and after confirming that the parameter i does not reach the value N/2, the process returns to step 111 described above, and the second loop processing ends when the parameter i reaches the value N/2. Then, the process proceeds to the third loop (steps 117 and 118).

Therefore, this second loop process is a process of reading the stored data D from each area of the memory 11 and testing it by ascending address complement, and writing the inverted data ID of the read data into the read area. It is.

The third loop process is similar to the second loop process, except that the data read from each area of the memory 11 is data ID, and the data written to each area is data D. different (steps 120-128)
.

[Test] - When the third loop process is completed, the apparatus main body 10 proceeds to the fourth loop process (steps 130 to 138). The fourth loop process differs from the first to third loop processes by performing address complements in descending order. The fourth processing loop, by descending address complement,
This is a process in which stored data D is read from each area of the memory 11, tested, and inverted data ID of the read data is written in the read memory area.

Upon completion of the fourth loop process, the test device main body 10 proceeds to the fifth loop process (steps 140 to 148). The fifth loop process is a process using descending address complement similar to the fourth loop process, but the data read from each area of the memory 11 is a data ID, and the data written to each area is This processing loop differs from the fourth processing loop in that it is data D.

When the test device main body 10 finishes the fifth loop processing,
A series of tests on the memory 11 are completed.

[Problems to be Solved by the Invention] In the conventional memory test device described above, the test device main body 10 must generate an address that changes according to the address complement every two cycles. Also, data must be generated in these intermediate cycles. It is desirable to achieve short cycles, as they determine the total test time.

It takes a long cycle to generate an address that changes according to the address complement and data to be output in an intermediate cycle thereof using software. Therefore, in the past, in order to shorten the cycle, all addresses and data to be generated were prepared and stored in the auxiliary storage device 10a, and read out sequentially from this auxiliary storage device 10a and outputted one after another. .

By the way, the total amount of addresses and data to be prepared and stored in the auxiliary storage device 10a is determined by the following formula: Total amount of addresses and data = (address input cycle + data read/write cycle) x number of memory addresses x number of loops =2XNX5=lON It can be determined from (1), and is a large amount corresponding to ION cycles.

In the future, there is a tendency for the capacity of RAM, and therefore the number N of memory addresses, to increase more and more.

In this case, since the total amount of addresses and data to be prepared 1ON is proportional to the number of memory addresses N, the total amount to be prepared becomes very large, and the auxiliary storage device (for example, disk memory capacity) 10a There may be times when you can't get into it. That is, it may become impossible to perform a memory test according to the address complement method. It is also possible to store the information by dividing it into a plurality of auxiliary storage devices, but in this case, the configuration of the memory test device becomes complicated.

Therefore, a memory test device has been proposed that simply increments and generates addresses for testing. Fourth
The figure is a block diagram showing the proposed memory test device, and the same parts as in FIG. 2 are denoted by the same reference numerals.

This memory test device is provided with a counter circuit 15 that generates an address by simply incrementing it, and in the test mode, a multiplexer circuit 16 selects the address from this counter circuit 15 to
I try to give it to Therefore, the test device main body 17
In this conventional device, the counter circuit 15 generates the address, so there is no need to store the address in the test device main body 17, and the address During one cycle, the input data latch circuit 12 can latch the same data and write data. Therefore, if the test device main body 17 stores only a small amount of written data, the temperature is good.

However, in this conventional device, since the address is a simple increment change, it is not possible to test the dynamic operation of the memory 11, especially the address decoder.

The present invention has been made in consideration of the above points, and provides a memory test device that can execute a test according to address complement and requires less data to be prepared in the test device itself. This is what I am trying to do. Another object of the present invention is to provide a data string generation circuit that can realize such a memory test device.

[Means for Solving the Problems] A first aspect of the present invention relates to a data string generation circuit applicable to a memory test device. This first invention alternately takes a value larger than the median value and a value smaller than the median value each time a clock signal is generated, and changes the value so that it converges to the median value as the number of clock signals generated increases. The purpose of this is to generate a data string. In order to generate such a data string, the first aspect of the present invention includes a counter circuit, and when the least significant bit data outputted from this counter circuit is at one logic level, the other bit data outputted from the counter circuit is A gate circuit that inverts and outputs other bit data output from the counter circuit when the least significant bit data is at the other logic level, and after giving a reset signal to the counter circuit. , and a control circuit that provides a clock signal of a predetermined period to the counter circuit.

A memory test device according to a second aspect of the present invention uses the data string generation circuit according to the first aspect of the present invention as an address generation circuit according to address complement, and allows the test device main body to detect a semiconductor memory specified by the generated address. It tests semiconductor memory by accessing areas.

[Operation] In the first invention, after the counter circuit is reset by a reset signal given from the control circuit,
The count value is updated one by one by a clock signal given from the control circuit.

When the least significant bit data output from the counter circuit is at one logic level, the gate circuit allows other bit data output from the counter circuit to pass through as is and outputs it, and the least significant bit data is at the other logic level. At this time, the other bit data output from the counter circuit is inverted and output.

As a result, the output data alternately takes a value larger than the median value and a value smaller than the median value each time a clock signal is generated, and changes so that it converges to the median value as the number of clock signals generated increases. It becomes a data column.

Therefore, the data string generated by the data string generation circuit of the first aspect of the present invention has an address according to the address complement when viewed from the memory test device.

Therefore, in the second aspect of the present invention, this data string generation circuit is used as an address generation circuit according to address complement. Therefore, the test device main body accesses the memory area specified by the address without generating an address. In other words, if the semiconductor memory is capable of both writing and reading, the test is performed by writing or reading data to the memory area specified by the address, and if the semiconductor memory is capable of reading only. If so, data is read from the memory area specified by the address and tested.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

The precepts of the body First, the overall configuration of the embodiment will be explained.

FIG. 1 is a block diagram showing the overall configuration of this embodiment. In FIG. 1, a test device main body 20 generates write data to a memory 21 to be tested, and tests data read from the memory 21. The write data is input to the input data latch circuit 22.
is latched and applied to the memory 21. Further, an address latch circuit 23 is provided for normal use of the memory 21. However, in this embodiment, the test device main body 20 does not generate an address, so the address latch circuit 23 has no meaning in the test mode. The data read from the memory 21 is latched by the output data latch circuit 24 and provided to the test device main body 20.

The address that specifies the memory area to be accessed in the memory 21 is generated by the address generation circuit 25 under the control of the test device main body 20. The address generation circuit 25 includes a counter circuit 26 and an address complement circuit 27. The counter circuit 26 is connected to the test device main body 20.
After receiving the reset signal r (ST), the address complement north circuit B27 generates data that is counted up according to the clock signal CK that arrives, and the address complement north circuit B27 outputs the data in the ascending/descending order given from the test equipment main body 20. Depending on the instruction signal U/D, the address is converted into an address according to an ascending address complement or an address according to a descending address complement and output.

The address latched by the address latch circuit 823 and the address generated by the address generation circuit 25 are given to the multiplexer circuit 28.

The multiplexer circuit 28 is given a selection instruction signal TBS from the test device main body 20, and the multiplexer circuit 28
8 is the address generation circuit 25 in the test mode.
The address where the error occurred is given to the memory 21.

Address 25- Next, the detailed configuration of the address generation circuit 25 will be explained.

Here, FIG. 5 is a block diagram showing the detailed configuration of the address generation circuit 25, and FIGS. 6 and 7 are charts showing input/output data, etc. of the address complementing circuit 27, respectively.

Note that for the sake of simplicity, it is assumed that the generated address is 3 bits.

In FIG. 5, the counter circuit 26 of this embodiment has four
It consists of a bit up counter, and is supplied with a reset signal R8T and a clock signal CK from the test apparatus main body 20 mentioned above. Therefore, after receiving the reset signal R8T, the counter circuit 26 counts up each time the clock signal CK arrives, and increments the 4-bit data D1 to D1 as shown in FIGS. 6 and 7. D
Outputs 4.

These 4-bit data D1 to D4 are applied to the address complement circuit 27. The address complement circuit 27 is supplied with an ascending order/descending order instruction signal U/D from the test apparatus main body 20.

Ascending order/descending order instruction signal U/D takes logic "1" when instructing ascending address complement, and takes logic "0" when instructing descending address complement.

The address complement circuit 27 includes the counter circuit 2
6, the least significant bit data Do and the ascending order/descending order instruction signal U/
An exclusive Noah 1111i'lO that obtains an exclusive Noah of D,
This exclusive NOR output S30 and each bit data D1 to D3. except the least significant bit data from the counter circuit 26. \
Three exclusive OR circuits 31 to take the exclusive OR of
It consists of 33. Output data A1-A3 from exclusive OR circuits 31-33 serve as addresses.

In the above configuration, when the ascending order/descending order instruction signal U/D indicates ascending order address complement (logic "1"), the exclusive NOR circuit 30 inverts the least significant bit data DO from the counter circuit 26. It operates as an inverter circuit and the least significant bit data string 1”010101
Exclusive NOR output string rlo1 consisting of an inverted data string of 01J
01010" is output.

Each exclusive OR circuit 31 to 33 has an exclusive NOR output S3
When the exclusive NOR output S30 is a logic "0", each bit data D1 to D3 arriving from the counter circuit 26 is passed through as is when the exclusive NOR output S30 is a logic "0".
Each bit data D1 to D3 arriving from the inverter is inverted and passed through. As mentioned above, the exclusive Noah output S
30 changes as rlolololo, each exclusive OR circuit 31 to 33 passes each bit data D1 to D3 as is in the first cycle, and inverts each bit data D1 to D3 in the next cycle. In subsequent cycles, passing and reversing are alternately repeated and output.

Thus, as shown in FIG.
When /D indicates ascending address complement, addresses A1 to A follow ascending address complement.
3 data strings are output from the address generation circuit 25.

On the other hand, when the ascending order/descending order instruction signal U/D indicates descending order address complement (logic "0"), the exclusive NOR circuit 30 acts as a circuit that passes the least significant bit data Do from the counter circuit 26 as is. working,
The data string “01010101” of the least significant bit data Do
" is output as is.

Therefore, each exclusive OR circuit 31 to 33 inputs each bit data D1 from the counter circuit 26 in the first cycle.
~D3 are inverted and output, and in the next cycle, each bit data D1 to D3 are passed through as they are, and in subsequent cycles, the inversion and passing are alternately repeated and output.

Thus, as shown in FIG.
When /D specifies descending address complement, A1 to A1 of the address following the descending address complement
83 data strings are output from the address generation circuit 25.

Kyojongtan Shangwang Cliff Next, a test procedure according to this embodiment will be explained.

FIG. 8 is a flowchart showing the test procedure according to this embodiment.

The test device main body 20 first receives the address complement north I! of the address generation circuit 25. 127. Ascending/descending instruction signal U/D instructing ascending address complement to
At the same time, write data D to the memory 21 is output.
is output and latched by the input data latch circuit 22 (
Steps 200 and 201) At this time, the address complementing circuit 27 is in a state where it can generate an address according to the ascending address complement.

Next, a reset signal R3T is output to the counter circuit 26 of the address generation circuit 25 to reset the counter circuit 26, and a selection instruction signal TBS is applied to the multiplexer circuit 28 to select an address from the address complement circuit 27 ( Step 202.2o3).

The processing up to this point is the initial processing in the first loop processing. Once this initial processing is completed,
The address according to the ascending address complement is given to the memory 21 via the multiplexer circuit 28, and the write data D latched in the input data latch circuit 22 is written into the corresponding memory area (step 204.2o5).
).

Thereafter, after confirming that data D has not been written to all memory areas of the memory 21, step 204 described above is performed.
Returning to step 206, the clock signal CK is applied to the counter circuit 26 to generate the next address according to the ascending address complement and provide it to the memory 21 (step 206).

By repeating the process of steps 204 to 206, memory 21 is stored according to the ascending address complement.
When the data D is written to all memory areas, the first loop process ends and the process proceeds to the second loop process.

In this second loop process, the initial process of giving an address according to ascending address complement to the memory 21 and latching the write data is almost the same as the first loop process (steps 210 to 213).
. However, it differs from the initial processing in the first loop processing in that the inverted data ID of the write data D in the first loop processing is latched as write data in the input data latch circuit 22; An address according to ascending address complement is given to the memory 21 via the circuit 28, and the stored data D is first read out and latched into the output data latch circuit 24 for testing. Write the write data ID latched in the latch circuit 22 to the corresponding memory area (steps 214 to 21
6).

Thereafter, after confirming that the processing for all memory areas of the memory 21 has not been completed, step 21 described above is performed.
Returning to step 4, the clock signal CK is applied to the counter circuit 26 to generate the next address according to the ascending address complement and provide it to the memory 21 (step 217).

By repeating the process of steps 214 to 217, the memory 21 is stored in accordance with the ascending address complement.
The test is performed by reading out the stored data D from all memory areas of The process ends and the process proceeds to the third loop process.

In this third loop process, the initial process of giving an address according to ascending address complement to the memory 21 and latching the write data to the input data latch circuit 22 is the same as the first loop process (steps 220 to 223). ).

When such initial processing is completed, an address according to ascending address complement is given to the memory 21 via the multiplexer circuit 28, and the stored data ID is first read out and latched into the output data latch circuit 24 and taken in. A test is performed, and then the write data D latched in the input data latch circuit 22 is written into the memory area from which it has just been read (step 22
4-226).

Thereafter, after confirming that the processing for all memory areas of the memory 21 has not been completed, step 22 described above is carried out.
Returning to step 4, the clock signal CK is applied to the counter circuit 26 to generate the next address according to the ascending address complement and provide it to the memory 21 (step 227).

By repeating the process of steps 224 to 227, the memory 21 is stored according to the ascending address complement.
Read the stored data ID from all memory areas, perform a test, write data D to the memory area,
When reading of data ID and writing of data D to all memory areas is completed, this third loop process is completed and the process proceeds to fourth loop process.

In this fourth loop process, the test device main body 20 first outputs an ascending/descending instruction signal U/D that instructs the address complementing circuit 27 of the address generation circuit 25 to perform descending address complement, and
The write data ID for 1 is output and latched by the input data latch circuit 22 (steps 230 and 231).
. At this time, the address complementing circuit 27 is in a state where it can generate an address according to the descending address complement.

Next, a reset signal R8T is output to the counter circuit 26 of the address generation circuit 25 to reset the counter circuit 26, and a selection instruction signal TBS is applied to the multiplexer circuit 28 to select an address from the address complement north circuit i27 ( Steps 232.233).

The processing up to this point is the initial processing in the fourth loop processing. Once this initial processing is completed,
An address according to the descending address complement is given to the memory 21 via the multiplexer circuit 28, and the stored data D is first read out and latched into the output data latch circuit 24 for testing. Write the write data ID latched in the data latch circuit 22 to the memory area that has just been read (
Steps 234-236).

Thereafter, after confirming that the processing for all memory areas of the memory 21 has not been completed, step 23 described above is performed.
Returning to step 4, the clock signal CK is applied to the counter circuit Fr426 to generate the next address according to the descending address complement and provide it to the memory 21 (step 237).

By repeating the process of steps 234 to 237, the memory 21 is stored in accordance with the descending address complement.
Read the stored data D from all memory areas, perform a test, write the data ID to the memory area,
When the reading of data D and the writing of data ID to all memory areas are completed, this fourth loop process is completed and the process proceeds to the fifth loop process.

In this fifth loop process, the initial process of giving an address according to the descending address complement to the memory 21 and latching the write data to the input data latch circuit 22 is almost the same as the fourth loop process (steps 240 to 24). 243). However, the fourth loop process is different from the initial process in that the input data latch circuit 22 latches the inverted data ID of the write data D in the fourth loop process.

When the above initial processing is completed, an address according to the descending address complement is given to the memory 21 via the multiplexer circuit 28, and the stored data ID is first read out and latched into the output data latch circuit 24. Then, the write data D latched in the input data latch circuit 22 is written into the memory area from which it has just been read (steps 244 to 244).
246).

Thereafter, after confirming that the processing for all memory areas of the memory 21 has not been completed, step 24 described above is performed.
Returning to step 4, the clock signal CK is applied to the counter circuit 26 to generate the next address in accordance with the descending address complement and provide it to the memory 21 (step 247).

By repeating the process of steps 244 to 247, the memory 21 is stored in accordance with the descending address complement.
Read the stored data ID from all memory areas, perform a test, write data D to the memory area,
When reading of data ID and writing of data D to all memory areas is completed, this fifth loop process is completed and the series of tests is completed.

Therefore, according to the above embodiment, the address generation circuit 25
can generate data strings that follow ascending address complements or special data strings that follow descending address complements. Since such an address generation circuit 25 is used, the test device main body 20 only needs to store a small amount of data such as write data in each loop process, and the storage configuration of the test device main body 20 can be simplified. can be taken as a thing. Moreover, it is possible to execute a test according to address complement, and it is possible to execute a dynamic memory test.

In this way, since the amount of data stored in the test device main body 20 is small, it becomes possible to apply the test using address complement to the test of memory, which will become increasingly integrated and have a large capacity in the future.

(1) In the above embodiment, the semiconductor memory to be tested is a RAM, but a ROM (Read
only +emory). That is, the present invention can be widely applied to semiconductor memories where it is meaningful to apply address complement to test the dynamic characteristics of the memory, for example, the dynamic characteristics of the address decoder. . Of course, the number of bits of a memory address and the number of bits of data are not limited to predetermined values.

(2) In the above embodiment, the memory is tested using five loop processes, but the test may be performed using more loop processes, or the memory may be tested using fewer loop processes. Furthermore, the order of the loop processing is not limited to that of the above-described embodiment. In short, any test using address complement is sufficient.

(3) Part of the configuration for executing the test may be configured on a memory chip that accommodates the memory to be tested. For example, the address generation circuit 25 of the embodiment may be mounted on the same memory chip as the memory 21.

(4) The address generation circuit 25 shown in FIG. 5 generates addresses in relation to memory test equipment, but it is also significant as a data string generation circuit that generates data strings that undergo special changes. For example, it can be used as a test data generation circuit when testing a logic circuit that forms output data according to the input data from input data of multiple pins, and can also be used as an input for simulation of various devices. It can also be used as a data generation circuit.

(5) In the above embodiment, the address generation circuit 25
Although the counter circuit 26 shown in FIG. 1 has an up-counter configuration, it can be configured in the same manner even if it has a down-counter configuration.

[Effects of the Invention] As described above, according to the first aspect of the invention, a value larger than the median value and a value smaller than the median value are alternately taken every cycle, and moreover, as the cycle progresses, the value converges to the median value. Therefore, it is possible to obtain a data string generation circuit that can generate a special data string that gradually changes.

Further, according to the second aspect of the invention, the data string generation circuit according to the first aspect of the invention is applied as an address generation circuit according to address complement of a memory test device. There is no need to store test addresses and data, and the configuration of the memory test device can be simplified, and even large-capacity semiconductor memories can be tested according to address complement.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a memory test device according to the second invention, FIG. 2 is a block diagram showing a first example of a conventional memory test device, and FIG. 3 is a test procedure for the device shown in FIG. FIG. 4 is a block diagram showing a second example of a conventional memory test device, and FIG. 5 is a flowchart showing a second example of a conventional memory test device. FIG. ), FIGS. 6 and 7 are diagrams showing the data contents of each part of the circuit shown in FIG. 5, and FIG. 8 is a flowchart showing a test procedure for the device shown in FIG. 1. 20...Test device main body, 21...Memory, 25.
...Address generation circuit, 26...Counter circuit, 27
. . . address complement circuit, 30 . . . exclusive NOR circuit, 31 to 33 . . . exclusive OR circuit. Figure 30: Exclusive NOR circuits 31-33. Exclusive OR circuit 271 Dress con 7 degree remention circuit 7 7'' [+1 diagram showing the truth value of Figure 5 (1) Figure 5 showing the truth value of Figure 5 ( 1) Diagram Diagram

Claims (2)

[Claims] (1) Counter circuit When the least significant bit data output from this counter circuit is at one logic level, the other bit data output from the counter circuit is passed through and output as is, and the least significant bit data When is at the other logical level,
a gate circuit that inverts and outputs other bit data output from the counter circuit; and a control circuit that applies a clock signal of a predetermined period to the counter circuit after applying a reset signal to the counter circuit; A data string generator that generates a data string that alternately takes a value larger than a value and a value smaller than a median value every time a clock signal is generated, and converges to the median value as the number of clock signals increases. circuit. (2) The data string generation circuit according to claim 1 is used as an address generation circuit according to address complement, and the test device main body accesses the area of the semiconductor memory specified by the generated address to A memory test device characterized by testing memory.