JPH022240B2 - - Google Patents

Abstract

PURPOSE:To increase the reliability, by obtaining a binary output without flowing a current at all times to a nonvolatile storage element even in case a normal circuit is faulty, by providing the nonvolatile storage element, a switching element and a contol means which controls the switching element. CONSTITUTION:The gate of an MOSFETQE1 is turned on by the program signal P level 1, and a large current flows to a fuse element F. Thus the element F is fused. If a power supply VD is applied under such conditions, the output of an inverter I1 is set at level 1. Then an MOSFETQE2 is turned on, and the signal of an output terminal Out is set at level 0. On the other hand, when the element F is not fused, the output of the I1 is set at level 0 and the MOSFETQE2 is cut off with the application of the VD. In this case, a current is not supplied at all times to the element F to avoid the misfusing. Thus the reliability is increased for a semiconductor integrated circuit.

Description

[Detailed Description of the Invention] Technical Field of the Invention The present invention relates to a semiconductor integrated circuit having a redundancy function capable of switching to a backup circuit when the regular circuit is defective. The present invention relates to a semiconductor integrated circuit that generates a signal used as a switching control signal.

Technical Background of the Invention Recently, in semiconductor integrated circuits, especially semiconductor memories, regular memory cell circuits and spare memory cell circuits are formed in advance, and if a defective bit is found in the regular memory cell circuit during manufacturing, In recent years, an increasing number of devices have a redundancy function that allows the defective bit portion to be replaced with a spare memory cell circuit. This is because even if a normal memory cell circuit has just one defective cell, the memory as a whole is defective, so such memories are discarded as defective products.

However, as memory capacity increases, the probability of defective memory cells is increasing, and if defective memory is thrown away, the cost of the product becomes extremely high. Put it away. Therefore, in order to improve the overall yield, a method has been adopted in which a spare memory cell circuit is formed and used by switching when a part of the regular memory cell circuit is defective. Information for switching is written in a nonvolatile memory element.

FIG. 1 is a block diagram of a semiconductor memory in which the above-mentioned spare memory cell circuit is formed. In FIG. 1, 1 is an address buffer to which an address signal is applied, and this address buffer 1
The output from the address decoder 2 is given to a regular address decoder 2 and a spare address decoder 3 in parallel.
The decoded output of the regular address decoder 2 is given to the regular memory cell circuit 4, one or more memory cells in the regular memory cell circuit 4 are selected by this decoded output, and then,
Data is stored in or read from the selected memory cell. Further, the decoding operation of the regular address decoder 2 is controlled by the output from the spare address decoder 3. The decode output of the spare address decoder 3 is given to the spare memory cell circuit 5, a memory cell in the spare memory cell circuit 5 is selected by this decode output, and data is then transferred to the selected memory cell. is stored and data is read. Further, the output of the spare address decoder 3 is also output as a signal for controlling the decoding operation of the regular address decoder 2. Furthermore, the decoding operation of the spare address decoder 3 is performed when there is a defective bit in the regular memory cell circuit 4 and when this defective part is replaced with a memory cell in the spare memory cell circuit 5. It is controlled by an exchange control signal output from an exchange control signal generator 6 in which information for the exchange is written in advance in a nonvolatile memory element. That is, in a semiconductor memory having such a configuration, if there is no defective bit in the regular memory cell circuit 4, the exchange control signal is not output, and only the regular address decoder 2 operates to replace the memory in the regular memory cell circuit 4. A cell is accessed. On the other hand, if there is a defective bit in the regular memory circuit 4, the spare address decoder 3 is programmed in advance to obtain a decode output corresponding to the row or column address containing the defective bit, and the exchange control signal is The non-volatile memory element is programmed so that a 1 level or 0 level exchange control signal can be obtained from the generator 6. Therefore, if the address buffer 1 now obtains an output corresponding to the row or column address containing a defective bit in the normal memory cell circuit 4, the spare address decoder 3 will output the output in the spare memory cell circuit 5. A memory cell is selected. Furthermore, the decoding output of the spare address decoder 3 at this time stops the decoding operation of the regular address decoder 3, and the regular memory cell circuit 4 is not accessed. Through such operations, the defective portion in the regular memory cell circuit 4 is replaced with the spare memory cell circuit 5.

FIGS. 2a and 2b are circuit diagrams showing the conventional configuration of the exchange control signal generating section 6. FIG. In the circuit shown in Figure 2a, a fuse element F made of polysilicon, which is one of the nonvolatile memory elements, is inserted between the power supply VD application point and the output terminal Out, and the output terminal
Insert MOSFET Q _E in enhancement mode for programming between Out and the ground point, and MOSFET Q _D in depletion mode between the output terminal Out and the ground point, and the gate of MOSFET Q _E for programming. In addition to applying signal P, the gate of MOSFET Q _D is connected to the ground point. The circuit shown in Figure 2b also has an enhancement mode connection between the power supply VD application point and the output terminal Out.
Insert MOSFETQ _E and similarly set the depresion mode between the power supply VD application point and the output terminal Out.
Insert MOSFETQ _D , and insert fuse element _F between the output terminal and the ground point, and then
The program signal P is given to the gate of MOSFETQ D, and the gate of MOSFETQ _D is connected to the output terminal Out.
It was designed to connect to.

In the circuit of Figure 2a, when fuse element F is not blown, the level of output terminal Out is
It is maintained at one level by the resistance ratio between MOSFETQ _D and fuse element F. On the other hand, MOSFETQ _E
When a 1-level program signal P is applied to the gate of MOSFET Q E, this MOSFET Q _E is turned on and the fuse element F
When a large current flows through the fuse element F and fuse element F is blown out by the Joule heat generated at this time, the signal P becomes 0 level again and MOSFETQ _E is cut off, and this time the output terminal is passed through MOSFETQ _D.
Out is discharged to 0 level. When the level of the signal at the output terminal Out, that is, the exchange control signal, is, for example, 1 level, the decoding operation of the spare address decoder 3 is stopped, and when it is, for example, 0 level, the decoding operation is performed.

In the circuit of Fig. 2b, contrary to the circuit of Fig. 2a, when fuse element F is not blown, the level of the output terminal Out becomes 0 level due to the resistance ratio of MOSFET Q _D and fuse element F. It is maintained. Then, when a 1-level program signal P is applied to the gate of MOSFETQ _E , the fuse element F is blown out in the same way as described above, and then the output terminal Out is
Charged to level 1 via MOSFETQ _D. In this case, when the level of the signal at the output terminal Out, that is, the exchange control signal, is, for example, 0 level, the decoding operation of the spare address decoder 3 is stopped, and when it is, for example, 1 level, the decoding operation is performed.

FIG. 3 is a circuit diagram showing an example of the configuration of one decoding circuit of the spare address decoder 3. This circuit uses a depletion mode MOSFETQ _LD for the load and each address signal A ₀ , ₀ , A ₁ , ₁ output from the address buffer 1.
It is composed of a plurality of enhancement mode MOSFETQ _DRs for driving with n as a gate input, and a plurality of fuse elements FB inserted between each of the plurality of MOSFETQ _DRs and the MOSFETQ _LD .

In such a decoding circuit, for example, if one of the memory cells of the normal memory cell circuit 4 corresponding to the address A ₀ =A ₁ =...=An=0 is defective, the decoding circuit corresponding to this address is Each fuse element F _B is programmed so that an output is obtained, that is, a fuse element connected to a MOSFET Q _DR with gate inputs of ₀ , ₁ , and n.
F _B is fused.

Problems with the Background Art By the way, in the conventional exchange control signal generator shown in FIGS. 2a and 2b, when the fuse element F is not blown, current always flows through the fuse element F. It's summery. On the other hand, the width of the pattern of the fuse element F is made extremely narrow so that it can be easily blown out. For this reason, it is not preferable in terms of reliability to constantly flow current through the fuse element F. For example, if noise is added to the power supply VD for some reason, or if the power supply voltage is increased by mistake,
There is a risk that an abnormal current will flow through the fuse element F and it may be accidentally blown out.

Purpose of the invention Therefore, the purpose of this invention is to:
An object of the present invention is to provide a highly reliable semiconductor integrated circuit that can obtain a binary output using a nonvolatile memory element.

Summary of the Invention The semiconductor integrated circuit of the present invention includes a nonvolatile memory element such as a fuse element whose impedance between both ends changes in a nonvolatile manner between a power supply and an output terminal, and a MOSFET between the output terminal and ground. By inserting a switching element made of Even when the impedance between both ends of the nonvolatile memory element is low, reliability is improved by obtaining a binary output without the need for constant current flow through the nonvolatile memory element. It is.

Embodiments of the Invention Hereinafter, embodiments of the invention will be described with reference to the drawings. FIG. 4 is a circuit diagram showing the configuration of an embodiment of the present invention. This circuit inserts a fuse element F made of polysilicon between the power supply VD application point (one potential supply end) and the output terminal Out, and connects the output terminal Out and ground (the other potential supply end). Enhancement mode for programs in between
Insert MOSFETQ _E1 and connect another enhancement mode between output terminal Out and ground.
Insert MOSFETQ _E2 , connect the input terminal of inverter I ₁ for detecting the signal of this terminal to the above output terminal Out, and connect the output of this inverter I ₁ to the above output terminal Out.
given to the gate of MOSFETQ _E2 and further above
A program signal P is applied to the gate of MOSFETQ _E1 . And output terminal Out
The signal is applied to the spare address decoder 3 in the circuit shown in FIG. 1, for example.

In a circuit having such a configuration, when fuse element F is blown out, a 1-level program signal P is applied to the gate of MOSFET Q _E1 . Then, this MOSFET Q _E1 is turned on and a large current flows through the fuse element F, and the fuse element F is blown out by the Joule heat generated at this time. After programming, if the power supply VD is turned on with fuse element F blown, the output terminal Out will be VD
Since it is not charged by the inverter I ₁
The output of will be level 1. Therefore,
MOSFETQ _E2 is turned on and the signal at the output terminal Out is set to 0 level.

On the other hand, when the power supply VD is turned on when the fuse element F is not blown, the output terminal Out becomes 1.
The output of inverter _I1 becomes 0 level, and MOSFET Q _E2 is cut off. In this case, the signal at the output terminal Out is set to 1 level. Also, at this time, MOSFETs Q _E1 and Q _E2 are both cut off, so current does not constantly flow through the fuse element F as in the conventional case, so it will not be accidentally blown out, increasing reliability. Can be done. In addition, the resistance of fuse element F and
The resistance ratio between MOSFETQ _E2 and the on-resistance is desirably set so that the signal at the output terminal Out is at 1 level.

FIG. 5 is a circuit diagram showing the configuration of another embodiment of the invention. In this circuit, the means for detecting the signal at the output terminal Out is from three inverters I ₂ to I ₄ connected in series and a capacitor C inserted between the inverters I ₃ and I ₄ and the ground. This circuit uses the following circuit.

This circuit uses the signal delay time caused by inverter _I3 and capacitor C to ensure that MOSFET Q _E2 is turned on and off in accordance with the state of fuse element F.

Note that the present invention is not limited to the above embodiments; for example, the fuse element F is
Although the case where the MOSFETQ _E1 is used for fusing has been described, the fusing may be performed by irradiating energy beams such as laser beams. In this case, MOSFETQ _E1 is not necessary. Furthermore, instead of fuse element F, MNOS,
A non-volatile memory element such as FAMOS may be used,
In short, it can be used in place of the fuse element F as long as the impedance between both ends changes in a non-volatile manner. Furthermore, when using a fuse element made of polysilicon, the initial state is set to a high resistance state to be in the same state as when it was blown, and then laser annealed to lower the resistance to the same state as when it was not blown out. You may also do so.

Furthermore, although the case where one inverter is provided in FIG. 4 has been described, it is sufficient if the number is an odd number.

Effects of the Invention As described above, according to the present invention, it is possible to provide a highly reliable semiconductor integrated circuit that can obtain a binary output using a nonvolatile memory element.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram of a semiconductor memory in which a spare memory cell circuit is formed, FIGS. 2a and 2b are circuit diagrams showing the conventional configuration of some circuits of the semiconductor memory, and FIG. 3 is a block diagram of the semiconductor memory in which a spare memory cell circuit is formed. FIG. 4 is a circuit diagram showing the structure of one embodiment of the present invention, and FIG. 5 is a circuit diagram showing the structure of another embodiment of the present invention. 1... Address buffer, 2... Regular address decoder, 3... Spare address decoder, 4
... Regular memory cell circuit, 5 ... Spare memory cell circuit, 6 ... Exchange control signal generator, Q _E ,
Q _DR , Q _E1 , Q _E2 ...Enhancement mode
MOSFET, Q _D , Q _LD ...depression mode MOSFET, F, F _B ... fuse element, I ₁ ...
I ₄ ...Inverter, C...Capacitor.

Claims (1)

[Scope of Claims] 1. A nonvolatile memory element inserted between one potential supply end and an output end and whose impedance between both ends changes in a nonvolatile manner, and a nonvolatile memory element inserted between the output end and the other potential supply end. a switching element, an inverter means for detecting a signal at the output terminal and controlling the switching element according to the detection signal, and a switching element provided between the input signal or output signal of the inverter means and the other potential supply terminal. 1. A semiconductor integrated circuit characterized by having a capacitance of 2. The semiconductor integrated circuit according to claim 1, wherein the nonvolatile memory element is a fuse element made of polysilicon. 3. The semiconductor integrated circuit according to claim 1, wherein the inverter means includes an odd number of inverters. 4. The semiconductor integrated circuit is formed in a semiconductor memory having a regular memory circuit and a spare memory circuit, and is used when a defective memory occurs in the regular memory circuit and the defective memory is replaced with a memory in the spare memory circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the signal at the output terminal is used as an exchange control signal.