JPH02224103A - Information processor - Google Patents

Abstract

PURPOSE:To select either one of operation clock in a central processor unit(CPU) without using a mechanical switch by storing the information of the selected operation clock in a memory and automatically selecting the operation clock at the time of executing power supply ON reset or manual reset. CONSTITUTION:Clock information relating to a specified operation clock among operation clocks in the CPU 2 including two or more operation clocks is stored in a rewritable memory 3. The operation clock is selected based upon the clock information read out from the memory during a reset period following power supply ON reset or manual reset. Thus, the operation clock can be selected without using a mechanical switch.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention stores information on the operating clock of a central processing unit in a memory so that the operating clock is automatically selected upon power-on reset or manual reset. It relates to a processing device.

[Prior Art] FIG. 4 shows the connection relationship between the central processing unit 2 and the memory 3 in the basic configuration of a widely used information processing device 1. Hereinafter, based on this diagram, The selection mechanism for the operating clocks selected in connection with power-on reset and manual reset will be briefly explained.

The operating clock of the central processing unit 2 is 16 of the reference oscillator 4.
The MHz oscillation output is obtained by successively dividing the frequency using two cascade-connected 2-2 frequency dividers 5°6, and one of the 2-divided output and the 4-divided output obtained here is Selector circuit 7
and is sent to each clock input terminal of the central processing unit 2 and the read/write control section 8.

By the way, the selector circuit 7 is configured to select an operating clock according to the clock selection signal latched by the latch circuit 9, and the data input terminal of the latch circuit 9 is connected to an open/close switch S whose one end is grounded and a resistor connected to the power supply Vcc. R
Connect to the connection point. Further, the clock input terminal of the latch circuit 9 is connected to the reset output terminal of the reset control unit 1O which receives the power-on reset signal and the manual reset signal, and the reset control circuit 1O receives the power-on reset signal or the manual reset signal. When the reset signal generated by delaying the trailing edge for a certain period of time is supplied to the clock input terminal of the latch circuit 9, the clock selection signal corresponding to high/low of the data input terminal is latched, and the selector circuit 7 sent to.

[Problems to be Solved by the Invention] The conventional information processing device I described above is configured to select two types of clock signals, 8 MHz or 4 MHz, depending on the open/close state of the open/close switch S. It is necessary for the user to manage the clock information corresponding to each open and closed state according to the program used by the user.

This is because the operating clock information is not displayed on the screen of a display device, etc., so the open/closed state of the open/close switch S is the only clue to knowing the clock frequency, and it is easy to forget the correspondence between the open/close switch S and the clock frequency. If this occurs, the proper operation of the program may be at risk.Furthermore, as manufacturing technology advances and clock frequencies increase, 3. It is anticipated that there will be situations in which multiple clock frequencies are required, and selecting the operating clock by operating a mechanical switch in such a situation would easily lead to further confusion.

[Means for Solving the Problems] The present invention solves the above problems, and provides a central processing unit with two or more types of operating clocks, and a designated clock in addition to the operating program and processing data of this central processing unit. a rewritable memory for storing clock information regarding the operating clock that has been read out; clock information reading means for reading clock information from said memory during a reset period following a power-on reset or manual reset; The present invention is characterized by comprising a latch means for latching clock information, and a selection means for selecting an operating clock corresponding to the clock information latched by the latch means and supplying the selected operating clock to the central processing unit.

[Operation] This invention stores clock information regarding a designated operating clock among the operating clocks of a central processing unit in which there are two or more types of operating clocks in a rewritable memory, and performs a power-on reset or manual reset. To enable selection of an operating clock without using a mechanical switch by selecting an operating clock based on clock information read from a memory during a reset period.

[Example] Hereinafter, an example of the present invention will be described with reference to FIGS. 1 to 3. FIG. 1 is a circuit configuration diagram showing an embodiment of the information processing device of the present invention, FIG. 2 is a signal waveform diagram of each part of the circuit shown in FIG. 1, and FIG. 3 is a diagram showing the operation clock switching procedure. FIG.

In FIG. 1, the information processing device II is configured such that clock information (in this case, frequency data) regarding the operating clock can be written into the memory 3 that stores the operating program or processing data of the central processing unit 2. The memory function of the conventional open/close switch S is taken over by the memory 3, and the operating clock switching function is assigned to a keyboard device (not shown), which is a peripheral device, and the operating clock display function is assigned to a display device (not shown). It was designed so that In the embodiment, some circuit components are common to the conventional information processing device 1, but in order to store clock information in the memory 3, an address bus, a data bus, and a control bus connecting the central processing unit 2 and the memory 3 are provided. Each requires an address control section 12, a bidirectional buffer 13, and a read/write control section 8. That is, when fixed address data is given to the address control unit 12 and a storage address of clock information is specified, the clock information in the memory 3 is read out using a read signal from the read/write control unit 8, and the read clock information is read out from both sides. This is so that it can be sent to a latch means, which will be described later, on the front side of the buffer.

More specifically, at the time of power-on reset or manual reset, the reset signal outputted by the reset control unit 1O with a delay of time T is inverted by the inverter 4, and is sent to the address control unit 12, the bidirectional buffer 13, and Clock information is latched by simultaneously supplying it to the read/write control section 8, and in the case of the embodiment, the clock information is supplied to the reset control section IO, the inverter 14, and the address control section 12. Bidirectional buffer 13. The read/write control unit 8 and the like constitute clock information reading means.

On the other hand, the latch means for latching clock information includes, in addition to the latch circuit 9, a latch circuit 15 for generating a latch clock and two Nant gate circuits 16 and 17. The latch timing at which the latch circuit 9 latches the clock information in the memory 3 needs to be limited to an appropriate time during the reset period, and therefore it is necessary to devise a way to provide the latch clock. That is, in the embodiment, the reset signal inverted by the inverter 14 and the power-on reset signal are ANDed by the Nant gate circuit I6 to form the reset period instruction signal shown in FIG. 2(E). Furthermore, this reset period instruction signal is used as a data input to the first stage of a two-stage latch type latch circuit 15 which uses the output of the frequency divider 6 as a clock. latch circuit 15 first stage I
The Q small output is used as the second stage data input, and the first stage I
Q low output Q output of the second stage is a Nantes gate circuit! By negating the logical product at step 7, the Labchi clock shown in FIG. 2(H) is obtained.

Therefore, as shown in FIG. 2 (1), during the reset period T from the trailing edge of the power-on reset signal to the trailing edge of the reset signal, address data specifying the storage address of the clock information is sent from the address control section 12. is supplied to the memory 3, and the clock information read from the memory 3 is latched into the latch circuit 9 at the same time as the latch clock rises.

In other words, even if there is no open/close switch S that was required in the past,
The selection of the operating clock by the selector circuit 7 is completed until the central processing unit 2 is released from reset.

By the way, if you want to know the operating clock or switch the operating clock, it is best to follow the procedure shown in FIG. 3. First, in step (101), clock information is read from the memory 3, and in the following step (102), the clock frequency is determined. And step (
103) or step (104), the clock frequency displayed on the screen is checked, and if there is no need to change the frequency, the end key is operated in step (106) following step (105). If there is a need to change the frequency, in step (107), the user manually instructs the change. As a result, in step (10B), clock information regarding the newly selected operating clock is written into the memory 3.

However, in this case, simply writing the clock information in the memory 3 does not change the clock frequency, and as shown in the following step (109), a new operating clock can be selected by performing a manual reset operation. Complete.

During a manual reset, as well as during a power-on reset, the clock information set according to the above procedure is read out from the memory 3 during the reset period specified by the reset control unit IO, and the latch circuit 9 is read out at the rising edge of the latch clock. is latched to.

In this way, the information processing device II replaces the storage function of the conventional mechanical switch S with the memory 3, and also performs the operation clock switching function and the operation clock display function as an input/output device of the central processing unit 2. It can be assigned to the keyboard device or display device, and not only can the operating clock be automatically selected at power-on reset or manual reset, but also the clock information stored in memory 3 can be freely rewritten and then manually reset. It is possible to change the operating clock and check clock information at any time using the screen, which is particularly suitable when using a central processing unit 2 that supports multiple clocks.

[Effects of the Invention] As explained above, the present invention stores clock information regarding a designated operating clock among the operating clocks of a central processing unit in which there are two or more types of operating clocks in a rewritable memory; Since the operating clock is automatically selected based on the clock information read from the memory during the reset period following a power-on reset or manual reset, the memory function of a conventional mechanical switch is taken over by the memory, and the operating clock is The clock switching function and operating clock display function can be assigned to the central processing unit's human input and output devices such as the keyboard and display device. You can freely rewrite the clock information stored in the , then manually reset it to change the operating clock, and even check the clock information on the screen at any time. It has excellent effects such as being particularly suitable when used.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing an embodiment of the information processing device of the present invention, FIG. 2 is a signal waveform diagram of each part of the circuit shown in FIG. 1, and FIG. 3 is a diagram showing the operation clock switching procedure. The flowchart shown in FIG. 4 is a circuit configuration diagram showing an example of a conventional information processing device. 211. central processing unit, 3. , , memory, 7° selector circuit, 8. ,, Read/Write control section. 930. latch circuit, 10. ,,Reset control section. 11. Information processing device, 12. ,,address control section,
13. , , bidirectional buffer, 14. ,,inverter,1
5. ,, latch circuit, 16.17° nand gate circuit.

Claims (1)

[Claims] In addition to the central processing unit that has two or more types of operating clocks, and the operating programs and processing data of this central processing unit,
a rewritable memory that stores clock information regarding a specified operating clock; a clock information reading means that reads clock information from the memory during a reset period following a power-on reset or a manual reset; An information processing device comprising: latch means for latching clock information latched; and selection means for selecting an operating clock corresponding to the clock information latched by the latch means and supplying the selected operating clock to the central processing unit.