JPH0222410B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a data transfer circuit used for transferring data from a processor to an external device.

[Prior art]

When transferring data from the processor to the outside,
Depending on the conditions of the equipment connected to the outside, the speed at which data is sent from the processor and the speed at which data is sent to the outside may be different. In this case, data is sent out according to the memorized order.
Using a FIFO (First In First Out.) type sequential input/output memory, data from the processor is temporarily stored in this memory, and then the contents of the memory are read out at a read speed that matches the conditions of the external device and sent to the outside. It has become something to be sent out.

However, in the past, in order to control the storage status of sequential input/output memory, sequence control was performed based on pulses generated by a monostable multivibrator, and a processor also participated in sequence control. must be processed, the operating load increases, and
The time constant of the monostable multivibrator fluctuates due to aging of the resistor and capacitor, resulting in drawbacks such as unstable control conditions.

[Summary of the invention]

The present invention has the purpose of fundamentally eliminating such drawbacks of the conventional technology, and includes the above-mentioned sequential input/output memory, an output circuit for transmitting future data to the outside, and a write command signal from a processor. An extremely effective method is provided with an input control circuit that sends a write start signal to the sequential input/output memory in synchronization with a clock pulse in response to a match between the condition and the condition in which a ready signal from the sequential memory is given. It provides a data transfer circuit.

〔Example〕

Hereinafter, details of the present invention will be explained with reference to figures showing examples.

Figure 1 is a block diagram of the entire configuration. Parallel data from the processor CPU is sequentially applied to the input/output memory (hereinafter referred to as memory) FIFO, where it is temporarily stored and then processed in the same order as when it was stored. The signals are read out in parallel and given to the output circuit OC of the digital-to-analog converter, communication interface, etc.
After the parallel data is converted into serial data by the same circuit OC, it is sent to the outside as output data _D0 .

However, storing data in memory FIFO is
This is done in response to a write command signal from the processor CPU, but the memory FIFO receives a ready signal IR.
It is impossible to write to the memory FIFO until the signal (a signal that occurs in the memory FIFO and becomes high level and is output when there is free space in this memory and it is possible to capture output data) is sent. An input control circuit ICT is provided and operates to send out a write start signal SI in response to a match between a given condition of the write command signal and a given condition of the ready signal IR, This ensures consistency between the write command signal and the state of the memory FIFO.

Figure 2 is a block diagram of the input control circuit ICT. When the initial reset signal is given as "L" (low level), it is sent to the reset terminal R of the D-type flip-flop circuit (hereinafter referred to as FFC) _FF1 . Directly to the reset terminal R of FFC/FF ₂ .
It is applied via OR gate _G1 , FFC and _FF2 are reset, and their output terminals Q become "L".

Next, a write command signal is sent from the processor CPU.
If WT is given as an "L" pulse, this is applied to the set terminal S of FFC/FF ₁ , so
FFC・FF ₁ is set and output terminal Q is set to “H”
(high level) and gives this to AND gate _G2 , and the write command signal also goes to AND gate
When this returns to " _H ", the AND gate _G2 turns on, allowing the clock pulse CLK synchronized with the clock pulse for the processor CPU to pass through, and transmitting it to the clock terminal CK of FFC/FF _2. Send.

Therefore, if the ready signal IR from the memory FIFO applied to the data terminal D of FFC/FF ₂ is generated as "H", or if it is generated, it is simultaneously transmitted to the FFC/FF ₂ via OR gate _G1 . is applied to the reset terminal R of
In response to the rise of the clock pulse CLK applied via the gate _G2 , FFC/ _FF2 is set, the output terminal Q is changed to "H", and this is sent to the memory FIFO as a write start signal SI.

Also, when the output terminal Q of FFC/FF ₂ becomes "H", this is applied to the clock terminal CK of FFC/FF ₁ , and its data terminal D is connected to the common circuit and becomes "L". Therefore, FFC/FF ₁ is reset, output terminal Q is changed to “L”, and AND
Gate _G2 is turned off to stop sending out the clock pulse CLK.

On the other hand, the memory FIFO enters the write state in response to the write start signal SI and sets the ready signal IR to “L”.
In order to return to the current state, data terminal D and reset terminal R of FFC/FF ₂ go to "L", FFC/FF ₂ is also reset, output terminal Q is changed to "L", and sending of the write start signal SI is stopped. At the same time, all circuits return to their initial states.

Therefore, FFC/FF ₁ maintains the given condition of the write command signal and also ensures that this condition matches the given condition of the ready signal.
It is detected by FFC/FF ₂ , and when both conditions match, a write start signal SI is sent out in synchronization with the clock pulse CLK, and the write command signal is
The states of the WT and the memory FIFO are matched, and the input control of the memory FIFO becomes stable and reliable.

However, depending on the situation, OR gate G ₁ may be replaced with a NOR gate, etc., AND gate G ₂ may be replaced with a NAND gate, etc., and a latch circuit or memory, etc. may be used for FFC/FF ₁ and FF ₂ , and these The same effect can be obtained by selecting the configuration according to the conditions of the external equipment, and the output circuit OC can be modified in various ways, such as by selecting one according to the conditions of the external device.

〔Effect of the invention〕

As is clear from the above explanation, according to the present invention, the processor only needs to send out a write command signal, which reduces the operating load on the processor, creates a margin in the operating status of the processor, and prevents the structure from becoming unstable. Since there are no external elements and input control to the memory can be made stable and reliable, a remarkable effect can be obtained in data transfer from the processor. Furthermore, since the write start signal is generated in synchronization with the clock pulse, there are no timing fluctuations, further increasing control stability.

[Brief explanation of drawings]

The figures show an embodiment of the present invention, with FIG. 1 being a block diagram of the entire configuration, and FIG. 2 being a block diagram of the input control circuit. CPU...Processor, FIFO...Memory (sequential input/output memory), OC...Output circuit, ICT...Input control circuit, FF ₁ , FF ₂ ...FFC (flip-flop circuit), G ₁ ...OR gate, G ₂ ...AND gate,...Write command signal, IR...Ready signal, SI...Write start signal, CLK...Clock pulse.

Claims (1)

[Scope of Claims] 1. A sequential input/output memory that sequentially stores and sequentially transmits data from a processor; an output circuit that transmits data from the memory to the outside; and a circuit that receives a write command signal from the processor. and an input control circuit that sends a write start signal to the memory in synchronization with a clock pulse of the processor, in response to a match between the condition given by the readiness signal and the condition given by the readiness signal from the memory. Data transfer circuit.