JPH02224162A - Memory control device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to memory control in a computer system.

[Conventional technology]

Figure 3 shows an example of a conventional memory with error detection and correction code (hereinafter referred to as ECC).
input data signal group (a) and second input data signal group (
(d) is an input and generates ECC (g), (4) is the first memory, (5) is the second memory IJ, (
7) is the ECC memo cable (8) < 1117) the input data selection signal (b), the second input data selection signal (e), the first input data signal group (a) and the second input data A write timing signal (H) for inputting the signal group (D) to the memory is input, and a first write signal (S) for controlling writing to the first memory (4) and the second memory (4) are input. 5) A write control circuit that outputs a second write signal (W) for controlling the write, where (W) is a memory address.

FIG. 4 is a general operation explanatory diagram of FIG. 3;
In FIG. 4, a memory address (wa), a first input data signal group (a), a first input data selection signal (b), a second input data signal group (d), and a second input data selection When the signal (E) is input, the first input data signal group (A)
and ECC (g) for the second input data signal group (d)
is generated, and furthermore, by inputting the write timing signal (ch), the first write signal (su) and the second write signal (wo) are generated, and the first memory (4) and the second memory ( 5) and write the respective data to the ECC memory (7).

[Problem to be solved by the invention]

In the memory shown in FIG. 3, one FCC is generated for the first input data signal group (a) and the second input data signal group (d), so as shown by the broken line in FIG. When writing only the first input data signal group (a) to
There is a problem that FCC cannot occur. The same applies to the case where only the second input data signal group (d) is written.

Furthermore, if separate FCCs are attached to the first input data signal group (a) and the second input data signal group (d), the number of signal lines will increase (input data lines: 16, EC
C: 6 lines, input data lines: 8 lines, ECC: 5
There is also the issue of needing books.

[Means to solve the problem]

The present invention receives a first input data signal group and a first input data selection signal as input, and the first input data selection signal selects the first input data signal group or high impedance (
a first data control circuit which outputs high impedance) as a first output data signal group; a second input data signal group and a second input data selection signal; 2 input data signals or high impedance
pedance) as a second output data signal group, a first input data selection signal, a second input data selection signal, a first input data signal group and a second input data signal. a first write/read signal for controlling writing/reading of a first memory to which a write timing signal for inputting a group of data signals to a memory is input, and a first write/read signal for controlling writing/reading of a first memory to which the first output data signal group is connected; A write/read control circuit is added that outputs a second write/read signal that controls writing/reading of a second memory to which data signal groups are connected.

[Effect]

In the present invention, when writing only the first input data signal group, when writing only the second input data signal group by reading the data at the write address from the second memory and inputting it to the ECC generation circuit, , reads the data at the write address from the first memory and inputs it to the ECC generation circuit.

〔Example〕

FIG. 1 shows an embodiment according to the present invention. In the figure,
(1) inputs the first input data signal group (a) and the first input data selection signal (b), and selects the first input data signal group or high impedance (tlighlmpcda).
a first data control circuit that outputs (nse) as a first output data signal group (c); (2) inputs a second input data signal group (d) and a second input data selection signal (e); a second data control circuit (3) which outputs a second input data signal group or high impedance (formerly GH Impedance) as a second output data signal group (to);
) is an EC that receives the first output data signal group ()
C generation circuit, (4) is the first memory.

(5) is the second memory, (6) is the first input data selection signal (b), the second input data selection signal (e) and the first
input data signal group (a) and second input data signal group (
Write timing signal (d) for inputting to memory
a first write signal (su) that controls writing to the first memory (4) and a first write signal (su) that controls reading of the first memory (4);
a write/read control circuit that outputs a read signal (nu), a second write signal (ru) that controls writing to the second memory (5), and a second read signal (wo) that controls reading; (7) is the ECC memory, and (wa) is the memory address.

FIG. 2 is a timing diagram for explaining one embodiment. Give address X to memory address (wa). The initial data at address X in each memory are assumed to be AC and D, respectively. (In Figure 2, the bottom three are the data content at address X in the first memory, the data content at address X in the second memory, and E
The first input data signal group (a) with data content B is the input data (indicates the data content at address X of the CC memory).
Give only. Accordingly, only the first input data selection signal (b) is input as the input data selection signal. At this time, the first data control circuit (1) outputs B as the first output data signal group (c), and the second data control circuit (1) outputs B as the first output data signal group (c).
2) outputs high impedance.

The write/read control circuit (6) outputs a first write signal (su) and a second read signal (wo). As a result, the second output data signal group (
data C at address X of the second memory (5) as
is output. Data B of the first output data signal group (c) and data C of the second output data signal group (f) are input to the FCC generation circuit (3), and ECC (g) is applied to data B and C. E is generated. The first output data signal group (c) of data content B and the ECC of data content E (
)) are respectively written into the respective memories by the first write signal (su) and the write timing signal (chi).

At this time.

The data in the second memory remains unchanged.

〔Effect of the invention〕

As described above, according to the present invention, in a memory having a first input data group, a second input data group, and an FCC for both data groups, only one of the first or second input data group Even when writing FCC data, normal FCC can be added without increasing the number of FCC data.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a memory control device according to the present invention, FIG. 2 is a timing diagram for explaining the operating principle of the present invention, and FIG. 3 is a block diagram of a conventional memory control device. FIG. 4 is a timing diagram for explaining the operating principle of a conventional memory control device. In the figure, (1) is the first data control circuit, (2) is the second data control circuit, (3) is the FCC generation circuit, and (4) is the FCC generation circuit.
) is the first memory 1c (5) is the second memory, (6) is the write/read control circuit, (7) is the ECC memory, (8
) is a write control circuit, and (a) is a first input data signal group. (b) is the first input data selection signal, (/\) is the first output data signal group, (d) is the second input data signal group,
(E) is the second input data selection signal, (F) is the second output data signal group, (G) is the FCC, (H) is the write timing signal, and (S) is the first write signal. (J) is the first read signal, (R) is the second write signal, (W) is the second read signal, and (W) is the memory address. Note that the same reference numerals in each figure indicate the same or corresponding parts. Figure 1

Claims (1)

[Claims] A first input data signal group and a first input data selection signal are input, and the first input data selection signal selects the first input data signal group or high impedance.
Impedance) as a first output data signal group; a second input data signal group and a second input data selection signal; input data signals or high impedance
) as a second output data signal group, and an error detection circuit that receives the first output data signal group and the second output data signal group as input and outputs a determined error detection correction code. a correction code generation circuit, a first input data selection signal, a second input data selection signal, and a first input data selection signal;
and a second input data signal group to the memory, and which controls writing/reading of a first memory to which the first output data signal group is connected. a memory control circuit comprising a write/read control circuit that outputs a second write/read signal that controls writing/read of a second memory that connects the first write/read signal and the second output data signal group; Device.