JPH02224184A - Method for detecting position of hybrid integrated circuit substrate - Google Patents

Method for detecting position of hybrid integrated circuit substrate

Info

Publication number
JPH02224184A
JPH02224184A JP1045891A JP4589189A JPH02224184A JP H02224184 A JPH02224184 A JP H02224184A JP 1045891 A JP1045891 A JP 1045891A JP 4589189 A JP4589189 A JP 4589189A JP H02224184 A JPH02224184 A JP H02224184A
Authority
JP
Japan
Prior art keywords
recognition
region
integrated circuit
recognition mark
hybrid integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1045891A
Other languages
Japanese (ja)
Other versions
JPH0770856B2 (en
Inventor
Takashi Kimura
崇 木村
Yoshiyuki Tsumita
積田　義之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiyo Yuden Co Ltd
Original Assignee
Taiyo Yuden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiyo Yuden Co Ltd filed Critical Taiyo Yuden Co Ltd
Priority to JP1045891A priority Critical patent/JPH0770856B2/en
Publication of JPH02224184A publication Critical patent/JPH02224184A/en
Publication of JPH0770856B2 publication Critical patent/JPH0770856B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/601—Marks applied to devices, e.g. for alignment or identification for use after dicing
    • H10W46/603—Formed on wafers or substrates before dicing and remaining on chips after dicing

Landscapes

  • Structure Of Printed Boards (AREA)
  • Supply And Installment Of Electrical Components (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)
  • Image Analysis (AREA)
  • Image Processing (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、混成集積回路基板をマウント装置やワイヤボ
ンディング装置に装填し、装填位置を画ｆ象認識によっ
て検出する混成集積回路基板の位置検出方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to position detection of a hybrid integrated circuit board in which the hybrid integrated circuit board is loaded into a mounting device or a wire bonding device, and the loading position is detected by image recognition. Regarding the method.

［従来の技術］ 混成系８を回路基板上にマウンター装置によって電子部
品をマウントする場合や、基板上の半導体チップにワイ
ヤーボンディング装置によってワイヤーボンディングす
る場合には、ｔ　％パターン、厚膜抵抗等が形成された
基板をこれらの装置の所定の位置に配置しなければなら
ない、所定の位置に配置されたか否かは、従来、第７図
及び第８図のように、基板１上に電極パターン、抵抗、
ガラス等の印刷時に同時に設けられた認識マーク２を、
ＣＣＤカメラ等で光学的に読み収り、標準マークと比較
して決定する。[Prior Art] When mounting electronic components on the hybrid system 8 on a circuit board using a mounter or wire bonding to a semiconductor chip on the board using a wire bonding equipment, a t% pattern, a thick film resistor, etc. are used. The formed substrate must be placed in a predetermined position of these devices.Whether or not it has been placed in a predetermined position can be determined by conventionally forming an electrode pattern on the substrate 1, as shown in FIGS. 7 and 8. resistance,
The recognition mark 2 that was placed at the same time as printing on glass etc.
The mark is optically read using a CCD camera, etc., and compared with the standard mark.

［発明が解決しようとする課題］ ところで、認識マーク２は、電極パターン、抵抗、ガラ
ス等の印刷時に設けられるため、その後の工程において
上面に傷が付く場合があった。認識マーク上面に傷が付
いた場合、傷により上面に乱反射が起り、認識エラーを
起こすことがある。[Problems to be Solved by the Invention] By the way, since the recognition mark 2 is provided during printing of electrode patterns, resistors, glass, etc., the upper surface may be scratched in subsequent steps. If the top surface of the recognition mark is scratched, the scratches may cause diffuse reflection on the top surface, resulting in recognition errors.

そこで、本発明の目的は、傷による認識エラーを防ぐこ
とができる混成集積回路基板の位置検出方法を提供する
ことにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for detecting the position of a hybrid integrated circuit board that can prevent recognition errors caused by scratches.

［課題を解決するための手段〕 上記目的を達成すための本発明は、混成集積回路を構成
するための基板上に認識マークを設け、この認識マーク
を光学的に読み収って前記基板の位置を検出する混成集
積回路基板の位置検出方法において、第１の色の第１の
領域とこの第１の領域の外側に配設された第２の色の第
２の領域とから成る認識マークを設けると共に、前記第
２の領域の周辺に前記第１の領域を基準にして前記第２
の領域よりも突出している突出部を設け、前記第１及び
第２の領域を利用した画像認識によって前記基板の位置
検出を行う混成集積回路基板の位置検出方法に係わるも
のである。[Means for Solving the Problems] To achieve the above object, the present invention provides a recognition mark on a substrate for configuring a hybrid integrated circuit, optically reads the recognition mark, and detects the recognition mark on the substrate. In a method for detecting a position of a hybrid integrated circuit board, the recognition mark includes a first region of a first color and a second region of a second color disposed outside the first region. is provided around the second area, and the second area is provided around the second area based on the first area.
The present invention relates to a method for detecting the position of a hybrid integrated circuit board, in which a protruding portion is provided that protrudes beyond the area of the hybrid integrated circuit board, and the position of the board is detected by image recognition using the first and second areas.

なお、突出部は第２の領域と同一材料で形成することが
望ましい。Note that it is desirable that the protruding portion be formed of the same material as the second region.

［作用］ 本発明における突出部は第２の領域の保護領域として機
能する。即ち、第２の領域は突出部よりも低いので、突
出部によって保護され、第２の領域に傷が付き難い、突
出部には傷が付いても、突出部は画像認識に無関係な領
域であるから認識エラーは発生しない。[Function] The protrusion in the present invention functions as a protection area for the second area. In other words, since the second area is lower than the protrusion, it is protected by the protrusion and is unlikely to be scratched. Even if the protrusion is scratched, the protrusion is an area unrelated to image recognition. Because of this, recognition errors do not occur.

［実施例］ 次に、第１図〜第４図を参照して本発明の実施例に係わ
る混成集積回路基板の位置検出方法を説明する。[Embodiment] Next, a method for detecting the position of a hybrid integrated circuit board according to an embodiment of the present invention will be described with reference to FIGS. 1 to 4.

第３図に示すように、・多数のアルミナ基板１１のそれ
ぞれの周辺部に認識マーク１２を印刷する。As shown in FIG. 3, a recognition mark 12 is printed on the periphery of each of a large number of alumina substrates 11.

この認識マーク１２は、銀パラジウム電極材料の印刷に
よって形成する。なお、認識マーク１２は電極即ち配線
導＃：（図示せず）と同時に形成する。This recognition mark 12 is formed by printing silver palladium electrode material. Note that the recognition mark 12 is formed at the same time as the electrode, that is, the wiring conductor # (not shown).

第３図では各基板１１の対角線上の２箇所に設けられて
いる。In FIG. 3, they are provided at two diagonal locations on each substrate 11.

第１図及び第２図に拡大図示されている認識マーク１１
は、黒（第１の色）として認識されるセラミック基板１
１からなる第１の領域１３とこれを囲む銀パラジウム系
導体から成る第２の色の第２の領域１４と、土手のよう
に形成された突出部１５とから成る。突出部１５は第１
の領域１３と同一の銀パラジウム系導体から成り、第１
の領域と同時に形成されている。第２の領域１４は突出
Ｍ１５から基板１１の表面に向って垂れ下がっている傾
斜面領域であって、白（第２の色）として認識される。Recognition mark 11 shown in enlarged view in Figures 1 and 2
is a ceramic substrate 1 recognized as black (first color)
1, a second region 14 of a second color made of a silver-palladium-based conductor surrounding the first region 13, and a protrusion 15 formed like a bank. The protrusion 15 is the first
The first region is made of the same silver-palladium conductor as the region 13.
It was formed at the same time as the region of The second region 14 is an inclined surface region that hangs down from the protrusion M15 toward the surface of the substrate 11, and is recognized as white (second color).

導体から成る認識マーク１２は四角形であって、外側の
各辺の長さは約１ｆｆｍであり、四角形の第１の領域１
３の各辺の長さは約０．４市である。The recognition mark 12 made of a conductor is a rectangle, the length of each outer side is approximately 1ffm, and the first area 1 of the rectangle is
The length of each side of 3 is approximately 0.4 city.

認識マーク１２の形成が終了したら、厚膜抵抗（図示せ
ず）を形成する。After the formation of the recognition mark 12 is completed, a thick film resistor (not shown) is formed.

次に、電子部品（半導体チップ）をマウントするために
、認識マーク１２を有する基板１１をマウント装置に装
填する。第４図はマウント装置における位置検出方式を
原理的に示すものであり、台１６上の基板１１の認識マ
ークを読み取るためのＣＯＤカメラ１７、及び認識装置
１８等を含む。Next, in order to mount electronic components (semiconductor chips), the substrate 11 having the recognition mark 12 is loaded into the mounting device. FIG. 4 shows the principle of the position detection method in the mounting device, and includes a COD camera 17 for reading the recognition mark on the substrate 11 on the stand 16, a recognition device 18, and the like.

認識装置１８には、第１の領域１３に対応した標準マー
ク（画像データ）が予め書き込まれているメモリを内蔵
しており、この標準マークとカメラ１７で読み取った認
識マークとを比べて所定位置を検出する。認識装置１８
によって認識マーク１２と８準マークとが不一致である
ことが判定された時には移動装置（図示せず）によって
基板１１を移動して両マークを一致させる。第２図に鎖
線で示す認識エリア１９の中に第１の領域１３が入った
場合に標準マークと合致したものと見なされる。The recognition device 18 has a built-in memory in which a standard mark (image data) corresponding to the first area 13 is written in advance, and compares this standard mark with the recognition mark read by the camera 17 to identify a predetermined position. Detect. Recognition device 18
When it is determined that the recognition mark 12 and the 8 quasi-mark do not match, the substrate 11 is moved by a moving device (not shown) so that the two marks match. When the first region 13 falls within the recognition area 19 shown by the chain line in FIG. 2, it is considered that it matches the standard mark.

基板１１の位置ずれが補正されたら、電子部品をマウン
トし、半田付けする。しかる後、ワイヤボンディング装
置に電子部品（半導体チップ）をマウントした後の基板
１１を移し、マウント時と同様な方法で基板１１の位置
決めをなし、電子部品（半導体チップ）にワイヤを接続
する。After the positional deviation of the board 11 is corrected, electronic components are mounted and soldered. Thereafter, the board 11 with the electronic component (semiconductor chip) mounted thereon is transferred to a wire bonding device, the board 11 is positioned in the same manner as during mounting, and wires are connected to the electronic component (semiconductor chip).

本実施例の位置検出方法は次の効果を有する。The position detection method of this embodiment has the following effects.

（１）　突出部１５によって土手状に囲まれている第１
の領域１３と第２の領域１４とが認識工リア１９となる
ので、突出部１５に傷が付いても、これに無関係にパタ
ーン認識を行うことが可能になり、認識エラーが少なく
なる。(1) The first part surrounded by the protruding part 15 in a bank shape
Since the area 13 and the second area 14 serve as the recognition area 19, even if the protrusion 15 is scratched, pattern recognition can be performed regardless of this, and recognition errors are reduced.

（２）　第２の領域１４は突出部１５の形成によって必
然的に生じる傾斜部であるので、認識マーク１２の形成
が複雑にならない。(2) Since the second region 14 is a slope inevitably generated by the formation of the protrusion 15, the formation of the recognition mark 12 is not complicated.

［変形例］ 本発明は上述の実施例に限定されるものでなく、例えば
次の変形が可能なものである。[Modifications] The present invention is not limited to the above-described embodiments, and, for example, the following modifications are possible.

（１）　認識マーク１２を第５図に示すように断面形状
半円形状に形成してもよい。(1) The recognition mark 12 may be formed to have a semicircular cross-section as shown in FIG.

（２）　第６図に示すように、複数の基板１１の共通の
周辺部に認識マーク１２を設けてもよい。(2) As shown in FIG. 6, a recognition mark 12 may be provided in a common peripheral area of a plurality of substrates 11.

（３）　認識マーク１２を抵抗体と基板１１との組み合
わせで形成することができる。また、認識マーク１２を
導体と抵抗体との組み合わせで形成することもできる。(3) The recognition mark 12 can be formed by a combination of a resistor and the substrate 11. Further, the recognition mark 12 can also be formed by a combination of a conductor and a resistor.

（４）　認識マーク１２を平面形状円形にしてもよい。(4) The recognition mark 12 may have a circular planar shape.

［発明の効果］ 上述のように本発明によれば、認識マークの傷による認
識エラーの発生が少ない混成集積回路基板の位置検土方
法を提供することができる。[Effects of the Invention] As described above, according to the present invention, it is possible to provide a position detection method for a hybrid integrated circuit board in which recognition errors due to scratches on recognition marks are less likely to occur.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の実施例に係わる認識マークを示す第２
図のＩ−Ｉ線に対応する断面図、第２図は第１図の認識
マークを示す平面図、第３図は基板と認識マークとを示
す平面図、第４図はマウント装置における画像認識シス
テムを原理的に示すブロック図、 第５図は変形例の認識マークを示す断面図、第６図は変
形例の基板と認識マークとを示す平面図、 第７図は従来の認識マークを示す平、面図、第８図は第
７図の認識マークの断面図である。 １１・・・基板、１２・・・認識マーク、１３・・・第
１の領域、１４・・・第２の領域、突出部・・・１５、
認識装置・・・１８゜FIG. 1 is a second diagram showing a recognition mark according to an embodiment of the present invention.
FIG. 2 is a plan view showing the recognition mark in FIG. 1, FIG. 3 is a plan view showing the board and the recognition mark, and FIG. 4 is image recognition in the mounting device. A block diagram showing the principle of the system, Fig. 5 is a sectional view showing a modified recognition mark, Fig. 6 is a plan view showing a modified board and recognition mark, and Fig. 7 shows a conventional recognition mark. 8 is a cross-sectional view of the recognition mark of FIG. 7. DESCRIPTION OF SYMBOLS 11... Substrate, 12... Recognition mark, 13... First area, 14... Second area, Protrusion part... 15,
Recognition device...18°

Claims (1)

【特許請求の範囲】 ［１］混成集積回路を構成するための基板上に認識マー
クを設け、この認識マークを光学的に読み取って前記基
板の位置を検出する混成集積回路基板の位置検出方法に
おいて、第１の色の第１の領域とこの第１の領域の外側
に配設された第２の色の第２の領域とから成る認識マー
クを設けると共に、前記第２の領域の周辺に前記第１の
領域を基準にして前記第２の領域よりも突出している突
出部を設け、前記第１及び第２の領域を利用した画像認
識によって前記基板の位置検出を行うことを特徴とする
混成集積回路基板の位置検出方法。 ［２］前記突出部は前記第２の領域と同一材料で同時に
形成されたものである請求項１記載の混成集積回路基板
の位置検出方法。[Scope of Claims] [1] A method for detecting the position of a hybrid integrated circuit board, in which a recognition mark is provided on a substrate for configuring a hybrid integrated circuit, and the position of the substrate is detected by optically reading the recognition mark. , a recognition mark consisting of a first region of a first color and a second region of a second color disposed outside the first region is provided, and the recognition mark is provided around the second region. A hybrid device characterized in that a protruding portion is provided that protrudes from the second region based on the first region, and the position of the substrate is detected by image recognition using the first and second regions. A method for detecting the position of an integrated circuit board. [2] The method for detecting the position of a hybrid integrated circuit board according to claim 1, wherein the protruding portion is formed of the same material as the second region at the same time.
JP1045891A 1989-02-27 1989-02-27 Position detection method for hybrid integrated circuit board Expired - Fee Related JPH0770856B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1045891A JPH0770856B2 (en) 1989-02-27 1989-02-27 Position detection method for hybrid integrated circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1045891A JPH0770856B2 (en) 1989-02-27 1989-02-27 Position detection method for hybrid integrated circuit board

Publications (2)

Publication Number Publication Date
JPH02224184A true JPH02224184A (en) 1990-09-06
JPH0770856B2 JPH0770856B2 (en) 1995-07-31

Family

ID=12731865

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1045891A Expired - Fee Related JPH0770856B2 (en) 1989-02-27 1989-02-27 Position detection method for hybrid integrated circuit board

Country Status (1)

Country Link
JP (1) JPH0770856B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3015765A4 (en) * 2013-06-25 2016-06-29 Zhiming Chen COOLING DEVICE FOR HIGH POWER LED LAMP AND METHOD FOR MANUFACTURING SAME
EP3015764A4 (en) * 2013-06-25 2016-06-29 Zhiming Chen HIGH POWER LED LIGHT ROAD LIGHTING LUMINAIRE WITH ITS MANUFACTURING METHOD
WO2018155089A1 (en) * 2017-02-23 2018-08-30 株式会社村田製作所 Electronic component, electronic apparatus, and method for mounting electronic component

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3015765A4 (en) * 2013-06-25 2016-06-29 Zhiming Chen COOLING DEVICE FOR HIGH POWER LED LAMP AND METHOD FOR MANUFACTURING SAME
EP3015764A4 (en) * 2013-06-25 2016-06-29 Zhiming Chen HIGH POWER LED LIGHT ROAD LIGHTING LUMINAIRE WITH ITS MANUFACTURING METHOD
US9989238B2 (en) 2013-06-25 2018-06-05 Zhiming Chen Low light failure, high power led street lamp and method for manufacturing the same
WO2018155089A1 (en) * 2017-02-23 2018-08-30 株式会社村田製作所 Electronic component, electronic apparatus, and method for mounting electronic component
JP6384647B1 (en) * 2017-02-23 2018-09-05 株式会社村田製作所 Electronic component, electronic device, and mounting method of electronic component
US10772216B2 (en) 2017-02-23 2020-09-08 Murata Manufacturing Co., Ltd. Electronic component, electronic device, and method for mounting electronic component

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JPH0770856B2 (en) 1995-07-31

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