JPH02224332A - Semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device. In particular, high reliability AS
IC (Application-Specific
-Integrated-Circuit) Effective in semiconductor devices.

[Prior Art J] Conventionally, the input-output structure (hereinafter referred to as input/output pad area) of an ASIC semiconductor device has N, H, and E pads.

Weste, K. Eshraghian, “P.
r1nciples of CLIO3VLSI De
sign: A Systems PerSpect
ive Addison-Wesley Publicis
hing (:company, Inc, (19851
”, there is no reason to reduce the size of the wiring from the pad to the power supply line, thick wiring extends from the pad to the chip, and thick wiring for V on and V gg is connected to the input/output pad area. was crossing.

As integrated circuits (hereinafter referred to as ICs) become more highly integrated, the number of chips increases, the number of resin packages increases, and the number of layers of A12 alloy wiring increases.
Thermal stress caused by the thermal expansion of the resin package and the thermal expansion of the resin package impairs the reliability of the rC. In particular, due to the simplicity of the design method and the ease of connection with external signals, the influence of thermal stress caused by resin is strongest in the input/output pad area installed on the outer periphery of the chip. Thermal stress of the Al wiring itself and the resin is concentrated at the edge of the Al wiring pattern in the region, causing cracks in the glabella insulating film, stress migration of Al2 through the cracks, and frequent failures such as short circuits and disconnections.

[Problem to be solved by the invention]

It is an object of the present invention to avoid such defects of conventional ASIC semiconductor devices and to provide a highly reliable ASIC semiconductor device while minimizing cost and design man-hours.

[Means to solve the problem]

In the present invention, the ASIC semiconductor device has versatility,
Moreover, Va. has a limited number of cells. ,■□, An input/output pad area consisting of input, output pads, etc. is placed around the chip where the thermal stress of the resin is large, and the A of the input/output pad area is
By forming slits or holes in the β or Aj2 alloy wiring layer, the thermal stress of Al itself and the resin applied to the end of the Aβ pattern of unit length is alleviated. Since the input/output pad area has a limited number of cells, the increase in design man-hours can be minimized. In addition, the input/output pad area is
The Al wiring layer is simple and there are only a few layers (even if the width of the Al wiring increases due to the formation of slits and holes, it has little effect on the cell size and chip size, and there is no increase in cost.

[Example J] Hereinafter, an explanation will be given using an example. 1 to 4 show plan views of a semiconductor device according to the present invention. FIG. 1 is a layout diagram of a standard cell system used in the present invention. , an input/output pad area 1. FIG. 2 is a layout diagram of the gate array system used in the present invention. 113
, and an input/output pad region 11. 1st.
Both of FIGS. 2A and 2B are characterized in that an input/output pad area is formed on the outer periphery of the chip. Furthermore, in the present invention, Al2 or A of the input/output pad area (1, 11)
A feature is that slits or holes are formed in the l2 alloy wiring, and there are no slits or holes formed in other chip internal regions.

3 and 4 are plan views of the output pad area according to the present invention in the case of one layer of Aβ wiring and two layers of β wiring, respectively. Third
In the figure, Voo path 23. Voo pad 21, Voo wiring 22. and the Vss bus 24.

V is made of an Al2- layer and intersects with the VIIO wiring 22.

Bus region 25 is formed of polysilicon and connected through contact hole 26 . , l wiring regions are formed with slits 27 to relieve thermal stress caused by Aβ itself and the resin, and to avoid concentration of stress at specific locations (for example, at the ends of the Al pattern). In FIG. 4, the Vll bus 34 is formed of the Aβ-th layer, the Voo pad 31, and the CF Voo
C; L, 32.33 is an output pad formed of the second Al layer. A slit 35 and a slit 36 are formed in the first and second layers of Al wiring, respectively, and thermal stress is applied to specific locations (
For example, concentration at the pattern end of the Aβ wiring where the -th layer Ag wiring and the second layer Al wiring intersect is avoided.

Therefore, in the present invention, stress concentration in Aβ itself and the resin is avoided, and defects in reliability of IC semiconductor devices caused by thermal stress do not occur. Since the hole formation is limited to a small number of cells and only to the general-purpose input/output pad area, there is almost no increase in the number of design steps. There is no need to form slits, the number of design steps is the same as before, and there is no delay in delivery.Furthermore, the /l wiring in the input/output area has a wide margin (space area), and the increase in Al width by forming Al slits or holes , there is no increase in the input/output pad area size (the space area becomes narrower).

[Effect of the Invention 1] As explained above, according to the semiconductor device of the present invention, a highly reliable ASIC semiconductor device can be provided without increasing costs or delaying delivery.

Although the Voo pad area has been described in the embodiment of the present invention, the same applies to input pads, ternary pads, bidirectional pads, and other input/output pad areas.

[Brief explanation of the drawing]

FIG. 1 is a diagram of a standard cell system according to the present invention, FIG. 2 is a diagram of a gate array system according to the present invention, FIG. 3 is a diagram showing an Al2-layer Vt1O pad according to the present invention, and FIG.
The figure shows an Aff double-layer Voo pad according to the present invention. l, 1 l, 2 ・ ・ ・ 3, 3' 4, 13 ・ 21, 31 ・ 22, 23. 24, 34 ・ 25 ・ ・ ・ ・ 26 ・ ・ ・ 27, 35, l 2 ・ ・ ・ 32, 33 ・ 36 ・ ・ ・ ・ ・ Input/output pad area・Functional cell・Cell・Wiring・Voo pad・VOO Bus, V-Liao 8 bus, polysilicon, contact hole, Aelsi! Line layer pickpocket/lA't10 ¥21 figure Applicant: Seiko Epson Corporation

Claims (2)

[Claims] (1) In an integrated circuit semiconductor device composed of a gate array or a standard cell, the input-output structure of the IC is installed in the outer peripheral area of the chip, and the Al or Al alloy wiring layer of the input-output structure is , a semiconductor device characterized by having a slit or a hole formed therein. (2) Al or Al in the standard cell area placed in the chip internal area other than the input-output structure of the integrated circuit;
2. The semiconductor device according to claim 1, wherein the alloy wiring layer has no slit or hole.