JPH02224480A - Solid-stage image pickup element - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a solid-state image sensor, and more specifically, to a photoelectric conversion unit in which a large number of pixel elements that convert optical signals of pixels into electrical signals are arranged on a semiconductor substrate. The present invention also relates to a solid-state imaging device, in particular the structure of a pixel element, which has a scanning section for selecting the pixel element and an output section for reading out a signal from the scanning section as an image signal to the outside.

[Conventional technology]

Many types of solid-state image sensors have been known in the past, but one with a particularly high signal-to-noise ratio is a pixel amplification type solid-state image sensor, which has a structure in which an amplification element is provided for each pixel. Regarding the type of pixel amplification type solid-state imaging device, there is a document published by IEDM Technical.
Digest 16.4. Pages 400 to 443 (1
985) (IEDM Tech, Dig, 16.4
pp. 400-443 (1985)). The pixel element used in the solid-state image sensor described in the above-mentioned document is composed of a static induction transistor shown in FIG.

In the same figure, 12, 13 and 14 are pt layer gates which are the sources of static induction transistors, respectively.
5 is a trench isolation for preventing crosstalk between adjacent pixels, and 4 is a gate capacitor.

Such pixel elements are arranged in horizontal and vertical rows and columns, and the pixel elements are selected by signals from vertical and horizontal scanning circuits, converted into electrical signals, and output as image signals.

The output voltage signal of the above pixel element is α, G L A / (
Ca+Ct). Here, Ca is the capacitance value of the gate capacitor 4, CT is the capacitance value between the gate 13 and the substrate 14, and the capacitance value between the gate 13 and the source 12, and Cc + C
r is the value of storage capacity. In addition, A is the area of the light utilization area (the shaded area in FIG. 10(b)) excluding the area of gate capacitance 4 of the gate 13, GL is the charge generation rate, and α is a factor determined by the characteristics of the static induction transistor. be.

[Problem to be solved by the invention]

When a large number of pixel elements as described above are manufactured on a semiconductor substrate by an LSI manufacturing process, it is difficult to manufacture the constants of each pixel element to be completely uniform, and variations in element constants inevitably exist.

The above conventional technology does not take into account the uniformity of the output signal, and even when irradiated with uniform light, the output voltage from each pixel is not uniform, and only images with extremely poor image quality can be reproduced. There was a problem. That is, the first
Even if uniform light is irradiated, the gate voltage does not change uniformly due to variations in the light utilization area A and variations in the storage capacitance Ca + Cr.

Second, even if the gate voltage changes uniformly, the source line voltage fluctuations do not become uniform due to variations in the static induction transistor α provided in each pixel.

Further, the above-mentioned conventional technology does not take into consideration the reduction of dark current, and there is a problem in that the variation from pixel to pixel deteriorates the image quality at low illuminance.

Therefore, a first object of the present invention is to provide a pixel amplification type solid-state image pickup device that can obtain a uniform signal output when uniform light is irradiated even if the above-mentioned variations in device constants exist. Another object of the present invention is to reduce dark current in a solid-state imaging device having a structure that satisfies the first object.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a pixel comprising, on a semiconductor substrate, a photoelectric conversion element that generates a signal charge corresponding to optical information of a pixel, and an amplification element that generates an amplified signal corresponding to the signal charge of the photoelectric conversion element. In a solid-state imaging device having a photoelectric conversion section formed with a large number of children, an inverting amplifier circuit is configured using the amplification element as a component, and a feedback capacitor is provided between the output terminal of the amplification element and the photoelectric conversion element. . Furthermore, the formation area of this feedback capacitance and the light use area of each pixel are made to almost match.

The amplifying element is not limited to the electrostatic induction type transistor, but is composed of a semiconductor circuit such as a MOS transistor or a bipolar transistor. The photoelectric conversion element includes a case where it constitutes a part of the above-mentioned amplification element, such as a photodiode, and is constituted by a storage capacitor element that converts optical information into charge and stores it.

In order to achieve the other objectives mentioned above, the feedback capacitance is set to MO5.
A predetermined period during which no signal is output to the amplifier output end of the MO8 capacitor.

The structure is such that a voltage is applied to the surface of the first impurity layer forming the photoelectric conversion element so that a carrier layer having a polarity opposite to that of the first impurity layer is formed. Further, the second impurity layer forming the photoelectric conversion element is covered with a third impurity layer having a polarity opposite to that of the second impurity layer, and this third impurity layer is covered with the second impurity layer forming the photoelectric conversion element. The layer is separated from the substrate by a depletion layer around the layer. moreover,
A third impurity layer having a polarity opposite to that of the second impurity layer is provided on the second impurity layer forming the photoelectric conversion element, and the third impurity layer is separated from the substrate by a second impurity pattern, and Means is provided on the surface of the second impurity layer in this isolation region for inducing a carrier layer having the same polarity as the substrate during a certain period when no signal is output.

[For production]

Fluctuations in the output voltage of the pixel element in the solid-state image sensor of the present invention,
That is, the voltage fluctuation Vs of the inverting amplifier can be expressed by the following equation.

Here, Qs is the signal charge amount, CF is the capacitance value of the feedback capacitor,
Cp is the capacitance value other than the feedback capacitance attached to the input terminal of the amplifier, and G is the oven loop gain of the amplifier.

Now, if G is designed to be sufficiently large (for example, 10 times or more), the above equation can be approximated by Qs Vs = -- CF.

Therefore, the characteristic α of the transistor, which is a factor of variation in the output voltage mentioned above, is expressed in the gain G, and variation due to these factors is suppressed. Further, the signal charge Qs is the area A of the light use area of each pixel.

The variation in the signal charge Qs from pixel to pixel when illuminated with light of the same intensity is caused by the variation in the area of the light utilization region. On the other hand, the value CF of the feedback capacitance is proportional to the area of the region where the feedback capacitance is formed, and variations in the capacitance value occur due to variations in the region where the feedback capacitance is formed. Therefore, by making the region where the feedback capacitance is formed coincide with the optical use region, the signal voltage becomes almost constant regardless of the variations in each area.

Further, at the amplifier output terminal of the feedback capacitor formed by the MO8 capacitor, carriers of opposite polarity to the first impurity layer are formed on the surface of the first impurity layer forming the photoelectric conversion element during a predetermined period in which no signal is output. A voltage is applied to form a layer. As a result, the level existing on the surface of the impurity layer forming the photoelectric conversion element is filled with carriers, so that the generation of dark current can be suppressed. Furthermore, due to the third impurity layer having the opposite polarity to the second impurity layer provided on the second impurity layer forming the photoelectric conversion element, the surface of the second impurity layer forming the photoelectric conversion element can generate a dark current. The depletion layer, which is formed in the deep part of the substrate where there are few levels that are a source of generation, and around the second impurity layer electrically isolates the impurity layer on the photoelectric conversion element and the substrate. As a result, dark current is suppressed, and the third impurity layer on the photoelectric conversion element can serve as an upper electrode of a feedback capacitor electrically isolated from the substrate.

Further, the second impurity layer on the second impurity layer forming the photoelectric conversion element is
The third impurity layer having the opposite polarity to the impurity layer is separated from the substrate by the second impurity layer forming the photoelectric conversion element, and there is a certain period of time during which no signal is output on the surface of the second impurity layer in this separation region. A carrier layer with the same polarity as the substrate is induced. As a result, during signal readout, the third impurity layer can play the role of the upper electrode of the feedback capacitor electrically isolated from the substrate, and can also suppress the dark current generated in the isolation region. Current can be reduced.

〔Example〕

A first embodiment of a solid-state image sensor according to the present invention will be described with reference to FIGS. 1 to 3. FIG. 1 is a circuit configuration diagram of the solid-state image sensor of the first embodiment, FIGS. 2(a) and (b) are a plan configuration diagram and a cross-sectional configuration diagram of each pixel element in FIG. 1, respectively, and FIG. 3 (a) is a drive pulse timing diagram for explaining the operation of the solid-state image sensor in Figure 1, (b) is a diagram for explaining the method of setting the operating point of the inverting amplifier circuit, and (C) is a diagram for explaining the operation point setting method of the inverting amplifier circuit. 0 showing the potential diagram of a photodiode
The pixel of this example uses a fully depleted dual-gate vertical JFET that was previously proposed by the inventors (Japanese Patent Application No. 153292/1982). A means is provided for each column.

In FIG. 1, an n-channel fully depleted dual-gate vertical JFET 21 serving as a driver is an amplification element,
Together with the n-channel depletion MoS transistor 22 serving as a load, it forms an inverting amplifier circuit for detecting and amplifying the potential of a photodiode, which is a photoelectric conversion element.

23 is a feedback capacitor provided between the photodiode and the amplification element.

Note that, for the sake of simplicity, the drawings show a case in which nine pixel elements, each consisting of a photoelectric conversion element, an amplification element, and a feedback capacitor, are arranged in a matrix of 3 horizontally and 3 vertically.

2 is a vertical scanning circuit that selects each row; 3 is a level mixing circuit that generates three-value levels; and 5 is a horizontal scanning circuit. Further, 24 to 28 constitute an output circuit provided for each column in order to cancel variations in the DC voltage of each pixel, 24 is a coupling capacitor, and 25 is an output circuit for clamping one end of the coupling capacitor. A clamp switch 27 is a switch for writing a signal to the memory capacitor 26, and 28 is a switch for reading a signal from the memory capacitor 26. 29 is an amplifier for amplifying and outputting the signal charge read out to the horizontal signal line 30; 31 is a reset switch for resetting the horizontal signal line 30; 32 connects the output of the level mixing circuit 3 to each fully depleted dual gate vertical J FET.
A vertical gate line 33 is a vertical signal line for transmitting data to the gate of the signal line. φ0 is the power supply voltage of the inverting amplifier circuit, φC is the gate voltage of the clamp switch 25, VR is the reset voltage,
φ1, φ2 are the gate voltages of the read switch, Pl, P
2 is a two-phase clock signal that operates the horizontal scanning circuit, 0
1 and o2 are output terminals.

Note that the load 22 may be a p-channel MOS transistor or an n-channel MOS transistor.
A channel transistor may also be used.

In FIGS. 2(a) and 2(b) showing the structure of the pixel element, 4
1 is an n-type substrate, 42 is a floating low-concentration p-type impurity layer that becomes a photodiode, 43 is a p''-type impurity layer that becomes a reset gate for resetting pixel selection, 44 is polysilicon for wiring of the vertical gate line 32, 45 46 is a contact that serves as the source of the vertical JFET, and an n1 layer is formed for making ohmic contact.FIG. 1 Feedback capacitance 23 is formed between the p- impurity layer 42 which becomes a photodiode and the thin film polysilicon 45 which forms the vertical signal line 33.The light use region is the p- impurity region 42, and its plane region is the above-mentioned feedback region. This coincides with the formation area of the capacitor.If high-speed operation is required, the wiring layer 44 of the vertical gate line is formed with a low resistance wiring of silicide or aluminum, and the thin film polysilicon layer 45 is formed with a low resistance wiring of silicide or aluminum.
You can lower the resistance by connecting aluminum wiring to the moreover,
Reset gaiter? The potential of the impurity layer 43 may be controlled by capacitive coupling with the vertical gate line 44.

In FIG. 3(a), HBL is the horizontal blanking period, and n row is the nth row from the top in FIG. 1, φDφCφ□
φ2 indicates the voltage of the corresponding symbol in FIG. The voltage is higher in the upper part of the figure.

The vertical gate line voltage V L V MV N is always lower than the potential of the substrate 41 so that the p+ region 43 forming the reset gate is not in the forward direction with respect to the substrate 41 . Further, the voltage VDLVD)l of φD is always higher than the p+ region 43 so that the source region 46 is not in the forward direction with respect to the reset gaiter+ region 43.

Also, in Figure 3(b), the curve in the figure is a reset gaiter? This is a diagram showing the relationship between the voltage of the contact layer 46, which is the output of the inversion circuit, with respect to the potential of the photodiode p-impurity layer 42 when the region 43 is at VL, and Vpo is as shown in FIG.
The voltage of the photodiode p-impurity layer 42 when the voltage of the thin film polysilicon 45 shown in FIG.

VB is photodiode p-impurity layer 4 during signal readout
When φ0 changes from Vot to VDH, the photodiode voltage, which is Vpo at reset and shows a bias voltage of 2, is set to a bias point Va at which the inverting circuit has a high gain via the feedback capacitor 23. Further, in FIG. 3(C), each curve is a diagram showing the potential of the photodiode p-impurity layer 42 when the thin film polysilicon electrode 45 is at voltages VDL and VDH, and the high voltage VDII is a diagram showing the potential of the photodiode p-impurity layer 42 when the thin film polysilicon electrode 45 is at a voltage of VDL and VDH.
The voltage is such that carriers of the same type as the substrate, that is, electrons, are induced on the surface of the photodiode p-impurity layer 42 when the voltage is applied. On the other hand, at the surface potential of the photodiode p-impurity layer 42 during signal readout, carriers of the same polarity as the substrate are induced between the photodiode p-impurity layer 42 and the thin film polysilicon layer 45, and no shield reservoir is formed between the two electrodes. It is set as follows. The operation of this embodiment will be explained below.

When the horizontal blanking period begins, signals of n rows are first read out. That is, the 0th row vertical gate 832 is at V
As the voltage of the reset gaiter + impurity layer 43 increases, φD changes from VDL to Vo.

As a result, the voltage of the photodiode p-impurity layer 42 increases due to capacitive coupling via the output line 33 and the feedback capacitor 23, and the inverting amplifier with the fully depleted dual-gate vertical JFET 21 as a driver and the depletion MOS transistor 22 as a load has a high gain. Set to area. Immediately before this operation, the photodiode voltage is higher than the reset voltage Vpo by Vs' depending on the signal amount.
As a result of this operation, if the gain of the amplification element is sufficiently high, the photodiode voltage becomes a certain bias voltage VB near the threshold voltage Vt, and the output voltage becomes lower than the output voltage at reset by Va shown in the above equation. On the other hand, the reset switch 25 is conductive in this state, and the output terminal of the coupling capacitor 24 is at the reset voltage VR.

When the reset switch 25 closes (OFF), the coupling capacitance 2
After the output of the amplifier when there is a signal in the n row is held as the potential difference between the two ends of the photodiode p-impurity layer 42 (FIG. 3, 1=1.□), the photodiode p-impurity layer 42 is reset l-. That is, as the voltage φ0 becomes VDL again,
The voltage of the n-row vertical gate line 32 is equal to the punch-through voltage Vpt between the reset gaiter + impurity layer 43 and the photodiode p-impurity layer 42 and the photodiode p-impurity layer 4
The reset voltage VH becomes lower than the sum of the two reset voltages Vpo, and the photodiode p-impurity layer 42 is completely depleted and reset is performed (FIG. 3, 1=1.).
Thereafter, the amplifier output of each pixel when there is no signal is read out in the same way as when reading out the signal. That is, the clamp switch 25 remains closed (OFF) and the memory capacity 26-2
The signal read switch 27-2 opens. As a result,
The potential fluctuation of the coupling capacitor 24 from time 1=1L, that is, the potential fluctuation Vs of the amplifier output due to the signal,
The voltage of the memory capacity 26-2 rises above the reset voltage VR by the value divided by the capacity ratio between the memory capacity 26-2 and the memory capacity 26-2, and this voltage closes the switch 27-2 (OFF).
is held in the memory capacity 26-2 (Fig. 3(a) t
=t,).

After the above operation, the signal of the n+1 row is held in the memory capacitor 26-1 in exactly the same way (FIG. 3(a) t''t4). is kept at a voltage VM slightly lower than Vpt, and the vertical JFE
T will never become conductive, and even if it is exposed to strong light, the potential of the photodiode p-impurity layer 42 will be VM-VP.
It never becomes higher than T, and the blooming phenomenon is also suppressed.

After this, all vertical gate line voltages become V and all fully depleted dual-gate vertical JPETs are non-conducting, voltage φD becomes high voltage VH, and photodiode p
- Electrons are temporarily induced on the surface of the impurity layer 42, and the generation of dark current is suppressed (FIG. 3(a) t=tt).

When entering the horizontal scanning period, the horizontal switch 28-1゜28-
2 are sequentially opened and closed, and the signal charge read out to the horizontal signal line 30 is amplified by the amplifier 29 and output.

Note that the horizontal signal line 30 can be reset using the reset switch 3.
(This is done via

According to this embodiment, in addition to the effect of suppressing variations in pixel output due to the feedback capacitor, the photodiode is completely depleted at the time of reset, so no reset noise is generated, and the fully depleted photodiode is Since the surface is accumulated every horizontal scanning period,
Dark current can be reduced.

In this embodiment, the case of an n-channel JFET has been described, but the same applies to the case of a p-channel JFET. Further, an n-channel JFET may be formed in an n-well on a p-substrate, or a p-channel JFET may be formed in a p-well on an n-substrate.

Next, a second embodiment of the present invention will be described using FIGS. 4 to 6. FIG. 4 is a circuit configuration diagram of a solid-state image sensing device according to a second embodiment of the present invention, FIGS. This example shows the drive pulse timing for explaining the operation of the solid-state image sensor shown in Figure 4.
1988) pp. 646-652 (IEEE TRA
NSACTIONSON ELECTRON DEVI
The present invention is applied to the pixel amplification type solid-state image sensor described in CES Vol. 35 Na3 MAY 1988).

In FIG. 4, 2.3, 5.22 to 33 are the same as in FIG.
FET 52 is a gate capacitor that controls the gate voltage of the lateral JFET. Further, in FIG. 5, 53 is an n-type substrate, 54 is an n-type well, 55 is a photodiode p layer, and a lateral JFET is formed between the p-type substrate 53 and the pf layer 55. Further, 56 is polysilicon for wiring of the vertical gate line 32, and a gate capacitor 52 for gate voltage control is formed between the PT layers 55. 57 is a contact that becomes the drain of the horizontal JFET, 58 is the vertical signal line 33 and the feedback capacitor 2
A feedback capacitor 23 is formed between the 21 layer 55 and the polysilicon 58 using a light-transmitting thin film polysilicon which also serves as the upper electrode of the 21st layer 55 . The light utilization area in this embodiment is the area A in FIG. 3(a) because the wiring polysilicon 56 is non-transparent.

This coincides with the formation region of the feedback capacitor 23. Furthermore, the sixth
In the figure, each symbol is the same as that explained in FIG. 3(a). The operation of this embodiment is the same as that described in the above-mentioned document, except that the amplifier is composed of a capacitive feedback type amplifier, and φD is pulsed to set the amplifier to an appropriate bias point. A detailed explanation will be omitted. According to this embodiment, since the amplifier is of the capacitive feedback type, although the gate voltage control capacitor interacts with the photodiode storage capacitor, it does not affect the signal voltage at the time of signal readout, resulting in high uniformity. Signal output can be obtained.

In this embodiment, the case of an n-channel JFET has been described, but the same applies to the case of a p-channel.

Furthermore, a third embodiment of the solid-state imaging device according to the present invention will be described using FIGS. 7 and 8. FIG. 7 is a circuit configuration diagram of a solid-state image sensor according to the third embodiment, and FIGS. 8(a) and 8(b) are a plan configuration diagram and a cross-sectional configuration diagram of each pixel, respectively. It is constructed using bipolar transistors for each pixel element.

In FIG. 7, 2.3, 5.22 to 33 are the same components as in FIG. 1, 71 is a bipolar transistor serving as a driver of the inverting amplifier, and 72 is a gate for controlling the base voltage of the bipolar transistor. It is capacity.

- In FIG. 8, 73 is an n-type substrate, 74 is a p+ layer which becomes a photodiode, and 75 is polysilicon for wiring of the vertical gate line 32, and a gate capacitor 72 for base voltage control is formed between it and the p middle layer 74. has been done. Further, 76 is an NT layer that serves as the collector of the bipolar transistor, and 77 is a transparent thin film polysilicon that also serves as the vertical signal line 33 and the upper electrode of the feedback capacitor 23. A feedback capacitance is formed between the photodiode + layer 74 and the light-transmitting thin film polysilicon 77 connected to the NT layer 76 and the 01 layer, which serve as collectors.

On the other hand, the optical use area is the area A in FIG. 2A where the wiring polysilicon 76 is not formed above the photodiode 74, and coincides with the area where the feedback capacitance is formed. Also,
The drive pulse timing of this embodiment is the same as that shown in FIG. The operation of this embodiment is the same as that of the second embodiment (Figs. 4 and 5), except that the transistor provided for each pixel is changed from a JFET to a bipolar transistor, so it will not be explained here. omitted. In this embodiment as well, as in the second embodiment, a highly uniform signal output can be obtained despite the presence of gate capacitance.

In this embodiment, the case of an npn transistor has been described, but the same applies to the case of a pnph transistor.

In the above embodiments, an example of a two-dimensional solid-state image sensor has been described, but it goes without saying that the present invention is not limited to a two-dimensional solid-state image sensor, and can be easily implemented in a one-dimensional solid-state image sensor. Further, the present invention can be implemented regardless of the format of reading out the signal voltage from each pixel or the specific format of the inverting amplifier circuit.

In the above embodiments, thin film polysilicon was used as the electrode of the feedback capacitor.

However, if higher light transmittance is desired, it is also possible to form the upper electrode of the feedback capacitor with an impurity layer having a polarity opposite to that of the impurity layer forming the photodiode. Furthermore, a structure in which an impurity layer having a polarity opposite to that of the impurity layer forming the photodiode is formed above the photodiode is also effective in reducing dark current. However, in this case, since the impurity layer forming the feedback capacitance has the same polarity as the substrate, it is necessary to electrically isolate the feedback capacitance and the substrate. This method will be explained below using FIG. 9.

FIG. 9 is a diagram showing a cross-sectional structure at BB'B' of the same figure of an example in which the upper electrode is formed of an impurity layer of opposite polarity to the photodiode and the same polarity as the substrate in the pixel structure of FIG. 2. In the embodiment shown in FIG. 2(a), 41°42.44 is the same as in FIG. 2, and 91 is 07 which forms the upper electrode of the feedback capacitor.
It is a layer. The 19th layer 91 is formed so as to cover the entire area of the photodiode layer 42, and is connected to the wiring layer made of aluminum or the like of the vertical signal line at the contact portion 46 in FIG. 2(a). In the example, photodiode P″″[42
Even when the potential difference with respect to the substrate 41 is at its minimum, the n region of the photodiode isolation region (region D in the figure) is depleted, and the minimum value in the Y direction of the maximum potential in the X direction of the region is lower than the potential of the substrate 41. The n1 layer 91 is always small, so that the n1 layer 91 is electrically isolated from the substrate 41.

Furthermore, in the embodiment shown in FIG.
A field plate 9 is placed above the photodiode isolation region (area D in the figure) to ensure separation between
2 was established. A negative voltage is applied to the field plate 92 with respect to the substrate, and the minimum value of the maximum potential in the Y direction between the 01 layers 91 of different pixel elements is always lower than the lower voltage value of the voltages between the different NT layers 1. It has become. As a result, n
rlf91 are electrically isolated from each other.

Further, in the embodiment shown in FIG. 2(Q), n'N'll is formed in the inner part of the photodiode layer 42, and the n1 layer 91 is electrically isolated from the substrate 41 by the photodiode p-542. There is. At this time, the photodiode layer 4
A dark current is generated in the region where the n1 layer of No. 2 is not formed (region E in the figure). To prevent this problem, area E
A filled plate 92 is provided on top. A high voltage is applied to the field plate 92 during a predetermined period other than the signal readout period shown in FIG. 3(a), and electrons are temporarily induced on the surface of the photodiode layer 42, suppressing dark current. . Further, during the signal read period, a low voltage is applied, and the layer 9 operates so that the minimum voltage between the NF layer 91 and the N substrate 41 is always lower than the potential of the N substrate 41.
1 and n-substrate 41 are electrically isolated. Note that by using the field plate 92 as a mask and forming a p-layer and an n-middle layer, the structure shown in FIG. 12(c) can be easily realized.

Although one or more embodiments have been described using the structure of the pixel element shown in FIG. 2 as an example, the present invention can be implemented in the same manner with other pixel element structures. Further, although the case where the photodiode has p polarity has been described, the same applies to the case where the photodiode has n polarity. Also, when a p-type photodiode is formed between n-wells on a p-substrate,
The same applies when an n-type photodiode is formed in a p-well on an n-substrate. Furthermore, the embodiment shown in FIG. 9 is not limited to the method of forming the upper electrode of the feedback capacitance, and in order to reduce dark current, an impurity layer with the opposite polarity to the photodiode is formed above the photodiode, and the impurity layer is It can be implemented in all cases where electrical isolation from the substrate is required.

〔Effect of the invention〕

According to the present invention, the light utilization area of the amplifier input terminal provided in each pixel element, the storage capacitance, and the variations in characteristics of the transistors forming the amplifier are not affected.

Since uniform signal output can be obtained, there is an effect that high-quality reproduced images can be obtained.

In addition, the dark current generated on the impurity surface that forms the photoelectric conversion element can be reduced at the same time as the feedback capacitance required for the first invention is formed, so the dark current can be reduced while obtaining a uniform signal output. There is also this effect.

[Brief explanation of the drawing]

1, 4, and 7 are circuit configuration diagrams of the solid-state imaging device according to the present invention, and FIGS. 2, 5, and 8 are examples of the embodiments shown in FIGS. 1, 4, and 7, respectively. 3 and 6 are drive pulse timing diagrams of the embodiments of FIGS. 1 and 4, respectively, and FIG. 9 is a diagram of the drive pulse timing of the embodiment of FIG.
), and FIG. 10 is a cross-sectional structural diagram of a pixel element of a conventional solid-state image sensor. 21...Fully depleted dual gate vertical J FET2
2...Load MO823...Feedback capacitance 42...Photodiode p-impurity layer 45.58.77...Thin film polysilicon 51...Horizontal JFET 52.72
...Gate capacity 55.74...Photodiode-121
Layer 71...Bipolar transistor

Claims (1)

[Claims] 1. A pixel amplification type solid state having a photoelectric conversion section in which a plurality of pixel elements each consisting of a photoelectric conversion element and an amplification element that obtains an output corresponding to the signal charge of the photoelectric conversion element are formed on a semiconductor substrate. A solid-state image sensor, characterized in that an inverting amplifier circuit is constructed using the amplifying element, and each of the pixel elements is provided with a feedback capacitor for feeding back the output of the amplifying element to the photoelectric conversion element. 2. The solid-state imaging device according to claim 1, wherein the feedback capacitance is formed in substantially the same planar area as the area on the semiconductor substrate in which the photoelectric conversion element is formed. 3. In claim 1, the photoelectric conversion element is a low concentration impurity layer that is completely depleted at the time of reset, the feedback capacitor is configured with a MOS structure, and no signal is output to the terminal that serves as the output of the amplification element. A solid-state imaging device characterized in that a voltage is applied to the surface of the photoelectric conversion device for a predetermined period so that a carrier layer having a polarity opposite to that of impurities constituting the photoelectric conversion device is formed. 4. a semiconductor substrate made of a first impurity layer; a second impurity layer provided on the semiconductor substrate and having a polarity opposite to that of the substrate;
In a solid-state imaging device having a photoelectric conversion element comprising a third impurity layer covering the second impurity layer and having the same polarity as the substrate, the third impurity layer is formed between the semiconductor substrate and the second impurity layer. A solid-state imaging device characterized in that it is configured to be electrically isolated by a depletion layer. 5. a semiconductor substrate made of a first impurity layer; a second impurity layer provided on the semiconductor substrate and having a polarity opposite to that of the substrate;
A third impurity layer having the same polarity as the substrate provided on the second impurity layer.
In a solid-state imaging device having a photoelectric conversion element made of an impurity layer, the third impurity layer is separated from the substrate by the second impurity layer, and a predetermined period in which no signal is read out on the separated region. 1. A solid-state imaging device, comprising means for inducing a carrier layer having the same polarity as the substrate on the surface of the second impurity layer.