JP2865663B2 - Solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for realizing high sensitivity and low smear.
The present invention relates to a three-dimensional solid-state imaging device. [Prior art] Conventionally, MOS is a typical type of two-dimensional solid-state imaging device.
Type solid state imaging device is known "ISC Digest of Technical Papers (ISSC
C Digest of Technical Papers), p. 26, February 1, 1980
3 days". The above element has a circuit configuration as shown in FIG. In FIG. 4, 1 is a two-dimensionally arranged photodiode for performing photoelectric conversion, 2 is a vertical scanning circuit for selecting each row, 3 is a vertical gate line for guiding a selection signal from the vertical scanning circuit to each vertical switch, 4 is a vertical switch that opens and closes by a selection signal from the vertical scanning circuit, 5 is a horizontal scanning circuit that selects each row, 6 is a horizontal switch that opens and closes by a selection signal from the horizontal scanning circuit, 7 is an amplifier circuit outside the element, 8 is a vertical signal line, and 9 is a horizontal signal line. The above circuit performs the following operation. First, during the horizontal blanking period, the voltage of the vertical gate line 3 in the row selected by the vertical scanning circuit 2 increases, and the vertical switch 4 opens,
The signal charge is sent from the photodiode 1 to the vertical signal line 8. Thereafter, in the horizontal scanning period, the horizontal scanning circuit 5
Operates to sequentially open and close the horizontal switches 6, and the signal charges are sequentially amplified and output by the amplifier 7 outside the element. [Problems to be Solved by the Invention] In the above-mentioned prior art, the following two points are not considered, and the noise is large and the signal-to-noise ratio (hereinafter referred to as S / N ratio) is large.
Was low. KTC noise is generated by the thermal noise of the horizontal switch. Since the capacitance of the wiring portion serving as the input capacitance of the external amplifier is large, the signal voltage amplitude at the amplifier input terminal is small, and the pass band of the amplifier is wide, the noise of the amplifier is large. In addition, no consideration is given to the fact that an optical signal leaks into the vertical signal line during one horizontal scanning period, and when a bright subject is captured, vertical smear development occurs in which white tails appear above and below the reproduced image, resulting in high illuminance. This was a cause of image quality deterioration. On the other hand, there is a pixel amplification type element in which an amplifier is provided for each pixel. (For example, Ando et al .: Television Society, 1986
National Convention Proceedings 3-4, P51). In this device, the amplifier input capacitance becomes a photodiode capacitance and the signal voltage amplitude at the amplifier input terminal is large, so that amplifier noise can be reduced.
Further, since the signal voltage amplitude in the wiring increases, kTC noise generated during scanning can be reduced. As a result, low noise can be achieved. Further, vertical smear can be reduced for the same reason. However, in the pixel amplification type element, at least four elements are required for each pixel: a photodiode, a switch for resetting the photodiode, a switch for selecting each photodiode, and a transistor constituting an amplifier. As a result, it is difficult to increase the degree of integration.
An element having a sufficient number of pixels to conform to the method cannot be realized. Further, due to variations in the DC output level of the amplifier and the amplification gain for each pixel, a mottled fixed pattern noise was generated in the reproduced image. In order to solve these problems, a reset gate region and a floating gate region are arranged on the semiconductor surface, and a junction gate type FET (hereinafter a dual gate vertical JFET) having a channel region between these regions is arranged in each pixel. A fixed image pickup device is disclosed in Japanese Utility Model Publication No. 56-155565. An example of this type of solid-state imaging device will be described with reference to FIGS. FIG. 5 is a circuit configuration diagram of the solid-state imaging device, and shows a 3 × 3 case for simplicity. 6 (A) and 6 (B) are a sectional structure diagram and a circuit model diagram of the dual-gate vertical JFET of each pixel in FIG. 5, and FIG. 7 shows a drive pulse timing of the solid-state imaging device in FIG. 6 and 7 show the case of the n-channel, but in the case of the p-channel, the polarity may be reversed. In FIG. 5, 2, 3, 5, 6, 8, and 9 are the same as those in FIG. 4, 51 is a dual-gate vertical JFET serving as an inverter driver, 52 is an inverter load resistor, 53 is a bias power supply, and O
UT is an output terminal. FIG. 6 is a sectional view of a dual-gate vertical JFET constituting one pixel of FIG. Sixth
In FIG. 6A, 61 is an n-type substrate, 62 is a floating P-type impurity layer serving as a photodiode, 63 is a P-type impurity layer serving as a reset gate, 64 is an n ⁺ impurity layer for contact,
65 is an insulating layer, and 3, 52 and OUT are the same as in FIG. FIG. 2B shows a circuit model of the above cross-sectional view. A point node corresponding to the P-type impurity layer in FIG (A) 63, B point represents a node corresponding to the floating P-type impurity layer in FIG (A) 62, V _PT the figure (A) The punch-through voltage between 63 P-type impurity layers and 62 floating P-type impurity layers is shown. HBL in the drive pulse timing chart of FIG. 7 is a horizontal blanking period, and n rows are the nth row from the top in FIG.
The column indicates the m-th from the left, and the voltage is higher in the upper part of the figure. The operation of this circuit is described in “ISC Digest of Technical Papers, page 34, 1974, 2
On March 13). The operation is as follows. When the signal reading of n rows of a certain field is completed and the horizontal blanking period is started, the resetting of the floating P-type impurity layer 62 serving as the photodiode of n rows is performed. That is, the voltage of the vertical gate lines 3 of n row selected by the vertical scanning circuit 2 and 2 times the low reset voltage V _R of punch-through voltage V _PT of P-type impurity layer 62 and 63 (V _PT, V _R is a negative value). At this time, the potential of the P-type impurity layer 63 of each pixel in the n-th row is V _R
The floating P-type impurity layer 62 in the n-th row has a voltage of V _R −V _PT (V _PT ) due to the punch-through effect.
(FIG. 7 t = t ₁ ) Next, when the voltage of the vertical gate lines 3 in n rows is set to zero, n
Current flows from the zero potential and the P-type impurity layer 63 has decreased the line to floating P-type impurity layer 62, and finally floating P-type impurity layer 62 is reset to V _PT becomes potential, JFET
Becomes close to the threshold state regardless of the value of the punch-through voltage _VPT . (FIG. 7 t = t ₂ ) Then, the voltage of the vertical gate line 3 is changed to the punch-through voltage V
Light accumulation is performed while maintaining a voltage V _A (negative value) slightly lower than _PT . In other words, hit the light in floating P-type impurity layer 62 serving as a photodiode, discharge occurs in accordance with the amount, floating impurity layer 63 becomes a voltage higher than V _PT. However, the JFET does not become conductive. Further, now, when the strong light consider those Tatsuta state, by a punch-through effect, the potential of the floating P-type impurity layer 62 does not become higher than V _A -V _PT, blooming development is also suppressed. (FIG. 7 t = t ₃ ) In the horizontal scanning period of n rows of the next field, signal reading is performed. That is, n rows of vertical gate lines 3
When the potential of the P-type impurity layer 63 becomes zero and the voltage of the P-type impurity layer 63 becomes zero, the floating P-type impurity layer
In response to the voltage at 62, the JFET becomes conductive. In this state, when the selected horizontal switch is opened by the horizontal scanning circuit 5, the amplified photocurrent flows through the load resistor 52, and a signal voltage is generated at the output terminal OUT. In this conventional example, a photodiode, a switch for resetting a photodiode, a switch for selecting each photodiode, and a transistor constituting an amplifier are arranged on a semiconductor surface with a reset gate region and a floating region.
Dual gate JFET1 with a channel region between the regions
One is realized. For this reason, it is possible to realize a high degree of integration, which is the same as a conventional MOS element, although it is a pixel amplification type element.
Further, the reset level of the JFETs arranged two-dimensionally can be similarly close to the threshold state regardless of the variation of the punch-through voltage, and the fixed pattern noise can be reduced. However, since the reset level of each JFET is close to the threshold state, the current gain in the low illuminance region did not increase, and it was difficult to perform imaging in the low illuminance region. It is an object of the present invention to reduce the fixed pattern noise without complicating imaging in a low illuminance region in a pixel amplification type element using a dual-gate vertical JFET, and to achieve a high sensitivity, a low smear, and a high integration degree in two dimensions. An object of the present invention is to realize a solid-state imaging device. [Means for Solving the Problems] The object of the present invention is to provide a plurality of amplifiers each including a transistor having an input portion that accumulates photoelectrically converted signal charges and depletes at reset, and resets the input portion. In a solid-state imaging device having resetting means and horizontal scanning means for sequentially scanning outputs of a plurality of amplifiers in series on a single semiconductor substrate, the solid-state imaging device includes an input section for storing an amplifier at a first time when signal charges are accumulated. First output holding means for holding the output, second output holding means for holding the output of the amplifier at a second time after the input section has been reset, and second output holding means for holding the first output holding means. 1 and a second output holding means for performing a difference processing between the second output held by the second output holding means, wherein the first and second output holding means each have a vertical output terminal of the transistor. And horizontal scanning This is achieved by a solid state imaging device connected between the means. Here, when the transistor is a dual-gate JFET, a two-dimensional solid-state imaging device in which a reset gate region and a floating region serving as a photodiode are arranged, and a dual gate JFET having a channel region between these regions is arranged in each pixel. In the above, the floating region is formed of a low-concentration impurity layer. First, the output of each pixel when there is a signal charge is held, and then the output of each pixel when there is no signal charge after resetting the photodiode is held. After doing
This is achieved by providing a means for taking the difference between the two outputs for each column. [Function] The floating region formed by the low concentration impurity layer
At the time of reset, it does not become depleted and does not have a voltage higher than the punch-through voltage. Therefore, at the time of signal reading, the JFET is in a conductive state sufficiently higher than the threshold state,
Imaging does not become difficult even in the low illuminance region. Further, first, the output of each pixel when there is a signal charge in the floating area is held, and after that, the output of each pixel when there is no signal charge after the resetting of the floating area is held. A means to take the difference is provided. This makes it possible to cancel the variation in the DC output of the JFET and reduce the fixed pattern noise. Since the floating region serving as a photodiode is depleted, reset noise which is a problem in the case where the output is not depleted is not generated even if the output is held and the difference is obtained. Further, by providing the above means for each column, the above means can be realized without operating the circuit at high speed and without complicating the structure of the pixel portion. Embodiment One embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a circuit configuration diagram of a solid-state imaging device according to an embodiment of the present invention, and shows a 3 × 3 case for simplicity. 2A and 2B are a cross-sectional structure diagram and a circuit model diagram of a dual-gate vertical JFET of each pixel in FIG. 1, and FIG. 3 shows a drive pulse timing of the solid-state imaging device in FIG. In addition,
FIGS. 1 to 3 show the case where the JFET is a p-channel, but the same applies to the case of an n-channel. In FIG. 1, 2, 3, 5, 6, 8, and 9 are the same as in FIG.
1, 12 form a source follower for detecting a potential change of a photodiode, 11 is a p-channel dual gate vertical JFET as a driver, and 12 is a p-channel MO as a load.
It is an S transistor. 13-17 is "IEE
Solid State Circuits, SC14, (IEEE
Solid-State Circuits SC14) 961-969, December 1979
"Month", which constitutes an offset cancelled buffer. That is, 13 signal writing switch to the analog memory 15, 14 is the signal read switch, 16 Risetsutosuitsuchi, 17 buffer amplifier, O1, O2 output terminal, V _G denotes a bias voltage terminal of the load MOS 12. In FIG. 2A, 21 is a P-type substrate, 22 is a floating low-concentration n-type impurity layer serving as a photodiode, 23 is an n-type impurity layer serving as a reset gate, 24 is a wiring electrode of the vertical gate line 3, 25 Denotes a wiring electrode of the vertical signal line 8, 26 denotes a P ⁺ impurity layer for contact, and 65 denotes the same as in FIG. Further, in FIG. 4B showing the circuit model of the above sectional view, point C corresponds to the node corresponding to the n-type impurity layer 23 in FIG. 5A, and point D corresponds to the floating low-concentration n impurity layer 22. node, V _PT is a punch-through voltage between the n-type impurity layer 23 and the floating low concentration n-type impurity layer 22, V _PD denotes a depletion voltage for the P substrate 21 of the low-concentration n-type impurity layer. Here, V _PT is designed to be higher than V _PD (both V _PT and V _PD are positive values). HBL in the drive pulse timing chart of FIG. 3 indicates a horizontal blanking period, “n rows” indicates the nth row from the top in FIG. 1, “m columns” indicates the mth row from the left, and S1 to S3 indicate the first row. The voltage is higher in the upper part of the figure, corresponding to the symbol of each terminal in the figure. In the horizontal blanking period, first, the output voltage of each pixel when a signal is present is read. That is, the voltage of the vertical gate line 3 becomes zero and the n-type impurity layer
The voltage at 23 also becomes O, and according to the voltage of the floating low-concentration n-type impurity layer 22 changed according to the amount of light, the output voltage of the source follower using the dual-gate vertical JFET 11 as a driver and the P-channel MOS transistor 12 as a load Is determined. On the other hand, the reset switches 16-1 and 16-2 open, and the voltages at the input terminals of the buffer amplifiers 17-1 and 17-2 become the offset voltage of each buffer amplifier. Thereafter, the readout switch 13-1 is opened, and the output voltage of each pixel when a signal is present is held in the memory capacity 15-1. At this time, the vertical signal line voltage is equal to the output voltage of the selected source follower, and smear caused by leakage of an optical signal into the vertical signal line does not occur in principle. (FIG. 3 t = t ₁ ) Next, the resetting of the floating low-concentration n-type impurity layer 22 to be a photodiode is performed. That is, n
Punch-through voltage V _PT to floating low concentration n-type impurity layer 2 between the voltage of the row vertical gate lines of the n-type impurity layer 23 and 22
Reset voltage V higher than the sum of the depletion voltage V _PD of 2
_R (positive value). As a result, the floating low concentration n
-Type impurity layer 22 is depleted, the voltage becomes depleted voltage V _PD. At this time, n-type impurity layer by high reset voltage V _R
Needless to say, the impurity concentration of the n-type impurity layer is increased so that 23 does not become depleted. (FIG. 3 t = t ₂ ) Thereafter, the output voltage of each pixel when there is no signal charge after reset is read out. That is, when the voltage of the vertical gate line 3 becomes zero again, when there is no signal charge in each pixel, that is, when the floating low-concentration n-type impurity layer 22 is depleted,
It appears to Sosufuorowa output voltage vertical signal line 8 when the V _PD, open the switch 13-2 reads this voltage is held in the memory 15-2. (FIG. 3 t = t ₃ ) In the above operation, the depletion voltage V _PD is lower than the punch-through voltage V _PT , and the signal charge is floating.
The JFET is fully conductive even when it is not. Thereafter, when the reset switches 16-1 and 16-2 are idle and the horizontal scanning period starts, the horizontal switches 6-1 and 6-2 are sequentially opened by the horizontal scanning circuit 5, and the signals are output to the output terminals O1 and O2, respectively. The output voltage of each pixel, with and without, appears. By taking the difference between the two output terminals, it is possible to detect only the change in the output voltage of each pixel due to the signal charge regardless of the variation in the DC output of each pixel. Further, the change in the output voltage is substantially equal to the voltage change due to the signal charge of each photodiode because the amplifier constituting each pixel is a source follower. As a result, the variation in the voltage gain of the signal charge among the pixels can be reduced. On the other hand, the voltage of the n-row vertical gate line 3 is a voltage V slightly higher than the punch-through voltage _VPT.
The JFET kept at _A (positive value) does not enter a conductive state, and light is accumulated in the floating low-concentration n-type impurity layer 22. At this time, even if strong light is applied, the potential of the floating low-concentration n-type impurity layer 22 is reduced due to the punch-through effect.
It does not become lower than V _A -V _PT and blooming development is suppressed. (FIG. 2 t = t ₄ ) According to this embodiment, smearing and blooming development do not occur in principle. Further, since a buffer memory is provided for each column, high-speed operation is not required, each source follower band can be reduced, and amplifier noise can be further reduced as compared with a conventional amplifying element. Also, high integration is possible by using dual gate vertical JFET. Further, since each pixel is configured by the source follower, the voltage gain variation of the signal charge is small. A means for holding the output of each pixel when there is a signal charge, holding the output of each pixel when there is no signal charge after resetting the photodiode, and then taking the difference between the two outputs is provided. Canceling the variation in the DC output of the above, and providing the above means for each column and realizing the above means without causing the high-speed driving of the circuit, complicating the pixel structure, and generating reset noise,
If the input portion of the transistor (dual-gate vertical JFET in the above embodiment) in the pixel constituting the amplifier accumulates the photoelectrically converted signal charge and depletes at the time of resetting, the operation is performed regardless of the specific form of the input element. For example, the CMD (Ch) of a gate storage type MOS phototransistor described in “The Television Society, 1986 National Conference Proceedings 3-7, p57” can be used.
arge Modulating Device). Here, as described in the above document, the CM in the pixel constituting the amplifier is
The input portion of D is constituted by a potential well formed on the semiconductor surface below the gate electrode, and signal charges (holes) are accumulated in the potential well, and the potential well is depleted after resetting, so that reset noise is not generated. [Effects of the Invention] According to the present invention, even when there is no signal charge, the JFET constituting each pixel is in a conductive state sufficiently higher than the threshold state, and imaging is not difficult even in a low illuminance region. . Further, since the variation in the DC output voltage of each pixel can be canceled, the fixed pattern noise is reduced.
A three-dimensional solid-state imaging device can be realized.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit configuration diagram of one embodiment of the present invention, FIG. 2 (A)
(B) is a dual gate vertical type constituting each pixel of FIG.
FIG. 3 is a drive pulse timing chart of the solid-state imaging device of FIG. 1, FIG. 4 is a circuit configuration diagram of a conventional two-dimensional solid-state imaging device, and FIG. Circuit diagram of solid-state imaging device using JFET
5A and 5B are a cross-sectional structure diagram and a circuit model diagram of a dual-gate vertical JFET constituting each pixel of FIG. 5, and FIG. 7 is a drive pulse timing diagram of the solid-state imaging device of FIG. DESCRIPTION OF SYMBOLS 1 ... Photodiode, 2 ... Vertical scanning circuit, 3 ... Vertical gate line, 4 ... Vertical switch, 6 ... Horizontal switch, 8 ... Vertical signal line, 9 ... Horizontal signal line, 11 ... Dual gate Vertical JFET, 12 ... Source follower load, 13
…… Write switch, 14 …… Read switch, 15…
... Memory capacity, 16 ... Reset switch, 17 ... Buffer amplifier, 21 ... P-type substrate, 22 ... Floating n ^- type impurity layer, 23 ... N-type impurity layer, 24 ... Vertical gate line wiring electrode, 25: vertical signal line wiring electrode; 26: P + type impurity layer.

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Hideyuki Ono               1-280 Higashi Koigabo, Kokubunji-shi               Central Research Laboratory, Hitachi, Ltd. (72) Inventor Masaaki Nakai               1-280 Higashi Koigabo, Kokubunji-shi               Central Research Laboratory, Hitachi, Ltd.                (56) References JP-A-58-48578 (JP, A)                 JP-A-58-31670 (JP, A)                 JP-A-62-104074 (JP, A)                 JP-A-62-128679 (JP, A)

Claims (1)

(57) [Claims] A plurality of amplifiers each including a transistor having an input unit that accumulates photoelectrically converted signal charges and depletes at the time of reset, a reset unit that resets the input unit, and an output of the amplifiers connected in series. A first output holding means for holding an output of the amplifier at a first time when signal charges are stored in the input section, in a solid-state imaging device having horizontal scanning means for sequentially scanning on the same semiconductor substrate. A second output holding unit for holding an output of the amplifier at a second time after the input unit has been reset; a first output held by the first output holding unit; And a difference processing unit for performing a difference process with respect to the second output held by the output holding unit.
Wherein the output holding means is connected between each of the vertical output terminals of the transistor and the horizontal scanning means. 2. 2. The solid-state imaging device according to claim 1, wherein said transistor is a junction gate FET. 3. The input portion is a floating gate region having a first conductivity type of the junction gate FET, and the junction gate FET is a first gate region having the first conductivity type, the first gate region, and the first gate region. A channel of a second conductivity type opposite to the first conductivity type provided between the first gate region and the floating gate region; 3. The solid-state imaging device according to claim 2, wherein the voltage is lower than a punch-through voltage between the region and the region. 4. 4. The solid-state imaging device according to claim 3, wherein the first gate region and the floating gate region are provided on a surface of the semiconductor substrate exhibiting the second conductivity type. 5. 4. The device according to claim 3, wherein said junction gate type FETs are arranged in a matrix, and said floating gate region reads out said signal charges.
Item 5. The solid-state imaging device according to item 4. 6. 2. The solid-state imaging device according to claim 1, wherein said transistor is a CMD.