JPH02224518A - Cr oscillation circuit - Google Patents

Abstract

PURPOSE:To save power consumption and to obtain a stable oscillating frequency by fetching an output of a FF circuit with a MOS inverter, inverting the output, charging and discharging a capacitor and oscillating a CR oscillation circuit with the charging/discharging voltage. CONSTITUTION:When a capacitor 43 is charged and its level reaches a prescribed value, MOS 10a, 10c are operated and an input of a NOR gate 21 goes to a low level and its output goes to a high level. Thus, a FF 30 is set, a feedback signal FD is outputted and enters a gate of an inverter 40, a capacitor 43 is discharged by MOS 40a, 40b, when the level is descended up to a prescribed value, an output of an AND gate 22 goes to a high level by the MOS 10a, 10c, the FF is reset, the signal FD is outputted to recharge the capacitor 43. A charge/discharge voltage is fed to a MOS TR 10 through the repetition of operations above to generate the CR oscillation. Thus, the operation at a low voltage is attained, the power consumption is saved and a stable oscillating frequency is obtained.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a low power consumption CR oscillation circuit provided in an integration port '8 (hereinafter referred to as IC) of a CMO8 (complementary MOS transistor). It is.

(Prior Art) Conventionally, such fields include, for example, the one shown in FIG. The configuration will be explained below using figures.

FIG. 2 is a circuit diagram showing an example of the configuration of a conventional CR oscillation circuit.

This CR oscillation circuit consists of cascade-connected inverters 1.2
A time constant resistor 3 is connected in parallel to the inverter 1, and a time constant capacitor 4 is connected to the inverter 1.2.

This CR oscillation circuit operates as follows.

Electrical noise when power supply voltage VDD is applied is amplified by inverters 1 and 2, and part of the output thereof is fed back to inverter 1 via capacitor 4 in the form of feedback signal F. Capacitor 4 transfers the charging/discharging voltage at that time to inverter 1.
This circuit is made to oscillate by inputting . This C
The R oscillation circuit has the advantage of a simple circuit configuration.

However, in these various CR oscillation circuits, the power supply voltage VD
Not only is the oscillation frequency unstable because there is no means for correcting fluctuations in D, but also the through current flowing between the power supply voltage VDD and ground is large, making it impossible to drive at a low voltage.

Therefore, in order to solve these points,
Publication No. 9103 (hereinafter referred to as Document 1), and JP-A-5
A CR oscillation circuit described in Publication No. 8-63824 (hereinafter referred to as Document 2) has been proposed.

FIG. 3 is a circuit diagram of the CR oscillation circuit described in Document 1. This CR oscillation circuit has a Schmitt trigger circuit 11 consisting of bipolar transistors 1, 2, 3, 4, and a capacitor 6 and a resistor 8 for setting a time constant are connected to a node N1 on the input side, and The base of a feedback bipolar transistor 5 is connected to the node N2. The emitter of the bipolar transistor 5 is connected via a resistor 7 to a node N1 on the input side of the Schmitt trigger circuit 11, a capacitor 6, and a resistor 8, respectively.

Furthermore, bipolar transistors 9 and 10 are provided on the power supply voltage VDD side to take out the oscillation output OUT.

Next, the operation of this CR oscillation circuit will be explained.

First, when the charging current passing through the resistor 8 increases, the capacitor 6 increases its potential in proportion to the increase, and applies the high-level charging voltage to the node N1, which is the input side of the Schmitt trigger circuit 11. When this potential reaches the H level threshold voltage of the Schmitt trigger circuit 11, its output side node N2 becomes low level. Then, the bipolar transistor 5 turns off, and the capacitor 6 starts discharging, lowering its potential. When the potential reaches the L level threshold voltage of the Schmitt trigger circuit 11, the output node N2 of the Schmitt trigger circuit 11 is inverted and becomes high level. As a result, the capacitor starts charging again.

Oscillation is performed by repeating this charging and discharging. The power supply voltage VDD of this circuit only needs to be a voltage slightly higher than the input voltage of the Schmitt trigger circuit 11, and it oscillates stably even at a low voltage of 2 to 3 cm.

Further, FIG. 4 is a circuit diagram of the CR oscillation circuit described in Document 2. In this oscillation circuit, in order to stabilize the oscillation frequency, the resistance value is changed by the power supply voltage detection circuit 28 that detects the battery voltage of the power supply 29 and the detection signals 33, 34° 35 output from this power supply voltage detection circuit 28. A plurality of resistance value switching circuits 11, 12, and 13 are provided.

The resistance value switching circuits 11, 12, and 13 are connected in cascade between a plurality of inverters 14, 15, and 16 made of MOS transistors, respectively.
A plurality of time constant setting capacitors 17, 18, and 19 each having one end connected to the power supply voltage VDD are connected between each of the resistance value switching circuits 11, 12, and 5.16.

The power supply voltage detection circuit 28 of this CR oscillation circuit is connected to a power supply 29
The battery voltage is constantly detected, and a signal corresponding to the fluctuation in the battery voltage is sent to the resistance value switching circuit 11, 12, 13, and the resistance value switching circuit 11, 12, 13 changes the resistance value according to the fluctuation. It works to change. For example, when the battery voltage of the power supply 29 decreases, the oscillation frequency normally decreases, but in order to compensate for this, the oscillation frequency is stabilized by decreasing the resistance value by the length of the time constant.

(Problems to be Solved by the Invention) However, the CR oscillation circuit having the above configuration has the following problems. The CR oscillation circuit shown in Fig. 3 is constructed using bipolar transistors, but normally,
To drive a bipolar transistor, it is necessary to apply a voltage exceeding about 0.7 V between the base and emitter to cause a base current to flow. Therefore, when multiple stages of bipolar transistors are used, such as in a Schmitt trigger circuit, it is necessary to increase the drive current to make the output stronger and operate the next stage transistor appropriately.
This will consume current. In other words, it is difficult to operate this CR oscillation circuit with low power consumption. Further, in the circuit shown in FIG. 3, since the oscillation frequency is stabilized by analog control, there is a possibility that the oscillation frequency may become unstable if there are variations in the characteristics of the constituent elements.

In the CR oscillation circuit shown in Fig. 4, the voltage-driven element MOS
Since it uses transistors, it requires almost no current for driving and can operate with low power consumption. but,
This CR oscillation circuit has multiple resistance value switching circuits 11.12
．． 13, there is a risk that the inverter 14, 15, 16 cannot be driven properly due to a voltage drop, and it is difficult to operate it at a low voltage.

In any of the above CR oscillation circuits, the operating voltage is 1~
Low voltage type such as 1.5■ and power consumption of 1μW
It is not possible to stably oscillate both front and back, making it difficult to incorporate it into a high-precision integrated circuit that requires low voltage, low power consumption, and stable oscillation frequency.

The present invention provides a CR oscillation circuit which solves all the problems of the prior art, such as high operating voltage, difficulty in obtaining low power consumption, and unstable oscillation frequency.

(Means for Solving the Problems) In the first invention, in order to solve the above problems, at least one CR oscillation circuit, a CR oscillation circuit, a CR oscillation circuit, a CR oscillation circuit, a first resistor, and a CR oscillation circuit are provided.
a MOS transistor, a gate circuit for generating a set signal and a reset signal connected to both ends of the first resistor, a flip-flop circuit that is set by the set signal and reset by the reset signal, and a gate circuit for setting a time constant. It consists of a capacitor and a CMOS inverter whose input side is connected to the output of the flip-flop circuit 71 and whose output side is connected to the gate electrode of a CMOS transistor and the capacitor.

A second invention provides second and third electrodes in series with each drain electrode or each source electrode of the CMOS inverter.
This is a resistor connected.

(Function) In the first invention, since the CR oscillation is configured as described above, the 0MO8) transistor processes the input voltage digitally. The first resistor connected in series suppresses the through current flowing between the field effect transistor and the ground GND, and also serves to supply the necessary voltage to the gate circuit to properly operate the gate circuit. The gate circuit generates a set signal and a reset signal based on the voltage across the first resistor, and the flip-flow 11 circuit sets or resets the first output by inputting the set signal and reset signal, and sends the output to the CMOS inverter. Works like input. The CMOS inverter serves to charge or discharge the capacitor by taking the output of the flip-flop circuit and inverting the output. The capacitor supplies a charging/discharging voltage to the gate electrode of the CMO transistor 8) and functions to cause the CR oscillation circuit to oscillate.

In the second invention, since the second and third resistors are provided as described above, the second and third resistors work to suppress the on-resistance value of the CMOS inverter and reduce the circuit element area.

Therefore, the above problem can be solved.

(Embodiment) FIG. 1 is a circuit diagram of a CR oscillation circuit showing an embodiment of the present invention.

This CR oscillation circuit has a PMO810a and an NMO81 connected in series between the power supply voltage VDD and the ground GND.
A CMOS transistor 10 consisting of PMO
A load resistance resistor 11 is connected between the drain electrodes of 810a and NMO8IOb. A gate circuit 20 for generating a set signal 2O8 and a reset signal 2OR is connected to both ends of the resistor 11. The gate circuit 20 is
It has a two-manpower NOR gate 21 and a two-manpower AND gate 22, and the two manpowers of the NOR gate 21 and the AND gate 22 are connected to both ends of the resistor 11, respectively. NOR
The output of the gate 21 is connected to the set terminal of the flip-flop circuit 30 in the form of a set signal 20S, and the output of the AND gate 22 is connected to the reset terminal of the flip-flop circuit 30 in the form of a reset signal 2OR. This set/reset type flip-flow 71 circuit (hereinafter referred to as R8-F
The feedback signal FD, which is the output of the CMOS inverter 40, is connected to the gate electrode of a CMOS inverter 40. This frequency stabilizing CMOS inverter 40 has a PMO 840a and a PMO 840 connected between the power supply voltage VDD and the ground GND.
b, and time constant setting resistors 41 and 42 are connected to the source electrodes of the PMO 840a and PMO 340b, respectively. The drain electrode of this CMOS inverter is connected to the gate electrode of the CMOS transistor 10 and a time constant setting capacitor 43 whose one end is connected to the ground GND.

FIG. 5 is a waveform diagram of the charging and discharging voltage of the capacitor 43,
The operation of FIG. 1 will be explained with reference to this figure. In addition,
VTH is an H level threshold voltage of PMO 810a and PMO 810b, and VTL is an L level threshold voltage.

First, when current flows into the capacitor 43 through the resistor 41 and the PMO 840a, the potential of the capacitor 43 increases linearly as shown by waveform A. When this potential rises to the VTR, the PMO310a turns off and the PM
O310b turns on, the inputs of the NOR gates 21 each go to L level, and the output of this NOR gate 21 (set signal 20S) goes to H level. Therefore, R8-F
F30 is set and outputs an H level feedback signal FD.

Next, the H level feedback signal FD is applied to the CMOS inverter 4.
When input to the gate electrode of 0, PMO840a turns off,
The PMO 340b is turned on and the charge in the capacitor 43 is discharged via the PMO 840b and the resistor 42, so the potential of the capacitor 43 falls linearly as shown by waveform B. When this potential drops to VTL, PMO810
a is on, PMO310b is off, AND gate 22
The inputs of each become H level, and this AND gate 2
The output of No. 2 (reset signal 20R) becomes H level. Therefore, R8-FF30 is reset and outputs the feedback signal FD at L level.

When the L level feedback signal FD is input to the gate electrode of the CMOS inverter 40, the PMO 840a is turned on and the PMO
840b is turned off and the charge on capacitor 43 becomes PMO
Since the capacitor 43 is charged again via the capacitor 840a and the resistor 41, the potential of the capacitor 43 rises linearly again as shown by the waveform C. Thereafter, CR oscillation continues by repeating this process.

This embodiment has the following advantages.

(1) Transistor shown in Figure 1 (PMO810a.

40a, NMO810b, 40b) are all configured with CMO8, so in principle, the sum of the threshold voltages of PMO8 and NMOS transistors (0.5V + 0.5
It can operate at a low voltage of about IV, which is V).

(2) Resistors 11, 41, and 42 suppress the through current to a very low value (for example, 0.5 μA), so the current consumption for the entire circuit is about 1 μA, which is 1 μW (= 1 μAX I
Power consumption can be reduced to about V).

(3) Fig. 4 shows the output voltage waveform diagram when the power supply voltage VDD fluctuates, and Fig. 5 shows the oscillation frequency shown in Fig. 1 (
FIG. 3 is a comparison diagram between the conventional technique (F2) and the conventional technique (F2) of FIG. 2;

For example, as shown in FIG.
When increasing as, the threshold voltage VTR, VT
L and charge/discharge time t also increase accordingly, and V
TH8°VTLS, ts. However, feedback is applied by the action of the CMOS inverter 40 to which the feedback signal FD is input, and the rate of charging and discharging the capacitor 43 increases proportionally, so the oscillation frequency f (=1/1) cannot be maintained almost constant. , the results are shown in FIG. 5 as a computer simulation. As shown in Figure 5,
If the oscillation frequency can be maintained at around 30 kHz, the value of the capacitor 43 can also be made around pF, so it can be incorporated into the CMO8 IC.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. Examples of such modifications include the following.

(a) By increasing the on-resistance of the PMO 840a and the NMO 840b, the resistors 41 and 42 can be omitted, and thereby not only the same operation and effect as in the above embodiment can be obtained, but also the number of circuit elements can be reduced.

(b) The NOR gate 21 and AND gate 22 in FIG.
By wiring so as to apply feedback to the gate electrode of the inverter 40, for example, the NOR gate 21 can be used as a NAND gate, the AND gate 22 as an OR gate, the NOR gate 21 as an AND gate, and the AND gate 22 as a NOR gate. Can be replaced.

(c) R8-FF30 can also be configured with other flip-flop circuits such as JK-FF.

(Effects of the Invention) As explained in detail above, according to the first invention, since a transistor made of CMO3 with a low threshold voltage (approximately 0.5V) is used, a low voltage of 1 to 1.5V is used. Furthermore, since the first resistor suppresses the through current to a low value, power consumption can be reduced. Furthermore, since the output of this CRR oscillation circuit is fed back to the input side by a CMOS inverter, an oscillation frequency that is stable against fluctuations in power supply voltage can be obtained. Furthermore, the circuit configuration can be simplified because the analog effects of charging and discharging the capacitor are digitally processed using CMOS transistors, gate circuits, and flip-flop circuits. Therefore, it becomes possible to incorporate it into an integrated circuit that requires high precision, and it is possible to expect miniaturization and high reliability due to integration.

In the second invention, since the second and third resistors are provided, the second and third resistors suppress the on-resistance value of the CMOS inverter, so that the area of the circuit element can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a CRR swing circuit showing an embodiment of the present invention,
2 is a circuit diagram of a first conventional CRR oscillating circuit, FIG. 3 is a circuit diagram of a second conventional CRR oscillating circuit, FIG. 4 is a circuit diagram of a third conventional CRR oscillating circuit, and FIG. 6 is a diagram of the charging/discharging voltage waveform of the capacitor shown in FIG. 1, FIG. 6 is an output waveform diagram when the power supply voltage increases as shown in FIG. 1, and FIG. 7 is a comparison diagram of the oscillation frequency with the conventional one. 10...CMOS transistor, 11...
...First resistor, 20...Gate circuit, 30.
...Flip-flop circuit, 40...C
MOS inverter, VDD...Power supply voltage, GN
D...Ground, FD...Feedback signal,
OUT...Output voltage, 43...Capacitor, 2O8...Set signal, 2OR...
...Reset signal.

Claims (1)

[Claims] 1. A CMOS transistor in which a first resistor is connected in series; a gate circuit for generating a set signal and a reset signal connected to both ends of the first resistor; a flip-flop circuit that is reset by the reset signal, a time constant setting capacitor, and a CMOS inverter whose input side is connected to the output of the flip-flop circuit and whose output side is connected to the gate electrode of the CMOS transistor and the capacitor. A CR oscillation circuit characterized by comprising: 2. In the CR oscillation circuit according to claim 1, the CMO
A CR oscillation circuit in which second and third resistors are connected in series with each drain electrode or each source electrode of the S inverter.