JPH02224524A - Input buffer for semiconductor integrated device - Google Patents

Input buffer for semiconductor integrated device

Info

Publication number
JPH02224524A
JPH02224524A JP1046304A JP4630489A JPH02224524A JP H02224524 A JPH02224524 A JP H02224524A JP 1046304 A JP1046304 A JP 1046304A JP 4630489 A JP4630489 A JP 4630489A JP H02224524 A JPH02224524 A JP H02224524A
Authority
JP
Japan
Prior art keywords
resistor
buffer
input buffer
input terminal
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1046304A
Other languages
Japanese (ja)
Inventor
Sumio Shiotani
塩谷　純男
Tamotsu Kobayashi
保 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NEC Engineering Ltd
Original Assignee
NEC Corp
NEC Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC Engineering Ltd filed Critical NEC Corp
Priority to JP1046304A priority Critical patent/JPH02224524A/en
Publication of JPH02224524A publication Critical patent/JPH02224524A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electronic Switches (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To attain the design and manufacture when the buffer is not decided by connecting drains of P-channel and N-channel MOS transistor(TR) to the input terminal of a CMOS input buffer and connecting a power supply and ground to a source via a resistor. CONSTITUTION:A CMOS input buffer 1 connects to an input terminal 5 and the drains of a P-channel MOS TR 7 and an N-channel MOS TR 8. The source of the TR 7 is connected to a power supply 4 via a resistor 2, the source of the TR 8 is connected to a ground 4 via a resistor 3, and the bases of the TRs 7, 8 are connected to an input terminal 6. Thus, when a low level is applied to the terminal 6 the TR 7 is turned on and the TR 8 is turned off to form a buffer with pullup resistor. Moreover, when a high level is applied to the terminal 6, the TRs act like a buffer with a pulldown resistor conversely. Even when the buffer is not decided and requires the change, the design and manufacture are attained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積装置に関し、特に入力バッファに関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated device, and particularly to an input buffer.

〔従来の技術〕[Conventional technology]

第２図は従来のＰＵＬＬ−ＵＰ抵抗付き入力バッファで
あり、入力端子５が入力オープンの場合、入力バッファ
１の出力レベルはハイレベルになる。FIG. 2 shows a conventional input buffer with a PULL-UP resistor, and when input terminal 5 is open, the output level of input buffer 1 becomes high level.

２は抵抗、４は電源である。2 is a resistor, and 4 is a power supply.

第３図は従来のＰＵＬＬ−ＤＯＷＮ抵抗付抵抗力バッフ
ァであり、入力端子５が入力オープンの場合、入力バッ
ファ１の出力レベルはロウレベルになる。３は抵抗であ
る。FIG. 3 shows a conventional resistive buffer with a PULL-DOWN resistor, and when the input terminal 5 is open, the output level of the input buffer 1 becomes a low level. 3 is resistance.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の入力バッファは、ＰＵＬＬ−ＵＰ抵抗付
きまたはＦＵＬＬ−ＤＯＷＮＩ抗付きが決定しない場合
、設計・製造ができず、また半導体集積装置の評価時等
にＰＵＬＬ−ＵＰ　−ＰＵＬＬ−ＤＯＷＮを変更する必
要が生じた場合、再設計・再製造が行なわなければなら
ないという欠点を有していた。The conventional input buffer described above cannot be designed and manufactured unless it is determined whether it has a PULL-UP resistor or a FULL-DOWN resistor, and PULL-UP-PULL-DOWN cannot be changed when evaluating a semiconductor integrated device. It has the disadvantage that it must be redesigned and remanufactured if the need arises.

本発明の目的は前記課題を解決した半導体集積装置用入
力バッファを提供することにある。An object of the present invention is to provide an input buffer for a semiconductor integrated device that solves the above problems.

〔課題を解決するための手段〕[Means to solve the problem]

前記目的を達成するため、本発明に係る半導体装置用入
力バッファは半導体集積装置用ＣＭＯ３人カバツカバッ
ファ端子にＰ形ＭＯ３）ランジスタとＮＦＭＯＳトラン
ジスタのドレインを接続し、各トランジスタのソースに
抵抗を介してそれぞれ電源電極と接地電極を接続し、各
トランジスタのベースを互いに結線して外部入力端子に
接続したものである。In order to achieve the above object, the input buffer for a semiconductor device according to the present invention connects the drains of a P-type MO3) transistor and an NFMOS transistor to the CMO three-way capacitor buffer terminal for a semiconductor integrated device, and connects the drains of a P-type MO3 transistor and an NFMOS transistor to the source of each transistor through a resistor. A power supply electrode and a ground electrode are connected to each other, and the bases of each transistor are connected to each other and connected to an external input terminal.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する、第１図
は本発明の一実施例を示す回路図である。Next, the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing one embodiment of the present invention.

図において、ＣＭＯ３人カバツカバッファ１端子５にｆ
ｉ続され、更にＰｉＭＯ３）ランジスタフとＮ形ＭｏＳ
トランジスタ８のドレインを接続している。Ｐ形ＭＯＳ
トランジスタ７のソースは抵抗２を介して電源４に接続
され、Ｎ形ＭＯＳトランジスタ８のソースは抵抗３を介
して接地電極に接続されている。また、Ｐ形ＭＯＳトラ
ンジスタ７とＮ形ＭＯＳトランジスタ８のベースを互い
に結線したう元で外部入力端子６に接続されている。In the figure, f
i is continued and further PiMO3) Langistav and N-type MoS
The drain of transistor 8 is connected. P-type MOS
The source of the transistor 7 is connected to the power supply 4 via the resistor 2, and the source of the N-type MOS transistor 8 is connected to the ground electrode via the resistor 3. Further, the bases of the P-type MOS transistor 7 and the N-type MOS transistor 8 are connected to the external input terminal 6 through the wires connected to each other.

従って、外部入力端子６にロウレベルを印加した場合、
Ｐ形ＭＯＳトランジスタ７はＯＮ状態になり、Ｎ形ＭＯ
Ｓトランジスタ８はＯＦＦ状態になるため、ＦＵＬＬ−
ＵＰ抵抗付き入力バッファになり、外部入力端子６にハ
イレベルを印加した場合、Ｐ形ＭｏＳトランジスタ７は
ＯＦＦ状態になり、Ｎ形ＭＯ３）ランジスタ８はＯＮ状
態になるため、ＰＵＬＬ−ＤＯＷＮ抵抗付抵抗力バッフ
Ｔになる。Therefore, when applying a low level to external input terminal 6,
P-type MOS transistor 7 is turned on, and N-type MOS transistor 7 is turned on.
Since the S transistor 8 is in the OFF state, the FULL-
When the input buffer becomes an input buffer with a UP resistor and a high level is applied to the external input terminal 6, the P-type MoS transistor 7 is turned off and the N-type MOS transistor 8 is turned on. It becomes a power buff T.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、外部入力端子にロウレベ
ルまたはハイレベルを印加することにより、ＰｔＪＬＬ
−１ＪＰ抵抗付き入力バッファまたはＰＵＬＬ−ＤＯＷ
Ｎ抵抗付抵抗力バッファに変えることができるという効
果がある。そのため、ＰＵＬＬ−ＵＰ抵抗付きまたはＦ
ＵＬＬ−ＤＯＷＮ抵抗付抵抗力定しない場合にも設計・
製造ができ、また半導体集積装置の評価時等にＰＵＬＬ
−ＵＰ・ＰＵＬＬ−ＤＯＷＮを変更する必要が生じた場
合でも再設計・再製造が不要になる。As explained above, in the present invention, by applying a low level or a high level to the external input terminal, the PtJLL
Input buffer with -1JP resistor or PULL-DOW
It has the advantage that it can be changed to a resistive buffer with N resistance. Therefore, with PULL-UP resistor or F
Designed with ULL-DOWN resistor even when resistance force is not fixed.
It can be manufactured, and it can also be used for PULL when evaluating semiconductor integrated devices.
- Even if it becomes necessary to change UP/PULL/DOWN, redesign and remanufacturing are not required.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例を示す回路図、第２図は従来
のＰｔＪＬＬ−１ＪＰ抵抗付き入力バッファを示す回路
図、第３図は従来のＰＵＬＬ−ＤＯＷＮ抵抗付抵抗力バ
ッファを示す回路図である。 １・・・ＣＭＯＳ入力バ ッファ・・・抵抗　　　　　４・・・電源５〜６・・・
外部入力端子 ７・・・Ｐ形ＭＯＳトランジスタ ８・・・Ｎ形ＭＯＳトランジスタFig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a circuit diagram showing a conventional input buffer with PtJLL-1JP resistor, and Fig. 3 is a circuit diagram showing a conventional resistive buffer with PULL-DOWN resistor. It is a diagram. 1...CMOS input buffer...Resistor 4...Power supply 5-6...
External input terminal 7...P-type MOS transistor 8...N-type MOS transistor

Claims (1)

【特許請求の範囲】[Claims] （１）半導体集積装置用ＣＭＯＳ入力バッファの入力端
子にＰ形ＭＯＳトランジスタとＮ形ＭＯＳトランジスタ
のドレインを接続し、各トランジスタのソースに抵抗を
介してそれぞれ電源電極と接地電極を接続し、各トラン
ジスタのベースを互いに結線して外部入力端子に接続し
たことを特徴とする半導体集積装置用入力バッファ。(1) Connect the drains of a P-type MOS transistor and an N-type MOS transistor to the input terminal of a CMOS input buffer for semiconductor integrated devices, connect the power supply electrode and the ground electrode to the source of each transistor via a resistor, and An input buffer for a semiconductor integrated device, characterized in that the bases of the two are connected to each other and connected to an external input terminal.
JP1046304A 1989-02-27 1989-02-27 Input buffer for semiconductor integrated device Pending JPH02224524A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1046304A JPH02224524A (en) 1989-02-27 1989-02-27 Input buffer for semiconductor integrated device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1046304A JPH02224524A (en) 1989-02-27 1989-02-27 Input buffer for semiconductor integrated device

Publications (1)

Publication Number Publication Date
JPH02224524A true JPH02224524A (en) 1990-09-06

Family

ID=12743454

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1046304A Pending JPH02224524A (en) 1989-02-27 1989-02-27 Input buffer for semiconductor integrated device

Country Status (1)

Country Link
JP (1) JPH02224524A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03212021A (en) * 1990-01-17 1991-09-17 Matsushita Electric Ind Co Ltd Input buffer circuit
JPH04266217A (en) * 1991-02-21 1992-09-22 Matsushita Electric Ind Co Ltd input buffer circuit
DE19545940C2 (en) * 1994-12-15 2000-01-20 Mitsubishi Electric Corp Semiconductor device
JP2009055656A (en) * 2007-08-23 2009-03-12 Toshiba Schneider Inverter Corp Inverter

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03212021A (en) * 1990-01-17 1991-09-17 Matsushita Electric Ind Co Ltd Input buffer circuit
JPH04266217A (en) * 1991-02-21 1992-09-22 Matsushita Electric Ind Co Ltd input buffer circuit
DE19545940C2 (en) * 1994-12-15 2000-01-20 Mitsubishi Electric Corp Semiconductor device
JP2009055656A (en) * 2007-08-23 2009-03-12 Toshiba Schneider Inverter Corp Inverter

Similar Documents

Publication Publication Date Title
JP3038094B2 (en) Output circuit of semiconductor integrated circuit device
JPH011200A (en) semiconductor integrated circuit
US20070268065A1 (en) Transistor Switch with Integral Body Connection to Prevent Latchup
JPH11103227A (en) Output amplitude adjusting circuit
JP2968653B2 (en) Output circuit
JP3636848B2 (en) CMOS hysteresis circuit
JPS5928986B2 (en) semiconductor integrated circuit
JPH03132115A (en) Semiconductor integrated circuit
JPH0685497B2 (en) Semiconductor integrated circuit
JPH0583104A (en) Semiconductor integrated circuit
JPH0563943B2 (en)
JPH03123219A (en) Semiconductor integrated circuit
JPS62194736A (en) Semiconductor integrated circuit
JPH0355912A (en) Hysteresis circuit
JP2595074B2 (en) Semiconductor integrated circuit device
JPS6318719A (en) Input buffer circuit
JPH0541494A (en) Semiconductor integrated circuit
JP2541289B2 (en) Output circuit
JPH0357316A (en) Pull-up/pull-down input circuit
JP2808784B2 (en) Input circuit
JP2712432B2 (en) Majority logic
JP2754673B2 (en) ECL-TTL level conversion circuit
JPS59121512A (en) Mos power breaking circuit
JPH03190422A (en) Input circuit
JPH02301326A (en) Input circuit for semiconductor integrated circuit