JPH02224525A - Counter circuit - Google Patents

Abstract

PURPOSE:To attain high speed calculation even in the case of the occurrence of multi-bit by dividing high-order and low-order bits of the result of address increment, detecting the occurrence of carry at the low-order bit and informing the result to the high-order bit. CONSTITUTION:Let the increment of an address be 1, the level of a control signal C1 goes to 1 and a transistor(TR) 43 of an AND circuit stacked laterally using the low-order 16-bit of the address as FFFEH is turned on. Then, the outputs of an AND gate 67 and an OR gate 70 are logic '0', carry input circuit 23 is not turned on and no carry is outputted. When the address is incremented to be FFFFH, TRs of the AND circuit are all turned off and the output goes to logic '1'. Since the signal C1 and the gates 67, 70 are logic '1', the circuit 23 is turned on and a carry is outputted. Thus, the low-order bit detects the occurrence of the carry, and informs it to the high-order bit to attain high speed calculation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a counter circuit suitable for a high-speed address incrementer.

[Prior Art] Conventionally, for example, DMA (Direct Mem
oryAccess) An address incrementer is used to continuously increment the address during transfer.

In recent years, advances have been made in expanding memory areas, increasing the number of bus cycles to two clocks, and increasing the speed of the bus cycle. This has led to a demand for increasing the number of address bits and increasing the speed of the address incrementer.

[Problem to be solved by the invention] However, in the conventional address incrementer described above,
For example, when incrementing a multi-bit address such as 32 bits using a high frequency clock signal, there is a problem in that the propagation time of a carry occurring over a large number of bits cannot keep up with the clock cycle, resulting in the output of an incorrect address.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a counter circuit that can generate addresses without errors in a multi-bit, high-speed address incrementer.

[Means for Solving the Problems] A counter circuit according to the present invention detects that the output on the lower bit side of the incrementer is an output pattern that causes a carry to occur on the upper bit side in the next increment,
It is characterized by having a carry lookahead circuit that generates a carry signal on the upper bit side.

[Operation] According to the present invention, the carry lookahead circuit monitors the output on the lower bit side of the incrementer, and if the output pattern is such that an output carry is generated that causes a carry to be generated on the upper bit side in the next increment, this Since it detects this in advance and generates a carry signal to the upper bit side, even when a carry occurs over multiple bits,
A carry to the upper bit side can be generated in advance by prior detection, and address increment can be made faster.

[Example] Next, an example of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of a counter circuit according to a first embodiment of the present invention.

This counter circuit is applied to a 32-bit address incrementer, and the bit cells 11, 12, 13, 14, 15 that make up the address incrementer are used for the LSB, 2nd bit, 3rd bit, and 15th bit in this order. and the 16th bit to MSB are shown, respectively.

A carry line 16 connecting each bit cell 11 to 15.
17, 18, and 19 are carry input circuits 20, 2, respectively.
1, 22, and 23 are connected.

These carry input circuits 20 to 23 receive carry signals C1, C2, C3, . . . in synchronization with the clock signal φ.
・ is entered. For example, if the number of increments is 1
In this case, if the number of 1° increments of the carry signal C1 is 2, the carry signal C2 is 1. If the number of increments is 4, carry signal C3 is set to 1.

Bit cells 11 to 15 are lower bits and bit cells 1
It is divided into bit cells 1 to 14 and upper 16 bits, and a carry lookahead circuit is connected to the lower 16 bits. That is, each bit cell 11
, 12, 13, and 14 are outputted from inverters 24, 27,
Bit line 36.37.38.3 before 29.31 respectively
Connected to 9. The gate of an N-channel transistor 42 is connected to the bit line 36, and the N-channel transistor 42 is connected to the bit line 37.
The gates of channel transistors 43 and 44 are connected to each other, and N-channel transistors 45 and 46 are connected to the bit line 38.
．． 47 are connected to each other, and each gate of an N-channel transistor 48°49.50 is connected to the bit line 39. And transistors 42.43, 45.4
The drains of the transistors 8 are connected in common, and a P-channel transistor 41 for precharging is connected to the drains, thereby forming a horizontally stacked AND circuit. Similarly,
The drains of the transistors 44, 46, and 49 are commonly connected, and together with the precharging transistor 51, they form a horizontally stacked AND circuit, and the transistors 47, 50, and 52 form a horizontally stacked AND circuit.

The output of these horizontally stacked logic circuits is the transfer gate 5
3.54, 55, buffer 56.57°58, transfer gate 61, 62.63 and buffer 64, 65.
66 and are input to one input terminal of each AND gate 67, 68, and 69. Also, this AND game)
Carry human power signals C1, C2, and C3 are input to the other input terminals of 67.68° and 69, respectively. and,
The outputs of these AND gates 67, 68, and 69 are logically summed by an OR gate 70, and the logical sum output is given to the carry input circuit 23 as a carry input signal on the upper bit side.

Next, the operation of the counter circuit of this embodiment configured as described above will be explained.

Now, if the address increment is 1, the control signal C1 becomes 1, and the other control signals C2 and C3 become 0. Also, if the lower 16 bits of the current address are FFFEH,
Of the horizontally stacked AND circuit, the N-channel transistor 42
is turned on, so one input of the AND gate 67 is
is given.

Therefore, the output of the AND gate becomes O. Moreover, the control signals C1, C2, and C3 are 1. Since O, O, A
ND gates 68 and 69 are both 0, OR gate 70
The output of will be 0. Therefore, the carry input circuit 23 is not turned on, and no carry is output to the upper 16 bits.

Next, when the address incrementer is incremented, the lower 16 bits become FFFFFH.

In this case, all the N-channel transistors constituting the horizontally stacked AND circuit are turned off, so the drains of these N-channel transistors are connected to the P-channel transistor 41.
．． 51. The Lebel charge precharged by 52 remains. Therefore, the output of the horizontally stacked AND circuit is all 1
becomes.

Further, since the control signal C1 is 1, the output of the AND gate 67 is 1, and the output of the OR gate 70 is also 1. Therefore, in this case, the carry input circuit 23 is turned on, the data of the lower 16 bits is reflected on the carry line 19 of the upper 16 bits, and a carry is output without waiting for the next increment operation.

In addition, in the above explanation, the increment of the address is assumed to be 1, but
If the address increment is 2 (control signal C2 is 1, C1
, C3 are 0), the output of the AND gate 68 becomes 1 when all of the lower 16 bits from the output of the bit cell 12 of the second bit to the output of the bit cell 14 of the 15th bit become 1.

Also, when the address increment is 4 (control signal C3 is 1
, C1, C2 are 0), similarly, when the output of the bit cell 13 for the third bit and the output of the bit cell 14 for the 15th bit all become 1, the output of the AND gate 69 becomes 1. In this way, by appropriately selecting the control signals C1, C2, and C3 according to the magnitude of the increment, it is possible to pre-read the carry of the lower bits.

FIG. 2 is a circuit showing a second embodiment of the present invention.

In this embodiment, even when the address increment is 3, it is possible to read ahead the carry, and OR gates 81 and 82 are newly added to the input side of the carry input circuit 20 and 21, and AND gates 83.85 and OR gates 84.86 are newly provided as circuits for detecting the output of the logic circuit. The other parts are the same as the configuration described in the previous embodiment.

In this circuit, when there is an address increment of 3, the control signal C4 becomes 1. In this case, the carry is output from the lower bit to the upper bit because the lower bits are FFFFEH and FFFDo, so these two values must be detected. However, FFFE)
I has already been detected by the carry input circuit 23 when incrementing by one. Also, F F F D n
is the output of buffer 66 when incrementing by 4 and 0
Since it is determined by ANDing the bit result with the output of the inverter 26, it can be detected by the AND gate 83. Therefore, 3 increments can be determined by OR gate 84. By ANDing the output of the OR gate 84 and the 3-increment control signal C4 using an AND gate 85, it is possible to detect whether or not a carry appears in the upper 16 bits.

[Effects of the Invention] As explained above, the present invention separates the upper bit side and the lower bit side of the address increment, detects in advance the occurrence of a carry on the lower bit side, and notifies the upper bit side. Even when carries are propagated the most, only the number of bits on the lower bit side is sufficient, making high-speed calculation possible.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a counter circuit according to a first embodiment of the invention, and FIG. 2 is a circuit diagram of a counter circuit according to a second embodiment of the invention.

Claims (1)

[Claims] (1) Features include a carry look-ahead circuit that detects that the output on the lower bit side of the incrementer is an output pattern that generates a carry to the upper bit side in the next increment, and generates a carry signal on the upper bit side. counter circuit.