JPH0222473B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention The present invention relates to an integrated circuit memory, and more particularly to an integrated circuit memory having an additional bypass circuit for outputting input data directly to an output terminal.

2. Prior Art FIG. 1 is a block diagram of a conventional integrated circuit memory, which is composed of a 2 ⁿ word×1 bit memory cell 1, an address decoder 2, a read/write circuit 3, an AND gate 4, etc. To briefly explain the operation of this, first, in order to select the entire semiconductor memory within the broken line, set the chip select to low level and apply addresses A ₁ to A _o , the decoder 2
One bit in the memory cell 1 is selected via the .
At this time, when the write signal is at a high level, that is, in a read state, it appears at the output terminal DO via the read/write circuit 3 of the selected cell. When writing, give the write data to the data input terminal DI,
When WE is set to low level, that is, in the write state,
Information is written into the selected cell via the read/write circuit 3. After writing, when is set to high level, the information is read to the output terminal DO.
The above is the general operation of high-speed bipolar memory, and no particular inconvenience occurs in normal usage.

By the way, in computer systems, in order to speed up processing, a high-speed buffer storage (BS) that stores a copy of the main memory is generally provided in the processing unit, and the processing unit responds to memory reference requests.
A method is used to obtain desired information from the BS. In this case, if the desired information is not in the BS, there is a request to transfer data from the main memory and write it into the BS, and at the same time to use the data. However, as for the operation of the memory in Figure 1,
Writing and reading cannot be performed at the same time. For this reason, when the memory shown in FIG. 1 is used as a BS, the configuration shown in FIG. 2 has conventionally been adopted.

FIG. 2 is a block diagram of part of a buffer storage (BS) and next stage read data register section using the semiconductor memory of FIG. 1. Book BS
20 is a memory device having a capacity of ²ⁿ words×m bits and using m memories 10 shown in FIG. This B.S.
When reading data from 20, m output data lines DO1 to DOm are read by applying an address.
Data is read from the buffer data register (BDR) of the read data register section 21 in the next stage.
22. When writing data into BS20, apply the address in the same way as when reading,
Data on m input data lines (DI1 to DIm)
Write in BS. On the other hand, due to the nature of the BS, the data that the computer attempts to process is not always within the BS. If the desired data does not exist in the BS 20, the data must be transferred from the main storage device to the BS 20, and at the same time as being written, the data must be sent to the next stage read data register unit 21 for processing. In Figure 2, this path is from DI1 to DIm
Buffer write data register (BWR) 2
3, and will eventually enter the BDR 22 in the same way as the read data from the BS 20.

However, the drawback of the configuration shown in Figure 2 is that in addition to the integrated circuit memory, BS20 also has BWR2 from DI1 to DIm.
Since three routes are required, the amount of hardware and wiring is essentially large. In particular, when the read data register section 21 is implemented as an LSI, paths for both the BS read data and the read data from the main memory are required as inputs, and a large number of input pins are used. Therefore, the ratio of the number of internal gates of the LSI to the number of input/output pins of the LSI (gate/pin ratio) decreases. Generally, in order to realize a high-density LSI, it is necessary to improve the gate/pin ratio, and from this point of view, it can be said that the configuration shown in FIG. 2 is not suitable for LSI.

On the other hand, if we focus only on the number of wires, the amount of wires will not be large if the input pins and output pins of the memory element are used in common. This type of memory already exists in MOS type semiconductor memory, but since the output and input are directly connected, the input load capacitance is also included as an output load, resulting in a large load and cannot be used for high-speed applications. . Also, when output from memory is enabled,
Unable to apply input signal.

OBJECT OF THE INVENTION The purpose of the present invention is to eliminate the above-mentioned conventional problems, and at the same time as input data is written into the memory, the data is also retrieved from the output side of the memory, so that it can be read as if it were from the memory. An object of the present invention is to provide an integrated circuit memory that can be used for data purposes and that input capacitance does not become an output load.

General Description of the Invention A feature of the present invention is that while input data is given to the memory to perform a write operation, the input data is outputted from the output side through a logic circuit, and at this time, the signal from the memory cell is This is to control so that it does not appear on the output side.

Embodiment of the Invention FIG. 3 shows an embodiment of an integrated circuit memory according to the present invention. Here, 10 is the same ²ⁿ word x 1 bit memory as explained in FIG. 1, but the difference from FIG. 1 is that in addition to logic circuit 4, logic circuits 5 and 6
and 7 were added. Logic circuits 4 and 5
is a NAND gate whose low level is “1”,
6 is a buffer gate that creates "1" or "0" for the input, and 7 is an inverter for polarity reversal. Also, 8 connects the outputs of logic circuits 4 and 5, and in terms of logic function, high level is "1".
It is an OR gate (wired OR). Since the basic functions of this memory 10 are the same as those shown in FIG. 1, their explanation will be omitted, and the following description will focus on the parts added according to the present invention.

First, when the signal is at a low level and the signal is at a high level, the read state is entered, and at this time, one of the logic circuits 4 and 5 is opened depending on the state of the DSEL signal. For example, when the DSEL signal is at a low level, the logic circuit 4 is opened and the contents of the memory cell 1 are output through the read/write circuit 3 to the DO terminal. This is a normal read operation.
When the DSEL signal is at a high level, the logic circuit 5 is opened and the signal at the DI terminal appears at the DO terminal.

Next, when the signal is at a low level and the signal is also at a low level, the memory 1 enters the write state. In this case, the signal at the DI terminal is first written into the memory cell. On the other hand, since is at low level, it depends on the state of the DSEL signal, as in the case of reading.
It is decided whether to extract the DI signal or the contents of memory 1 to the DO terminal. When the DSEL signal is high, the logic circuit 5 is opened and the input signal is taken out as is at the DO terminal. That is, simultaneously with the write operation, the data currently being written is output from the output terminal.

FIG. 4 shows the semiconductor memory of FIG. 3 according to the present invention.
This is a block diagram of the BS used individually. Functionally,
This is similar to FIG. 2 using a conventional memory, but the BWR 23 in FIG. 2 is eliminated, and the m data lines from DI that enter the read data register section 21 are no longer necessary. Instead, one DSEL terminal is added to BS20.

Effects of the Invention With the configuration as described above, the following effects can be obtained with the present invention.

(1) By adding a logic circuit that bypasses input data to the output side and a control signal to control it, input data can be used simultaneously as output data regardless of write and read operations.

(2) Since the input and output are separated by a logic circuit, the input capacitance does not become a load on the output.

(3) When the BS read data register section is implemented as an LSI, it is possible to improve the gate/pin ratio of the LSI without reducing the BS read speed (access time).

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional integrated circuit memory.
FIG. 2 is a block diagram of buffer storage and peripherals using the integrated circuit memory of FIG. 1, FIG. 3 is a block diagram of an embodiment of the integrated circuit memory of the present invention, and FIG. 4 is a block diagram of the integrated circuit of the present invention. FIG. 2 is a block diagram of buffer storage using memory and peripherals. DESCRIPTION OF SYMBOLS 1... Memory cell, 2... Decoder, 3... Read/write circuit, 4, 5, 6, 7... Logic circuit, 8... Wired OR circuit.

Claims (1)

[Claims] 1. In an integrated circuit memory equipped with a write data input terminal, a storage circuit, and a read data output terminal, a logic circuit that connects the write data input terminal and the read data output terminal, and a logic circuit that controls the logic circuit. A control signal terminal is added to apply a control signal for the control signal, and depending on the state of the control signal applied to the control signal terminal, the data at the write data input terminal is written to the storage circuit, and at the same time, the data is written through the logic circuit. An integrated circuit memory characterized in that the read data output terminal is bypassed.