JPH02226076A - Apparatus for monitor dynamic burn in test of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce cost for burn in test (BT) by a method wherein semiconductor integrated circuit devices (ICs) and an IC to be tested (DUT) are set in the test mode, synchronization is performed by operation at a clock level and the output signal of good ICs and the output signal from the DUT are compared with one another. CONSTITUTION:Good ICs 7 are mounted on a driver board 2 and these ICs 7 and a DUT 21 are set in the test mode. Then while synchronizing operation at a clock level, instruction codes for operating internal circuits of these ICs 7 and the DUT 21 are read out from memories 5, 6, the output signal from a synchronization circuit and the output signals from the memories 5, 6 are selected to be supplied to a driver unit 9, and the output signals from the good ICs 7 and the output signal from the DUT 21 are compared with one another to identify whether the DUT is good. This allows monitor dynamic BT at low cost and easily.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a dynamic burn-in test device (hereinafter referred to as a BT device) for monitoring semiconductor integrated circuit devices (hereinafter referred to as Ic), and is particularly applicable to microcomputers. This invention relates to an IC monitor dynamic BT device.

[Prior art] A BT device is a DtJT device that processes an IC under test (hereinafter referred to as DtJT) by applying power supply voltage and signals in a high-temperature furnace.
This is a device for accelerating the deterioration of the characteristics of the UT and removing initial defects of the DUT. In particular, by applying a signal to the DUT and
Performing a burn-in test (hereinafter referred to as BT) while operating the circuit inside the UT is called dynamic BT, and the device is called a dynamic BT device. Further, a device capable of observing (monitoring) the output signal of a DUT during dynamic BT and determining whether or not the DUT is operating properly is called a monitor dynamic BT device.

Figures 3, 4, and 5 are conventional monitor dynamic B
An overview of the T device is shown, and FIGS. 4 and 5 are schematic diagrams of the control board and driver board in FIG. 3, respectively. Third
In the figures, 20゛1 is the main control section, 203 is the control section, 204 is the address generation section, 205 is the pattern memory, 209 is the driver section, 210 is the determination section, 221 is the DUT, 212 .222, 232 and 232' are signal buses, 250 is a control board, 251 and 252 are cables, 253 is a driver board, 254.256.256'
and 257 are connectors, and 255 is a BT board. The right side of the broken line B-B is the inside of the BT furnace, and the left side is the BT control side that supplies power voltage, signals, etc. to the BT board 255 in the BT furnace.

The control board 250 in FIG.
Information such as the power supply voltage and signals to be applied to the BT board 2δ5 is sent to the driver board 253. The driver board 253 generates power supply voltage, signals, etc. based on the above information, and connects the connector 2 to the corresponding BT board 255.
54.

To explain the control board 250 in more detail, when the main/sub # section 201 of the entire BT device issues an instruction to send out information such as power supply voltage and signals to the control section 203 via the cable 251, the control section 203 An address value to be generated is set for the address generation section 204, and the address generation section 204 generates an address for the pattern memory 205. This pattern memory 205 has data that is the basis of the signal applied to the DUT written in advance, and the data at the address corresponding to the address generated by the address generator 204 is sent to the signal bus 232, connector 256, cable 252,
The signal is sent to the driver section 209 and determination section 210 of the driver board 253 via the connector 256' signal bus 232'.

These data are obtained by manually creating output values, that is, expected values for DOT input values, or by logically simulating them using a computer or the like. These data also include information on switching input and output of the DUT and information on which output of the DUT is to be determined.

Under the control of the control unit 203, the driver unit 209 generates a signal waveform based on the above data and applies it to the DUT 221 of the BT board 255 via the signal bus 212, connector 254, and signal bus 222.

DUT 221 on BT board 255 operates based on these signals. Further, the determination unit 210 determines whether or not the operation of the DUT 221 is correct by taking in signals from each DUT 221 and comparing them with expected data in the pattern memory 205, and transmits the results to the control unit 203 of the control board 250. The control unit 203 determines the result.

[Problems to be solved by the invention] The conventional monitor dynamic BT device described above is
This is a data generation method using a pattern memory using logical simulation data, and the capacity of the pattern memory is usually the same as the number of terminals of the DOT (for example, 64,128 bins...
・) requires a huge capacity of 32 to 64 I (...) for each DUT output switching information, DUT
It requires information such as whether or not to judge the output of the throat, and its control is complicated, and although it is a general-purpose device, it is generally an expensive device. It is impossible to easily create a huge amount of data manually, and it must be created using logical simulation using a computer. In any case, the cost required to create pattern data increases, and the overall BT cost increases. It has the disadvantage of causing an increase in

[Differences between the invention and the prior art] In contrast to the conventional monitor dynamic BT device described above, the present invention is an inexpensive device and can easily perform monitor dynamic BT.
The difference is that it can be done.

[Means and effects for solving the problems] The gist of the present invention is to provide a monitor dynamic burn-in test device for semiconductor integrated circuit devices, in which a semiconductor integrated circuit device whose normal function has been confirmed is mounted on a control board or a dry board;
a synchronous circuit that sets the semiconductor integrated circuit device and the integrated circuit device under test in a test mode and synchronizes them through clock level operations; a memory that stores instruction codes for operating both integrated circuit devices; A means for selecting an output signal and an output signal from the memory and outputting it to a driver unit that drives both integrated circuit devices, and a means for selecting an output signal and an output signal from the memory and outputting it to a driver unit that drives both integrated circuit devices, and output signals from a semiconductor integrated circuit device whose normal function has been confirmed and an integrated circuit under test. and comparison means for comparing the output signal from the circuit device.

The monitor dynamic BT device of the present invention mounts a non-defective IC on a control board or a driver board, puts the non-defective IC and DUT in test mode, and synchronizes their operations at the clock level. The instruction code for operating the circuit is read from the memory, the output signal of the synchronous circuit and the output signal from the memory are selected and supplied to the driver section, and the output signal from the good IC and the DU
The quality of the DUT is determined by comparing the output signals of the T.

[Embodiments] Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic diagram of a first embodiment of the present invention.

In the figure, 1 is the main control unit, 2 is the driver board, 3 is the control unit, 4 is the address generation unit, 5 and 6 are memories, and 7 is a semiconductor integrated circuit device whose normal function has been confirmed (hereinafter referred to as a good product I).
C), 8 is a selection section, 9 is a driver section, 10 is a judgment section, 1
1 is an address/data bus, 12 and 22 are signal buses,
13 is a connector, 14 is a clock generator, 15 and 1
6 is a switching unit, 20 is a BT board, and 21 is a DUT.

The main control unit 1 of the entire BT device instructs the control unit 3 on the driver board 2 to start BT, and the control unit 3 determines whether the IC is good or not.
and applying a power supply voltage and a clock signal to each DUT 21,
Further, a start address is set for the address generation section 4 and an instruction to generate an address is given, and the address generation section 4 sends address data to the memory 5.

This memory 5 includes a good IC 7 and each D on the BT board 2°.
Data for putting the UT21 into test mode is written in advance.

This test mode data is used to initialize the data of the IC's internal circuits, such as counters and registers, or to operate the test circuits installed internally in advance to create a test environment. Usually f
When testing an IC using a c tester, it is used to synchronize the operation of the IC tester and the operation of the DUT. Good IC7 and each 0 according to this test mode
The purpose of synchronization with the UT 21 will be described later.

When determining whether the operation of each DUT 21 is correct or not, the output of the non-defective IC 7 is used as the criterion, that is, the expected value, so the operation of the non-defective IC 7 and each DUT 21 must match at the clock level. It is from.

To enter this test mode, the input signal 111jl to a specific terminal of the IC is a combination of '0'' or a high voltage is applied. This is handled by writing in advance to
The latter is handled by driver 9.

The memory used here is, for example, 256)
Using a programmable read-only memory (FROM) of (32K x 8 bits), it is possible to generate 32 capacities of test mode data on eight terminals of the device, and the memory capacity and bits can be adjusted as needed. Vary the configuration.

This memory 5 sends data corresponding to the address data generated by the address generating section 4 to the selecting sections 8 and 8'.

These selection units 8 and 8' select data in the memory 6, data in the memory 5, and control of the control unit 3, which will be described later, and send them to the driver unit 9.
is converted into a predetermined waveform signal by control of the switching unit 15.
is applied to the good IC 7 via the signal bus 12, the connector 13, and the signal bus 22 of the BT board 2o.
Applied to UT21. As a result, the good IC7 and each DUT
21 is in test mode and synchronization can be achieved.

At the end of this test mode, data is written into the memory 5 so as to generate a reset signal for the reset terminal of the good fC7 and each DtJT21, and the selection section 8, driver section 9, and switching section 16 are The signal is input manually to the non-defective IC 7 via the selection section 8, the driver section 9, and the signal bus 12 to each DUT 21.

Upon receiving this reset signal, the control section 3 switches the switching section 16
The signal bus 12 to the non-defective IC 7 is disconnected, and the switching unit 15 controls the address/data bus 11 to be connected.

Good IC? This reset signal puts the device in a mode for accessing the memory 6, outputs an address to the memory 6, receives data in the memory 6, and operates based on the data. In this case, each DUT 21 of the BT board 20 is also in the mode of accessing external memory, but each 0U
Each T21 has no external memory, and the data received by the good IC 7 is transferred to each DUT 21 by the selector 8 and the driver #.
9, the equivalent operation is facilitated by providing signals via bus 12.13.

At this time, the input/output switching control of the driver section 9 is performed using the good product I.
Input/output control signals between C7 and memory 6, such as read (R)
D), write (WR), etc., and it is possible to avoid collision between the output signal of the driver section 9 and the output signal of each DUT 21. To determine whether the operation of each DUT 21 is correct, the output signals of the equivalent terminals from the non-defective IC 7 and each DUT 21 are taken into the determination unit 10 of the driver board 2, and the results are compared by sampling them with signals synchronized with the clock. is sent to the control unit 3, and the control unit 3 judges the result.

In the second embodiment, as shown in FIG. 2, one control board sends data that is the basis of the signal applied to the DUT to multiple driver boards, and these driver boards convert the data into a predetermined signal waveform. are generated and applied to the DUT of the BT board corresponding to the driver board, and the DU
To check the operation of T, compare it using the comparison section of each driver board.
This is an example of a monitor dynamic BT device in which the results are sent to the control board and the control section of the control board determines whether the product is good or bad. In the figure, 50 is a control board, 51 and 52' are cables, 53 is a driver board, 54 is a connector, and 55 is a B
It's a T-board.

The control board 50 is equipped with a control section, a memory for test mode, its address generation section, a non-defective IC, a memory storing instruction codes, etc., and each driver board 53 is equipped with a driver section and a determination section. Each DUT from 50
A monitor dynamic BT device is also conceivable, in which a large number of DUTs can be simultaneously monitored using one good IC.

[Effects of the Invention] As explained above, the present invention mounts a non-defective IC on a control board or a driver board, and includes a circuit for setting the IC and DUT in test mode and synchronizing their operations at the clock level, and the like. C and memory for storing instruction codes for operating the internal circuits of the IC and DUT; means for selecting the output signals of the above circuits and the output signals from the memory and outputting them to the driver section; and output from the good IC. Signal and D
By having means for comparing the output signals of the UT, an inexpensive monitor dynamic BT device can be realized.

[Brief explanation of the drawing]

FIGS. 1 and 2 show the first embodiment of the present invention. The block diagram showing the second embodiment and FIG. 3 are the conventional monitor dynamic B.
A block diagram showing an outline of the T device, and FIGS. 4 and 5 are the control boards in FIG. 3, respectively. FIG. 2 is a block diagram showing an outline of a driver board. 1.201... Main control section, 50.250.
...Control board, 2.53,253...
Driver board, 51.52°251,252...cable, 12, 22.
212°222,='232,232'...Signal bus. 3.203...Control unit, 4.204...Address generation unit, °Patent applicant NEC Corporation 13, 54. 254°

Claims (1)

[Claims] Monitoring of semiconductor integrated circuit devices In dynamic burn-in test equipment, a semiconductor integrated circuit device whose normal function has been confirmed is mounted on the control board or dry board, and the semiconductor integrated circuit device and the integrated circuit device under test are set to test mode. A synchronous circuit that synchronizes by clock level operation, a memory that stores an instruction code for operating both integrated circuit devices, and an output signal of the synchronous circuit and an output signal from the memory are selected and integrated circuits of both integrated circuits are selected. It has means for outputting to a driver unit that drives the device, and comparison means for comparing an output signal from a semiconductor integrated circuit device whose normal function has been confirmed and an output signal from the integrated circuit device under test. A monitor dynamic burn-in test device characterized by: