JPH02226552A - Reproducing block address generator - Google Patents

Abstract

PURPOSE:To always store data corresponding to a block address in a memory area correctly by providing a synchronous signal detection circuit, a parity check circuit, and a reproducing address forming part to generate the block address sequentially. CONSTITUTION:The block address and parity are inputted to the parity checking circuit 3 when the first detecting signal of each track is detected at a synchronism detection circuit 1, and the circuit 3 judges the propriety of the block address. When a first block address is correct, a reproducing block address generation circuit 3 is operated, and the block address for memory write is outputted at every prescribed cycle based on the first block address. Therefore, when it is started to output the block address for memory write from the circuit 3, since a reproducing block address corresponding to a normal address can be outputted from the circuit 3 even when the block address reproduced from a regenerative signal is incorrect or omitted, the data corresponding to the address can be stored in the correct area of a memory for interleave by using the block address.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is applicable to, for example, PCM audio and digital VTR.
This invention relates to a playback block address generator used when playing back digital data recorded using a block interleave method such as the above.

[Conventional technology]

In general, it is known that various data errors occur in recording and reproducing apparatuses during reproduction due to dropouts due to defects in the recording medium, data detection errors due to noise, etc. during recording or reproduction.

Among data errors during playback, for example, in the case of a random error where an error occurs in only one bit, if the location where the error occurred can be detected, the recorded content of the location where the error occurred can be estimated from the surrounding data. Errors can be corrected by restoring the data. However, such error correction cannot be performed in the case of burst errors in which errors occur continuously over a plurality of bits.

The block interleaving method is a recording method in which data is divided into blocks of a predetermined length and the blocks are rearranged and recorded. According to this recording method, burst errors that occur in rearranged data are dispersed and made into random errors by restoring the data order (deinterleaving) during playback, and correct data can be restored by error correction. become.

Therefore, when adopting the above recording method, in preparation for deinterleaving during playback, a synchronization signal indicating that the data is at the beginning of each block and a block address for block identification are usually added at the beginning of each block of data. is attached. In order to restore the order of each block during playback, a synchronization signal (Syn
After detecting c) (Sll), the block address of the block corresponding to the synchronization signal is detected (312), and this block address is used as the memory write address, and the data of each block is indicated by the block address of the block deinterleaving memory. written to the area (S1
3).

[Problem to be solved by the invention]

However, according to this conventional method, if an error occurs in a block address during reproduction, the data of that block will be stored in the wrong area of the block deinterleaving memory. Furthermore, if a block address is lost due to dropout or the like, the data in that block will be lost and there is a problem that the data cannot be restored correctly.

[Means to solve the problem]

In order to solve the above problems, the reproduced block address generator according to the present invention records data using a block interleaving method, and adds a synchronization signal, a block address for block identification, and a block address to each block of data. A playback block address generator that automatically generates a block address for memory writing to a memory for block deinterleaving when playing back digital data with a parity (or parity code) for determining whether it is correct or not. A synchronization detection circuit that detects the signal, a parity check circuit that determines whether the first block address is correct at a set timing based on the first synchronization signal, and a reproduced block address if there is no error in the first block address. The present invention is characterized by comprising a playback address generation circuit that sequentially generates the memory write block address at predetermined intervals based on the memory write block address.

[For production]

With the above configuration, the data of each reproduced block can be assigned a correct block address and stored in the block deinterleaving memory without error.

That is, when the synchronization detection circuit detects a synchronization signal from the reproduced signal, the parity check circuit determines whether the block address of the block to which the first detected synchronization signal is attached is correct or incorrect.

If the first block address is correct, the reproduction address generation circuit is started, and the memory write block address is output at predetermined intervals based on the first block address determined to be correct. Therefore, once this block address for memory writing starts to be output from the reproduction address generation circuit, even if the block address reproduced from the reproduction signal is incorrect or missing, the reproduction address generation circuit will output the regular reproduction block address. Since the reproduction block address corresponding to the block address can be obtained, the data corresponding to the block address can be stored in the correct area of the deinterleaving memory using this reproduction block address.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 to 6.

First, data to be reproduced is recorded as follows.

That is, as shown in FIG. 2(a), for example, one track of data is recorded as a block of a predetermined length BO+B l +
82 +...+Bn-1, the order of each block is rearranged according to a predetermined rule as shown in FIG. 2(b), and each block is divided into blocks as shown in FIG. 2(C). Block number (#0 to #n-1) indicating the order
) and a block address B6' indicating the deinterleaving memory area in which each data should be written during playback.
+B l' *B 2°+B3Z...B
n-1゛ is given. As shown in FIG. 2(d), a synchronization signal (sync signal) is placed at the beginning of each block.
and the block address B O'+ for block identification.
B%+B! ZB:1", . . . +BPl-1" and a parity for determining whether the block address is correct or not are recorded.

As shown in FIG. 1, the reproduced block address generator has a synchronization detection circuit 1 which inputs a reproduction signal obtained by reproducing this recording and detects a synchronization signal. This synchronization detection circuit 1 is configured to be able to detect a normal synchronization signal, while also eliminating erroneously detected synchronization signals, and forming a pseudo synchronization signal when a synchronization signal is missed to restore original synchronization. It is configured to have a known synchronization protection function of outputting at the same timing as the signal. Various synchronization signal generation circuits 2, which input the synchronization signals (or pseudo synchronization signals) separated by the synchronization detection circuit 1, operate the parity check circuit 3 and reproduction block address generation circuit 4, which will be described later, based on this synchronization signal. It is configured to generate various synchronization signals (or timing signals) that govern timing.

The block address and parity of the reproduced signal from which the synchronization signal has been separated by the synchronization detection circuit 1 are input to the parity check circuit 3 when the synchronization detection circuit 1 first detects the synchronization signal of each track. 3 determines whether the input block address is correct or incorrect at a predetermined timing, and if there is no error in the block address, outputs a count load command.

Note that the count load command of the parity check circuit 3 is output only when it is determined that there is no error in the block address for the first time, and is not output when it is determined that there is no error in the block address after repeated synchronization signals are detected.

The reproduced block address generation circuit 4 receives as input the block address of the reproduced signal from which the synchronization signal has been separated by the synchronization detection circuit 1 and outputs the block number corresponding to the block address. The first ROM is loaded by the count load command.
Input the block number output by 41 as the initial value,
Thereafter, a counter 42 is incremented by +1 at every predetermined synchronization period, and a second ROM 4 inputs the counted number of this counter 42 as a block number and outputs a playback block address corresponding to this block number.
It is composed of 3.

Next, a method for writing a reproduced signal into the block deinterleaving memory using this reproduced block address generator will be explained based on FIGS. 3 to 6.

If you input the playback signal that played back the recording as described above,
After the synchronization detection circuit 1 detects the synchronization signal (1'5tSync) at the beginning of the first block of each track (S 1 ), the parity check circuit 3 detects the block address of the first block, that is, the first block address. (1st address) is checked (S2).

If an error is determined in the above l'st address check (S2), the parity check circuit 3 does not output the count load command, and therefore,
No initial value is input from the first ROM 41 to the counter 42. Then, when the detection of the first synchronization signal of the next block is confirmed (S 1 ), the 1° st address check (S2) is executed again. In this way, the first synchronization signal detection (Sl) and l'st address check (Sl) are performed.
2) is repeated until it is determined that there is no error in the block address of the block at the l'st address check (S2) stage.

If it is determined that there is no error in the block address at the l'st address check (S2) stage, the parity check circuit 3 outputs a count load command only once for the first time, and at the same time the count load command is input to the l'st ROM 41. The block number corresponding to the block address is input to the counter 42 as an initial value, and the reproduced block address generation circuit 4 enters the operating state (S3).

Therefore, if the synchronization signal of the first block of each track is detected and it is determined that there is no error in the block address at that time, the block corresponding to the first block address B0'' will be The number "0" is input to the counter 42, and thereafter the counter 42 increments by +1 every cycle.

In addition, if the synchronization signal of the first block of the track cannot be detected and the synchronization signal is detected for the first time in the second block, and it is determined that there is no error in the block address at that time, the fifth block address will be detected. As shown in the figure, the first ROM 41 inputting the block address Bm' outputs the corresponding block number k, and the counter 42 which received the count load command inputs the block number k as an initial value. 42 is + per cycle
It will be incremented by 1.

Then, when the counter 42 starts counting, the second
The ROM 43 inputs the count number as a block number, and the second ROM 43 outputs a reproduction block address BO'' or Bk'' corresponding to this block number. Then, this playback block address B0” or B
Using kII as a block address for memory writing, the data of the reproduced signal is written to the memory for block deinterleaving (S4).

For subsequent blocks, after detecting the synchronization signal of that block (S5), the reproduction block address generation circuit 4
generates a correct reproduction block address (S6), and uses this reproduction block address as a memory write block address to write the reproduction signal data to the block deinterleaving memory (S7). This program is repeated.

Once the above program is started, for example, as shown in FIG. 6, if it is determined that there is an error in the block address of the m-th block or the m+1-th block consecutively. Even if the reproduction block address generation circuit 4
Correct playback block address B to be output in order for each cycle.

The data of each block is written to the block deinterleaving memory using B, , . Therefore, the data will be written to the correct area of the block deinterleaving memory, thereby preventing double writing due to an error in the reproduction block address and data loss due to omission of the reproduction block address.

〔Effect of the invention〕

As described above, the reproduced block address generator of the present invention performs recording using the block interleave method, and
When reproducing digital data in which each block of data has a synchronization signal, a block address for block identification, and a parity for determining whether the block address is correct or incorrect, the block address for memory writing to the memory for block deinterleaving is determined. A reproduction block address generator that automatically generates a synchronization signal detection circuit that detects the first synchronization signal, and a parity that determines whether the first block address is correct or incorrect at a set timing based on the first synchronization signal. a check circuit; and a reproduction address forming unit that sequentially generates the memory write block address every predetermined li1 period based on the reproduced block address after it is determined that there is no error in the first block address. The configuration is equipped with the following.

As a result, the parity check circuit determines whether the block address of the block is correct or incorrect based on the synchronization signal that is detected earliest by the synchronization detection circuit, and when there is no error, the reproduction block address generation circuit is started, and the reproduction block address is The generation circuit then outputs the correct playback block address at a predetermined timing regardless of the presence or absence of the block address included in the playback signal and whether it is correct or incorrect, so the correct playback block address output by this playback block address generator is used for memory writing. The data of the block can be written to the block deinterleaving memory as a block address. Therefore, it is possible to prevent double writing due to an error in the reproduction block address and data loss due to omission of the reproduction block address.

[Brief explanation of the drawing]

1 to 6 show an embodiment of the present invention, in which FIG. 1 is a block circuit diagram of a reproduction block address generator, and FIG. 2(a) shows data blocking on the recording side. Figure 2(b) is a diagram showing the structure of data block interleaved on the recording side.
C) is an explanatory diagram explaining the weighting of block interleaved data by block number and block address, Figure 2 (d) is a diagram of the configuration of the signal string of each block, and Figure 3 is the memory for block deinterleaving during playback. FIG. 4 is a flowchart showing the method of writing data to a track, and FIG. Figure 5 shows that synchronization was successfully detected for the first time in the second block of one track.
A timing diagram of the signals in each part of the reproduction block circuit when it is determined that there is no error in the block address of the block. Figure 6 shows each circuit when an error occurs in the block address after the reproduction block address generator has started. FIG. 7th
The figure is a flowchart showing a conventional method of writing data into a block deinterleave memory during playback. 1 is a synchronization detection circuit, 3 is a parity check circuit, and 4 is a reproduced block address generation circuit. Patent Applicant: Sharp Co., Ltd. Figure 1 Figure SL Figure Figure

Claims (1)

[Claims] 1. Digital data that is recorded using a block interleave method and in which each block of data is attached with a synchronization signal, a block address for block identification, and a parity for determining whether the block address is correct or incorrect. When playing,
This is a reproduction block address generator that automatically generates a block address for memory writing to the memory for block deinterleaving, and includes a synchronization signal detection circuit that detects the first synchronization signal, and a synchronization signal detection circuit that detects the first synchronization signal. a parity check circuit that determines whether the first block address is correct or incorrect at the correct timing;
and a reproduced address forming unit that sequentially generates the block address for memory writing at predetermined intervals based on the reproduced block address after it is determined that there is no error in the first block address. A regenerative block address generator featuring: