JPH02226724A - Manufacture of integrated circuit device - Google Patents

Abstract

PURPOSE:To eliminate deviation from designed values of widths of a gate electrode and of an interconnection pattern in a field oxide film region having difference in level with respect to an active element region and to improve reliability of an integrated circuit by using photomasks having widths appropriate to the regions to which they are used. CONSTITUTION:If photomasks for an active element region 1 and a field oxide film region 2 having a difference in level with respect to the region 1 have widths of l-f(alpha, h) and l, respectively, widths l44 and l33 of resist patterns will be l44 - [l - f(alpha, h)]-(l-l33)=f(alpha, h). Therefore, l33=l44. Accordingly, an interconnection pattern in the region 2 and a gate electrode in the region 1 can be formed in correct widths without deviation from designed values. Thus, an integrated circuit can be produced with improved reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing an integrated circuit device, and particularly to a method for forming a date electrode in the active element region in a field oxide film region having a step with respect to the active element region. The present invention relates to a method for forming wiring patterns having the same four-turn width and simultaneously forming them from the same material.

[Conventional technology]

FIGS. 3(a) and 3(b) are a plan view and a sectional view showing a part of the designed structure of an example of this loincloth integrated circuit device.

In the figure, 1 is an active element region, 2 is a field oxide film region, 3 is a gate electrode, 4 is a wiring pattern, 5 is a metal wiring turn, and 6 is a source and drain diffusion layer.

FIG. 4 shows the gate electrode 3 and wiring 1 of the conventional integrated circuit device shown in FIG. A method for forming turn 4 is shown.

A conductor layer 11 of a gate electrode material is formed on the wafer surface in which an active element region 1 and a field oxide film region 2 having a step with respect to this region 1 are formed.

A resist layer 12 is formed by applying a resist onto the conductor layer 11 to a thickness that flattens the surface.

As shown in FIG. 5, this resist layer 12 is exposed and developed using a photomask 13 having the same throughput and master turn width for the active element region 1 and the field oxide film region 2, and the exposed resist 12 is Remove by etching. The figure shows an example of a Poe type resist. In the case of a negative resist, the mask data is reversed. ) The conductor layer 11 is etched using the resist pattern formed in the active element region 1 and the field oxide film region 2 as a mask, and the resist pattern is removed.

According to the above steps, the wiring/arm turns 4 in the field oxide film region 2 are formed simultaneously with the formation of the gate electrode 3 in the active element region 1.

[Problem to be solved by the invention]

In the above process, when the resist layer 12 is exposed to light through a mask, developed, and the exposed resist 12 is etched away, the formed resist turns are as follows.
As shown in FIG. 6, the cross section is trapezoidal.

The etching taper is determined by the resist material, exposure time, and development time, and is determined by the i9 turn width t of the mask.
The pattern width of the resist pattern on the conductor layer 11 is t+2Δt22° in the active element region 1, t+2Δt4. Then, the difference in pattern width of the resist patterns in these two areas 2 (Δt2□−Δt
1. ) is the relationship f(
α, Δh).

As mentioned above, when maskers with the same pattern width are used, the resist pattern J? serves as an etching mask for the conductor layer 11 in the active element region 1 and field oxide film region 2. A pattern of turns I [K f (α, Δh) O difference is created.

Therefore, 7 of the ff-) electrodes 3 in the active element region l
When etching is carried out so that the width of the four tangents becomes the design value t, the wiring in the field oxide film region 2 (as shown in BL) in FIG. 7(a) J? When etching is performed so that the pattern width of the turn 4 becomes narrower than the design value t, and the width of each turn of the wiring pattern 4 in the field oxide film region 2 becomes the design value t, as shown in FIG. 8 (al, b). As such, the pattern width of the gate electrode 3 in the active element region 1 becomes thicker than the design value t.

That is, there was a problem in that the pattern width of either the wiring or the mother turf 4 of the date electrode 3 deviated from the designed value.

The present invention was made to solve the above problems.
The object of the present invention is to provide a method of forming gate electrodes, wiring, and arm turns with the same pattern width.

[Means to solve the problem]

In order to achieve the above object, the method of the present invention creates a dimensional difference corresponding to the function f (α, Δh) in the pattern width between the active element region and the field oxide film region of the photomask used for turning the resist layer. The pattern width is the same for the 1/no-turns and turns formed in both areas.

〔Example〕

1(a) and 1(b) show examples of mask patterns for the active element region and field oxide film region in the photomask used in the present invention, and FIG. 2(a)
*(b) shows resist leans formed by the mask turns shown in FIGS. 1(a) and 1(b), respectively.

Photomask/? The process is the same as before, only the turn width has been changed.

The turn width on the field oxide film region side shown in FIG. 1(a) is t, and the pattern width on the active element region side is t-f.
(α, Δh) In the resist pattern shown in FIG. zz-z,) =
From f(α, Δh), '53='44, and the pattern width is '5' in the case shown in Fig. 2(b) as well.
5''66 becomes '55 = t66.

Resist pattern width '5! S='44"55='6
6 is larger than t, but as the etching of the conductor layer 11 continues, the pattern width of the date electrode in the active element region and the wiring d' turn in the field oxide film region are simultaneously increased to t.
It can be done.

〔Effect of the invention〕

As explained above, according to the method of the present invention, there is no deviation from the design value in the width of the interconnect line in the field oxide film region having a step with respect to the active element region, and the width of the gate electrode. It is highly effective in contributing to improvement.

[Brief explanation of the drawing]

FIGS. 1A and 2B are plan views showing examples of masks and turns for the active element area and field oxide film area in the photomask used in the present invention.
Figures (a) and (b) are respectively Figure 1 (!L),
Cross-sectional view showing the resist/4' turn formed by the mask pattern shown in (b), Figures 3 (a) and (b)
1 is a plan view and a sectional view showing a part of the design structure of an example of this integrated circuit device. FIG. 4 is a cross-sectional view showing a conventional method for forming gate electrodes, wiring, and nine turns of this type of integrated circuit device, and FIG. 5 shows an example of a mask pattern in a photomask used in the method shown in FIG. The plan view shown in FIG. 6 is the mask i shown in FIG.
'? Cross-sectional views showing resist holes and turns formed by turns, FIG. 7(a), (b), FIG. 8(a),
(b) is a plan view and a sectional view showing a gate electrode and a wiring i4 turn, respectively, which are formed by etching using the resist/mother turn shown in FIG. 6 as a mask. DESCRIPTION OF SYMBOLS 1... Active element region, 2... Field oxide film region, 3... Gate electrode, 4... Wiring pattern Note that the same reference numerals in the drawings indicate the same or corresponding parts. (Q) Figure 1 Figure 12 (a) (b) Figure 3

Claims (1)

[Scope of Claim] In a method for manufacturing an integrated circuit device, a wiring pattern is provided in a field oxide film region having a step with respect to an active device region, and has a wiring pattern having the same pattern width and the same material as a gate electrode in the active device region. forming a conductor layer of a gate electrode material on the wafer surface in which a field oxide film region having a step with respect to the active element region is formed; and a resist having a thickness such that the surface is flattened on the conductor layer. forming a layer in the active element region and the field oxide film region caused by the etching taper of the resist layer when the resist layer is exposed and developed using a mask with the same pattern width; The resist layer is exposed and developed using a photomask with pattern widths set for the active element region and field oxide film region taking into account the difference in pattern width of the resist pattern, and the active element region and field oxide film region are exposed and developed. forming a resist pattern with the same pattern width at a predetermined position in the film region; and etching the conductor layer using the resist pattern as a mask to form a gate electrode in the active element region and a wiring pattern in the field oxide film region. A method for manufacturing an integrated circuit device, comprising the steps of: