JPH02226731A - Manufacture of thin film transistor - Google Patents

Abstract

PURPOSE:To manufacture a high precision TFT in high yield by a method wherein two each of TFTs are patterned to be cut off by laser beams. CONSTITUTION:An electrode 1 and a non-single crystal semiconductor layer such as N type, etc., are laminated on a substrate 22 having ITO electrode 21 and then these layers are cut off by laser beams so that the cut off parts may be patterned into two TFTs comprising a source region 25 and a source electrode 23 as well as drain regions 26 and drain electrodes 24. Next, these patterns are cut off by laser beam irradiation to be separated into two parts of the source region 25 and the source electrode 23 and then two TFTs are formed by successive specified processing. Through these processes of patterning two each of TFTs, the alignment precision can be augmented by around two times while relieving the mask precision so that a high precision TFT may be manufactured in high yield.

Description

Detailed Description of the Invention: Prior Art 1 When manufacturing a thin film transistor (hereinafter also referred to as TPT), conventionally, in patterning an N- or P-type non-single-crystal semiconductor thin film, high-resistance (■-type) When patterning non-single crystal semiconductor thin films and gate insulating films, patterning was performed to the size and shape of each thin film transistor. However, since thin film transistors are very small elements (they must be small for displays, etc.), alignment is extremely difficult, and masks also require strict precision, resulting in lower yields.

An example of a method for manufacturing a conventional thin film transistor (typically a staggered type) is shown in FIGS. 1(a) to 1(d).

A substrate (12) having an ITO electrode (11) as a pixel electrode.
), by forming a molybdenum thin film and patterning it, the source and droop-in electrodes (13) and (14) are formed.
Create. (FIG. 1(a)) After forming a semiconductor layer with N-type conductivity using the plasma CVD method,
A semiconductor layer having N-type conductivity is separated into source and drain regions (15) and (16) using a photolithography method. (FIG. 1(b)) Next, a high resistance (I type) non-single crystal semiconductor layer (17) and a gate insulating film (18) are formed. (FIG. 1(C)) Finally, a gate electrode (19) is produced to complete the thin film transistor. (FIG. 1(d)) Also, the response speed of the thin film transistor is given by the following equation.

S=μ・V/I,” where L is the channel length, μ is the carrier mobility, and ■ is the gate voltage.

The non-single-crystal semiconductor layer used in thin-film transistors contains a large number of crystal grain boundaries in the semiconductor layer, and due to these, carrier mobility is extremely low compared to single-crystal semiconductors, as can be seen from the above equation. There was a problem that the response speed of the transistor was extremely slow. Especially when using an amorphous silicon semiconductor, its mobility is approximately 0.1~
1 (cm''/V-Sec), and could hardly operate as a thin film transistor.

In order to solve this problem, it is most effective to shorten the channel length which is affected by the square.

However, when forming a device on a large-area substrate, it is difficult to reduce the source-drain spacing (corresponding to the channel length) to 10 μm or less using photolithography due to processing accuracy, yield, production cost, etc. It is clearly difficult and there is a need to shorten the channel length without using photolithography techniques.

As one answer, a TFT with a red channel structure as shown in FIG. 3 has been proposed. In this process, a non-single crystal semiconductor layer consisting of a source (30), an active region (31), and a drain (32) is laminated on a substrate, and then a gate insulating film (3
3) and has a gate electrode (34) thereon.

In this structure, the channel length is approximately equal to the active region (31
), the channel length could be easily varied by adjusting the thickness of the active region.

However, since TPT with this structure has multiple non-single-crystal semiconductor layers stacked, it has many interfaces in the direction in which current flows between the source and drain, resulting in a good TPT.
T characteristics cannot be obtained. In addition, since the cross-sectional area in the direction of current flow is large, there is a problem that the off-state current increases.
Vertical TPT does not essentially solve the problem.

"Structure 1 of the Invention In order to solve the above problems, the present invention provides that, at least until the middle of the manufacturing process, a non-single crystal semiconductor layer having at least N or P type conductivity is patterned as one unit for two thin film transistors. , the non-single crystal semiconductor layer for two thin film transistors is cut into respective parts by a laser beam.
"or a non-single crystal semiconductor layer having P-type conductivity" means
Or a non-single crystal semiconductor layer with P-type conductivity, source/
At least N or P of the drain electrode, high resistance non-single crystal semiconductor layer (one layer), gate insulating film, and gate electrode
It means a non-single crystal semiconductor layer having type conductivity, and includes each of the above five elements or a combination thereof.

Furthermore, in the present invention, since the source and drain regions are separated using laser light, the distance between the source and drain (corresponding to approximately the channel length) can be shortened.
Thereby, a thin film transistor with high response speed can be manufactured.

In addition, in the present invention, two thin film transistors in the middle of the process are first cut with a laser beam, and then the non-single crystal semiconductor layer having N or P type conductivity, the source/drain electrode, the first layer, and the gate insulating film are cut. , each of the gate electrodes, or a combination of these may be patterned as one for two thin film transistors, because in this case, the thin film is cut by laser light, so there is no thin film in the cut area, so in the end, the thin film transistor This is because it is sufficient to pattern it into two parts.

By using the present invention, the alignment accuracy during patterning of a non-single crystal semiconductor thin film having N or P type conductivity during the production of thin film transistors can be improved to twice the accuracy compared to conventional methods, and the accuracy of the mask can also be improved. Since the material becomes looser, the yield increases significantly.

Furthermore, source/drain electrodes, one layer, gate insulating film,
If the gate electrodes of two thin film transistors are patterned as one, their alignment will be approximately twice as accurate, and the precision of these masks will also be made looser, thereby further increasing the yield.

The present invention will be described in detail below using examples. It is believed that the present invention will be easier to understand by comparing it with the conventional example.

Example 11 In this example, a method for manufacturing a staggered thin film transistor for use in a liquid crystal display will be described using FIGS. 2(a) to 2(f).

A substrate (22) having an ITO electrode (21) as a pixel electrode.
), a molybdenum thin film is formed by a known sputtering method and patterned to produce an electrode (1). (FIG. 2(a)) And the known plasma CVD
A non-single-crystal semiconductor layer (non-single-crystal silicon film) having N-type conductivity is formed using a method. The film forming conditions at this time are as follows.

Substrate temperature 250°C Reaction pressure 0.05TorrRf power (13,56MHz) 150W Gas used
5iHa0PHs film thickness
Then, using excimer laser light, a non-single-crystal semiconductor layer with N-type conductivity and the previously formed electrode were used as a source.
Cut into drain regions (25) and (26) and source and drain electrodes (23) and (24).

Here, two adjacent source regions (25) are still connected. (Figure 2 (b)) The laser irradiation conditions in this process are a power density of 1
．． Five pulses were irradiated at 5 J/cm' and a pulse width of 15 psec. The irradiation conditions vary depending on the workpiece, and in the case of this example, preliminary experiments were conducted to determine the conditions described above, and those conditions were used.

Additionally, laser light is usually strong at the center and weak at the edges, exhibiting a Gaussian distribution of intensity. Therefore, if the light is irradiated in this state, only the central portion of the light will be cut, so in this example, an optical system was used to uniformize the intensity of the light and perform the irradiation.

Next, after forming a high resistance (summer type) non-single crystal semiconductor layer (27) and a gate insulating film (2 days), the source region is separated using excimer laser light (see Fig. 2). C))
.

Note that the summer type non-single crystal semiconductor layer (27) in this step
The film forming conditions were almost the same as those for a non-single crystal semiconductor layer having N-type conductivity, but only 5tO4 was used as the gas, and the film thickness was 6000 nm.

Then, the N-type non-single-crystal semiconductor layer, the summer-type non-single-crystal semiconductor layer (27), and the gate insulating film (28) are patterned to form the gate electrode (29), and the thin film transistor is completed (see Figure 2). d)).

In this example, after forming the gate insulating film, the source region was separated by irradiation with laser light. However, the gate insulating film may be formed after laser light irradiation. In this case, in FIG. 2(d), an insulating film remains between the two thin film transistors, but the performance of the thin film transistors is exactly the same.

In addition, in this example, the N-type semiconductor layer is separated using laser light to create the source and drain regions.
Furthermore, the connected source regions were cut using laser light. In other words, by using laser light, it was possible to shorten the distance between the source and drain (which roughly corresponds to the channel length).

Therefore, when amorphous silicon is used as a type semiconductor, it is possible to compensate for the extremely low carrier mobility of amorphous silicon and increase the response speed of a thin film transistor. Furthermore, in order to increase the aperture ratio in a display, it is said that the distance between pixels is as narrow as possible (the narrower the better), but as in this example, since the connected source regions were cut using laser light, the cut portion can be made very narrow, which is very effective for providing two thin film transistors between pixels.

Furthermore, in this example, the source region was separated by irradiating laser light before forming the gate electrode, but it is also possible to irradiate the source region after forming the gate electrode to separate the source region. In this case, the cross-sectional view is the second
It will look like FIG. 2(e), and the plan view will look like FIG. 2(f).

At this time, care must be taken not to cut the common wiring of the gate electrode when irradiating the laser beam, but there is an advantage that the gate electrode can also be patterned for two thin film transistors as one unit.

Here, FIG. 2(f) shows only the electrode portion.

Example 21 In this example, a method for manufacturing a coplanar thin film transistor for use in a liquid crystal display will be described using FIGS. 4(a) to 4(d).

A substrate (42) having an ITO electrode (41) as a pixel bridge.
), a high resistance (I type) non-single crystal semiconductor layer (non-single crystal silicon film) (47) and a non-single crystal semiconductor layer (50) having N-type conductivity were formed by plasma CVD. Afterwards, perform etching. (Figure 4 (a) Then, the semiconductor layer with N-type conductivity is cut into source and drain regions (45) and (46) using excimer laser light, and a thin molybdenum film is formed and patterned. The source and drain electrodes (43) and (44) are produced by cutting.
■Care must be taken not to cut the type semiconductor layer. Here, two adjacent source regions (45) are still connected. (FIG. 4(b)) Then, a silicon nitride film (48) is formed as a gate insulating film and patterned.
(Fig. 4 (C)) Next, after separating the source region using an excimer laser, a molybdenum fill is formed and patterned to form a gate electrode (49), and a coplanar thin film transistor is completed. . (FIG. 4(d)) In this example, the source region can be separated by laser light irradiation before the gate insulating film is formed, as in Example 1, or after the gate electrode is formed. It is possible.

In this example, a method for manufacturing a coplanar thin film transistor using the present invention was described, but it is clear that the same effects as in Example 1 can be obtained in this example as well. Furthermore, by referring to Example 1 and this example, it is clear that the present invention is applicable even when the thin film transistor to be manufactured is an inverted staggered type or an inverted coplanar type.

r effect 1 As described above, by using the present invention, the yield during patterning of low resistance non-single crystal semiconductor layers is increased, and furthermore, the patterning of high resistance non-single crystal semiconductor layers, source/drain electrodes, and gate insulating films is improved. Similarly, it is possible to increase the yield in patterning gate electrodes.

Further, in the examples in this specification, only a method for manufacturing a thin film transistor using a non-single crystal semiconductor layer having N-type conductivity is shown, but even when a P-type non-single crystal semiconductor layer is used. It is clear that the present invention can be used effectively.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(d) show the manufacturing process of a conventional staggered thin film transistor. Figures 2 (a) to (f) and Figure 4 (a) to (d) are
1 shows a manufacturing process of a thin film transistor according to the present invention. FIG. 3 shows a conventional vertical thin film transistor. 1... Electrode 21.41... Summer TO electrode 22.42... Substrate 23.43.24.44... Source, drain electrode 2
5.45.26.46...Source, drain region 27
．． 47... High resistance non-single crystal semiconductor layer 28.48.
...Gate insulating film 29.49...Gate electrode 50...Non-single crystal semiconductor layer having N-type conductivity

Claims (1)

[Claims] 1. A method for manufacturing a thin film transistor, in which a non-single crystal semiconductor layer having N or P type conductivity forming at least a source and a drain region is used as a thin film transistor 2 at least until the middle of the manufacturing process. A method for manufacturing a thin film transistor, characterized in that the non-single crystal semiconductor layers of the two thin film transistors are patterned as one, and the non-single crystal semiconductor layers of the two thin film transistors are cut into respective parts by laser light. 2. In claim 1, the portion that is patterned as a single unit of approximately two thin film transistors is N.
Or a non-single crystal semiconductor layer with P-type conductivity, source/
A method for manufacturing a thin film transistor characterized by comprising a drain electrode, a high resistance non-single crystal semiconductor layer, a gate insulating film, and a gate electrode. 3. A method for manufacturing a thin film transistor according to claim 1, characterized in that laser light is used to separate the N- or P-type non-single crystal semiconductor layer into a source region and a drain region.