JPH02226816A - Analog/digital conversion system - Google Patents

Abstract

PURPOSE:To speed up A/D conversion by setting the value of a current which flows through a current mirror circuit not to zero at all times regardless of an analog input value to an A/D converter. CONSTITUTION:An analog output value generating means 102 generates the result which is obtained by subtracting an offset quantity from the doubled value of the analog input value as an analog output value when the analog input value compared by a comparing means 101 is <=1/2 as large as a reference value, but generates the result which is obtained by subtracting the reference value from the doubled value of the analog input value and further subtracts the offset value as the analog output value when the analog input values is >1/2 as large as the reference value. Therefore, the offset value included in an input current becomes equal to the offset value included in an output current and the current of, for example, the current mirror circuit never becomes zero without reference to the analog input value. Consequently, the analog/digital(A/ D) converting speed is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an analog-to-digital conversion method for converting an analog signal into a digital signal.

[Conventional technology]

Figure 9 shows ELECTRONIC3LETTER3 magazine 1
It is described on page 471 of the April 14, 1998 issue (Vol. 24, No. 8), and is one of the circuit blocks of a conventional A/D converter.

1 is a current input terminal of the electronic circuit 2. 3 is an N-channel MOS transistor, the drain of which is connected to the current input terminal 1; Further, the N-channel MOS transistor 3 has its gate and train connected, and is a so-called diode-connected transistor. The gate of N-channel MOS transistor 3 is N-channel MOS transistor 3.
N-channel NOS transistor 3.5a is connected to the gates of OS transistors 5a and 5b.

5b forms a Karen 1-Mira circuit. The drains of N-channel MOS transistors 5a and 5b are connected to the drain of a diode-connected P-channel MOS transistor 12. Zarani, P channel MOS
Goo 1~ of transistor 12 is P channel MO81~
The transistors 12, 13 and 14 are connected to the gates of transistors 13 and 14, forming a current mirror circuit.

A reference current source 20 outputs a constant current (reference value amount), and is connected to a diode-connected N-channel MOS transistor 21. The gate of the N-channel MOS transistor 21 is connected to the N-channel MOS transistor via the terminal 9.
It is connected to the gates of S transistors 10 and 11, and transistors 21.degree. 10.11 form a current mirror circuit.

N-channel MOS transistor 10 and P-channel M
The train of OS transistors 13 is input to a current comparator 16. The output of the current comparator 16 is connected to an N-channel MO3I transistor 15 whose source is connected to the drain of the N-channel MOS transistor 11 and whose train is connected to the drain of the P-channel MOS transistor 14. There is. Further, the output of the current comparator 16 is connected to the digital output terminal 8, and the drain of the P-channel MOS transistor 14 is connected to the current output terminal 6.

Next, the operation will be explained. N-channel MOS transistor 3.5a forming a current mirror circuit,
Assuming that transistors 5b have the same characteristics, the same current as the current input from current input terminal 1 and flowing through the drain of transistor 3 becomes the train current of each of transistors 5a and 5b. In other words, the current input from current input terminal 1 (
The gate voltage of diode-connected N-channel MOS transistor 3 changes depending on the amount of analog input (analog input amount).

Since the gate of transistor 5b is connected to the gate of N-channel MO3+- transistor 3, the same amount of current flows through transistors 5a and 5 as the current flowing through the drain of transistor 3, respectively.
It also flows into train b. Therefore, a current twice the input current flows through the diode-connected P-channel MOS transistor 12. On the other hand, since the P-channel MOS transistors 13 and 14 also form a current mirror circuit together with the P-channel MO31 to transistor 12,
By the same principle as above, a current equal to the drain current of the transistor 13, that is, twice the input current, flows from 1 to
It flows through the drains of transistors 13 and 14. Similarly, regarding the N-channel MOS transistor 21.10.11 forming the current mirror circuit, the drain current of the transistor 10.11 has the same value as the output current of the reference current source 20.

The current comparator 16 is a P-channel MOS transistor 1
Drain current of 3 and N-channel MOS transistor 1
0 train current is compared, and the N-channel MOS transistor 15 is opened or closed depending on the comparison result. That is, P
The drain current of channel MOS transistor 13 is N
If the drain current is smaller than the drain current of the channel MOS transistor 10, the output of the current comparator 16 becomes a low potential level (logical value O), cutting off the N-channel MOS transistor 15, and in the opposite case, the output of the current comparator 16 becomes a high potential level. level (logical value 1) and makes the N-channel MOS transistor 15 conductive.

Accordingly, in the former case, the drain current of the P-channel MO3I- transistor 14 is directly obtained from the current output terminal 6, and in the latter case, the drain current of the P-channel MOS transistor 14 is obtained from the N-channel MO8l-
The amount of current obtained by subtracting the train current of transistor 11 is obtained.

The above operations can be summarized as follows.

B= O (if 2Iin<Iref) 1 (21i
If n≧1ref) (1) Iout = 2 I tn
-B -I ref However, Iin is the amount of current inflow from the current input terminal 1, I ref is the current value of the reference current source 20,
B is the output logic value of the digital output terminal 8, and 10ut is the current outflow amount of the current output terminal 6. Also, () in formula (1)
The conditional expression enclosed by is a comparison expression between 2iin and l ref, which is equivalent to a comparison between Iin and Iref/2. FIG. 10 explains the operations expressed by equations (1) and (2). When a linearly increasing current like the straight line 207 is input to input terminal 1, the current inflow is 1J.
The output logical value B until in becomes equal to Iref/2
110, and 2iin is output as an output current.

At the moment when the current inflow amount Jin becomes equal to IrE3f/2, the output logic value B becomes 1 and the output current changes from Iref to O. Then, when the current inflow 11in exceeds Iref/2 and increases to 1ref, the output current is calculated by the formula (21in
−1 ref ) and increases once again from O to l ref.

As an example of using a conventional circuit like this, a conventional A/D
An example of the configuration of the converter is shown in FIG.

The part surrounded by the dotted line in Figure 9 corresponds to 2 in Figure 11,
In the following, it will be referred to as a bit cell. The N circuit blocks are cascaded via a current input terminal 1 and a current output terminal 6. Further, the current input terminal 1 of the first bit cell 2 located on the input side is connected to a current source 22 .

The reference current source 20 is a diode-connected N-channel MO
The drain of S transistor 21 and all bit cells 2
are commonly connected to terminal 9 of the two terminals.

The operation of this A/D converter will be described below.

In the following, it is assumed that Jk: the input current B of the th bit cell; and the digital output value of the th bit cell I: the current value of the current source 22. Since the terminal 9 of all the bit cells 2 is commonly connected to the gate of the diode-connected N-channel MOS transistor 21, the train current of the N-channel MOS transistors 10 and 11 of all the bit cells 2 is the output of the current source 20. current) becomes equal to ref. Taking this into consideration, the operation is as follows. First, in the first bit cell 2, 2I and I ref are compared.

That is, a comparison equivalent to the comparison between ■ and Iref/2 is performed. Here, if I is larger than Iref/2, B1 becomes 1, and in the opposite case, B1 becomes O, and the first digit of A/D conversion is determined. At this time, the output current is 2L in the former case and 2l-Jref in the latter case.

In the second bit cell, these currents are doubled and 4
I or 4I-2Iref is compared to Iref. In other words, a comparison equivalent to the comparison of I and Iref/4 or 3Iref/4 is performed to determine the second digit. Through this procedure, Bk is sequentially calculated from the most significant bit B1.
Assume that by determining and proceeding, it changes linearly from O to Iref as shown in (207a>. First, in the first bit cell 2, when ■ changes from O to Iref/2, the digital output Bl (208a ) is 01 The output current of this bit cell 2, that is, the input current I2 of the second bit cell 2 (207b) changes from O to Iref. Then, when I changes from Iref/2 to J ref, the digital output B1 (208a) becomes 1, I2
(207b) changes again from O to Iref.

In the second bit cell 2, while I (207a) increases once from O to Iref, I2 (207
b) increases twice from O to l ref, so B
2 repeats the change from O to 1 twice as shown in (208b), and I3, which is the output of this bit cell 2, is (207c)
Repeat the linear increase from O to l ref 4 times as shown below. In the third bit cell 2, I (20
7a> changes once from O to 1ref, I3
Since (207G) increases four times from O to Iref, B3 repeats the change from O to 1 four times as shown in (208C), and I4, which is the output of this bit cell 2, becomes (20
7c), the linear increase from O to Iref is 8
Repeat times. In this way, when I changes from O to Iref, the output Bk of the k-th bit cell is 2j −(
Iref/2K)≦I<(2j+1) ・(Ire
f/2K), Bk=0 c2j+1>-(Iref/2')≦I<(2j+
2) In the case of (Iref/2'), Bk=1. In this way, a digital binary number [81B2 . . . BN] proportional to the analog ff1I is obtained.

(Problem to be Solved by the Invention) The conventional A/D converter is configured as described above, but because the response speed of the current mirror circuit is slow, the A/D converter is
This was impairing the conversion speed of the converter. For example, the 9th
N-channel MOS transistors 3, 5a and 5b in the figure
Consider a current mirror circuit consisting of the following. Assuming that the parasitic capacitance value attached to the gate of this current mirror circuit is 01, and the resistance value between the drain and source of the diode-connected N-channel MOS transistor 3 is R5, the response speed of this current mirror circuit is determined by the time constant C1·R5. The larger is, the slower it is. On the other hand, the drain current value of N-channel MOS transistor 3 is 15, and the drain-source voltage is MOS5.
, the threshold voltage of the N-channel MOS transistor is VTIIN, then l5-(β5/2>(MOS5-
It is widely known that VTHN)2 (5).

Here, B5 is a proportionality constant that does not depend on V DS5. From formula (5), R5 is dVDS5 1 1R5=
= =d15 B5(
MOS5-VTIIN) (215β'+)'. Here, since the current I5 entering the bit cell 2 takes one line from O to Iref, R5 may become infinite. When the input current of the bit cell 2 changes in the vicinity of V, the time constants C1 and R5 of the current mirror circuit become large, significantly impairing the response speed. As described above, in the conventional A/D converter, the current flowing through the current mirror circuit can be close to 0, which significantly impairs the conversion speed.

This invention was made to solve the above-mentioned problems, and it is an object of the present invention to provide an analog-to-digital conversion method that can improve the analog-to-digital conversion speed.

(Means for solving the problem) In the analog-to-digital conversion method according to the present invention,
The analog output quantity generating means 102 or 502 is the analog human power m compared by the comparing means 101 or 501.
is less than 1/2 of the reference value amount, 2 of the analog input amount
Generate the result of subtracting twice the offset amount for the elements of each means, or the result of subtracting twice the analog input amount from the reference value amount and further adding three times the offset amount as an analog output amount, On the other hand, if the analog input amount is larger than half of the reference value amount, the result of subtracting the reference value amount from twice the analog input amount and further subtracting the offset amount, or the analog Input amount 2
This feature is characterized in that the result of subtracting the multiplier and adding three times the offset amount is generated as an analog output amount.

[Effect]

The analog input amount compared by the comparing means 10'l is the base f!
If it is less than 1/2 of the value amount, the result of subtracting the offset amount from twice the analog input amount is generated as analog output R, and on the other hand, the analog input amount is larger than 1/2 of the reference value amount. In this case, the reference value amount is subtracted from twice the analog input amount, and the offset amount is further subtracted, and the result is generated as the analog output amount. In addition, if the analog input amount compared by the comparing means 501 is less than half of the reference value amount, the result of subtracting twice the analog input amount from the reference value amount and further adding three times the offset amount is calculated. Generated as an analog output quantity,
If the analog input amount is greater than half of the reference value amount,
The result of subtracting twice the analog input amount from twice the reference value amount and adding three times the offset amount is generated as an analog output amount.

[Embodiments of the invention]

An embodiment of the present invention will be explained with reference to FIG. 1 is a current input terminal of the electronic circuit 2. 3 is an N-channel MO3 transistor, the drain of which is connected to the current input terminal 1; Also, the gate and drain of the N-channel MOS transistor 3 are connected, and this transistor 3
is a so-called diode-connected transistor. The gate of N-channel MOS transistor 3 is connected to the gates of N-channel MOS transistors 5a and 5b.
a and 5b form a current mirror circuit. Nchi V
The drains of channel MOS transistors 5a and 5b are diode-connected P-channel transistors [7 channel MOS transistors 1
It is connected to the 2nd train. Zarani, P Channel M
The gate of OS transistor 12 is connected to the gates of P-channel MOS transistors 13 and 14, and transistors 12, 13, and 14 form a current mirror circuit. 20 is a reference current source that outputs a constant current, and is a diode-connected N-channel MOS transistor 21.
It is connected to the. N-channel MOS transistor 2
The gate of transistor 1 is connected to the gates of N-channel MOS transistors 10 and 11 via terminal 9, and transistors 20, 10, and 11 form a current mirror circuit.

N-channel MOS transistor 10 and P-channel M
The drain of the OS transistor 13 is input to a current comparator 16. The output of the current comparator 16 has its source connected to the drain of the N-channel MO81 to the transistor 11,
Its drain is connected to the gates of N-channel MO31 to transistor 15, whose drains are respectively connected to the drain of P-channel MOS transistor 14. Further, the output of the current comparator 16 is connected to the digital output terminal 8, and the double twin of the P-channel MO3 transistor 14 is connected to the current output terminal 6.
It is connected to the.

Reference numeral 30 denotes an offset current source that generates an offset amount, and is connected to a diode-connected N'J-P channel MOS transistor 31. The gate of the N-channel MOS transistor 31 is connected to the gates of the N-channel MOS transistors 1a and 17b and the N-channel MOS transistor 18 through one terminal, and the transistors 31°18.17a and 17b form a current mirror circuit. ing. Further, the drains and sources of the N-channel MOS transistors '17a and 17b are connected in parallel to the drains and sources of the N-channel MO31 to transistor 10. Further, the drain of the N-channel to 1oS transistor 18 is connected to the current output terminal 6, and the source thereof is grounded.

Comparison means 101 which compares the magnitude relationship between the analog input amount and one-half of the reference faffi and outputs a digital signal corresponding to the analog input amount includes N-channel MOS transistors 3, 5a, 5b, and 1o.

17a, 17b, 21, 31, P channel MOS transistors 12, 13, and current comparator 16. Analog output amount generation means 102 that generates an analog output amount according to the comparison result of comparison means '101 is an N-channel M
It has an OS transistor 11, 15, 18, 31 and a P channel MOS transistor 14.

Next, the operation will be explained. N-channel MOS transistors 3 and 5a forming a current mirror circuit,
Assuming that transistors 5b have the same characteristics, the same current as the current input from current input terminal 1 and flowing through the train of transistor 3 becomes the drain current of each of transistors 5a and 5b. That is, depending on the current input from the current input terminal 1, the diode-connected N-channel MO31 to
The voltage changes to 1 of transistor 3, but since the gates of N-channel MOS transistors 5a and 5b are connected to the gates of transistors 1 to 3, the same amount of current as the current flowing to the drain of transistor 3 flows to transistor 5a. It also flows to the drain of 5b. Therefore, a current twice the input current flows through the diode-connected P-channel MOS transistor 12. On the other hand, P channel MO
Since the 3I transistors 13 and 14 also form a current mirror circuit together with the P-channel MOS transistor 12, the same current as the drain current of the transistor 13, that is, twice the input current, flows through the transistors 13 and 13 according to the same principle as above. 14 drains. In addition, N-channel M forming a current mirror circuit
Similarly for OS transistor 21.10.11,
The drain current of transistors 10 and 11 is the reference current source 2.
The value is the same as the output current of 0. Also, an N-channel MOS transistor 31 forming a current mirror circuit
．． '18, 178, 17b by transistor 18.
Each of the train currents 17a and 17b has the same value as the output current of the offset current source 30.

The current comparator 16 is a P-channel MOS transistor 1
The drain current of No. 3 is compared with the sum of the drain currents of N-channel MOS transistors 10, 17a, and 17b, and N-channel MOS transistor 15 is opened or closed according to the comparison result. That is, N-channel MOS transistor 1
3 drain current is N channel MOS transistor 1
If the current is smaller than the sum of the drain currents of 0°178.17b, the output of the current comparator 16 becomes a low potential level (logical value O), causing the N-channel MOS transistor to pass. Accordingly, in the former case, the amount of current obtained by subtracting the drain current of the N-channel MOS transistor 18 from the drain current of the P-channel MOS transistor 14 is obtained from the current output terminal 6, and in the latter case, the amount of current obtained from the drain current of the P-channel MOS transistor 14 is obtained. The amount of current obtained by subtracting the drain currents of N-channel MOS transistors 11 and 18 from the drain current of is obtained.

The above operations can be summarized as follows.

B=O (if 2l1n-< Iref +21off) 1 (2Iin-≧Iref +2 Ioff
) Iout”=2Iin−−Ioff−
B-Iref (8) However, Iin'' is the current inflow amount from the current input terminal 1, 1 rcf is the current value of the reference current source 20, B is the output logic value of the digital output terminal 8, i 0U
T- is the amount of current flowing out from the current output terminal 6, and 1off is the current value of the offset current source 30.

FIG. 2 explains the operation expressed by equations 7 and 8. However, here, the input current ff1Itn of input terminal 1
It is assumed that an offset current value is added to the true input 1Iin in advance, and that i in-=lin+joff. When Itn changes linearly from O to 1ref/2, 1in” is Ioff as shown in 201.
It changes from (Iref /2+Ioff).

In this range, according to the conditional expression (7), B=O, and 1o
ut= is expressed by equation (8), so from 1off as in 203 (
I ref −1off).

Next, when lin changes from Iref/2 to Iref, l1n- changes from (Iref /2+Ioff) to (
Iref: )off). In this range, B=1 according to the conditional expression (7), and 1out - is from Ioff to (Ire
Repeat the change of f-1off> once again.

As can be seen from the above explanation, considering equation (9), (7
) formula is B=O(2Iin+21off < Iref +
In the case of 2 Ioff) 1 (2Iin+21off≧Ir13f +2 I
off) The conditional expression enclosed in parentheses in equation (10) is lin and I.
This is equivalent to the comparison expression of ref/2. Also, equation (8) is
Iout −= (21in-8-1ref)+I
off, but using the true current output amount l0ut expressed by equation (2), 1out ” = Iout + Ioff
(12). In this way, the offset range included in the input current and the offset range 1 to M included in the output current are
8 allows multi-stage connection of bit cells as described below).

An example of the configuration of an A/D converter using the circuit of this embodiment is shown in FIG. Z. Ng circuit blocks are connected in series via a current input terminal 1 and a current output terminal 6. In addition, the current input terminals 1 of the first pins 1 to 2 located on the input side are connected to an input current source 22 and a current source 3 having an output 11off equal to the offset current source 3Q.
Connected to 2. The reference current source 20 is commonly connected to the drain of a diode-connected N-channel MOS transistor 21 and the terminal 9 of all the pins 1 to 2. Further, the offset current source 30 and the drain of a diode-connected N-channel MOS transistor 31 and all bits are commonly connected to the terminal 19 of the circuit 2.

The operation of this A/D converter will be described below.

Below, the input current of the 1Mth bit cell is 3k: the digital output value of the 7Mth bit cell.
;Pull the current value of the current source 22. Drain currents of N-channel MO31 to transistor 10.11 of all cells and IN-channel MO3I-transistor 17a, '17b.

18 drain currents are equal to the reference current 1 ref and offset current 1oft, respectively, and the input current of the 1st pin 1 to cell is the sum of the true input current ■ and the offset current 1off, that is, I'1 −=I+Iof
Considering that f, the operation is as follows.

First, in the first cell 1 to cell, 2(I+Ioff) and (Iref +21off> are compared. If V, a comparison equivalent to the comparison between I and 1ref/2 is performed.

Here, if ■ is larger than [re4/2, B1 becomes 1, and vice versa, B1 becomes O, and the first digit of A/D conversion is determined. In this case, the output current is (2I+Iof
f), the latter s combination (21+ Ioff − Iref )
·bawl. In the second bit cell, these currents are doubled and 2 < 2 I+Ioff ) or 2(2I+
Ioff −I ref) is (Iref +21of
f). A simple calculation shows that this comparison is equivalent to comparing I with Iref/4 or 31ref/4. This comparison determines the second digit. Hereinafter, by sequentially determining Bk from the most significant bit B1 using the same procedure, the current value I of 22 becomes O.
The input current II'' of the first cell 2 changes linearly from i ref to Io as shown in (201a).
Consider the case where the value changes from ff to (lref+1off). First, in the first bit cell 2, 11- is l
When changing from 0ff to (Iref /, 2+ Ioff ), the digital output Bl (208a) becomes Ol.
1off). Then it = (Ire
f /2+Ioff ) to (Iref +Ioff
), digital output Bl (202a)
is 1.12-(201b) again from Ioff (l r
ef +1off). In the second bit cell 2, 11'' (201a) is increased by 1 from 1off to (l ref + 1off')/Jll
12 = (201b) changes from Ioff to (I
ref +Ioff) is increased twice until J-.
B2 repeats the change from O to 1 twice as shown in (202b), and the output of this bit cell 2 is 13 = (20
1c) from l off (I ref 11 off
) is repeated 4 times.

In the third bit cell 2, 11” (201a
) 7') < From Ioff (l ref +IoH)
Since l3-(201C) increases four times from l0ff to (l ref + Joff ) while changing once to , B3 = repeats the change from O to 1 four times as shown in (202c), and this bit cell 14 which is the output of 2
' is from l off to (l ref
The linear increase up to +Ioff> is repeated 8 times.

In this way, II ” is from l off (Iref
off), the output B of the k-th bit cell
k is 2j ・(lref /2K>+Ioff≦11′<(
2j+1> ・(If Iref/2K>+Ioff,
Bk = O(14) (2j+'l) ・(!ref/21')+ Iof
f≦11′<(2j+2> ・(Iref/2”)+
If 1off, Bk=1
(15). In this way, a digital binary number [BI B2 . . . BN ] proportional to the analog ill is obtained.

Here, considering equation (13), equation (14) and (
15) is exactly equivalent to equations (3) and (4).

That is, the conversion result obtained in the above embodiment is completely the same as in the conventional example, but as can be seen from FIG. 4, the input current to the bit cell 2 never becomes zero. Therefore, N
The current in the current mirror circuit formed by the channel MOS transistors 3.5a and 5b and the current mirror circuit formed by the P channel MOS transistors 12 and 13.14 does not become zero, and high-speed operation can be achieved.

Another embodiment of the invention will be described with reference to FIG. 1 is a current input terminal of the electronic circuit 2. Current input terminal 1 is connected to the drain of a diode-connected P-channel MO8I transistor 12. Zarani, P channel MOS
The gate of transistor 12 is a P-channel MOS transistor 13a.

The transistors 12, 13a, 13b, and 14a are connected to the gates of the transistors 13b, 14a, and '14b.

14b forms a current mirror circuit. 20 is a reference current source, which is a diode-connected N-channel MO
It is connected to the S transistor 21. N channel M
The gate of the OS transistor 21 is connected to the N-channel MOS transistors 10.11a and 11b via the terminal 9, and the transistors 21, 10.1'la,
l'lb is connected to the curl MOS transistor 31. The gate of the N-channel MOS transistor 31 is connected to the N-channel MOS transistor 17 via the terminal 19.
transistors 31 and 17a; connected to the gates of transistors 31 and 17b;

17b, 18a, 18b, and 18c form a current mirror circuit. P-channel MOS transistor 13
The drains of P-channel MOS transistor 13b and P-channel MOS transistor 13b are connected, and their trains are roughly connected to current comparator 1
It is input to the positive input terminal of 6. The drains of N-channel MOS transistors 10.degree. 17a and 17b are connected, and these drains are input to the negative input terminal of current comparator 16. The output of current comparator 16 is such that its source is N
N, which is connected to the drain of channel MOS transistor 11a and whose drain is commonly connected to the drains of P channel MOS transistors 14a and 14b.
It is connected to the gate of channel MOS transistor 15. In addition, the output of the current comparator] 6 is sent to the digital output terminal 8, which is connected to the P-channel MOS transistors 14a and 14.
The drain of b is an N-channel MOS transistor 11b.
.

It is connected to the drains of 18a, '18b, and 18G, and roughly connected to the current output terminal 6.

Comparison means 50'l includes N-channel MOS transistors 10.17a, 17b, 21.31 and P-channel MOS transistors 10.17a, 17b, 21.31.
S transistors 12, 13a, 13b and current comparator 16
and has. The analog output amount generation means 502 includes N channel MOS transistors 11a, 11b, 15, 18.
a, 18b.

18c, 31 and P channel MOS transistor 14a
, 14b.

Next, the operation will be explained. This circuit differs from the conventional example and the first embodiment described above in that the direction of the current that can be input to the input terminal 1 is the direction flowing out from the bit cell 2, and the direction of the current that can be output to the output terminal 6 is from the bit cell 2. This is the direction in which it flows into the interior. Therefore, the signs of the input amount and the output amount are positive in the outflow direction and inflow direction, respectively, contrary to the previous case. Also, in terms of expression, the following is also "input"
and use the word "output".

P-channel MOS forming a current mirror circuit
Transistors 12, 13a, 13b.

Assuming that 14a and 14b have the same shape, the same current input from current input terminal 1 and flowing through the drain of transistor 12 will flow through transistors 13a, 13b, '1
4a and 14b are drain currents, respectively. That is, according to the current input from the current input terminal 1, the diode-connected P-channel MOS transistor 12
However, since the gates of P-channel MOS transistors 13a, 13b, 14a and 14b are connected, each drain is connected to transistor 12.
The amount of current is the same as the current flowing through. Also, Nchi? which forms a current mirror circuit? channel MOS transistor 21.10.11a.

Similarly, regarding transistor 11b, the drain currents of transistors 10, 11a and 11b have the same value as the output current of reference current source 20. Similarly, N-channel MOS transistors 31 and 17a forming a current mirror circuit
, '17b, 18a.

Similarly, transistors 17a and 18b and 18c
, 17b and the transistors 18a, 18b, and 13G have the same value as the output currents of the off-celler 1 to the current source 30.

The current comparator 16 is a P-channel MOS transistor 1
The sum of the drain current of 3a and the train current of P-channel MOS transistor 13b, that is, 2iin and N-channel MO3I-transistor 10, '17a, 17b.
The sum of the drain currents, Zunawara (fret +2 Io
ff) is compared, and the N-channel MOS transistor 15 is opened or closed according to the result of the comparison v1. That is, 2)i
If n is smaller than (l ref + 21off), the output of the current comparator 16 will be at a low potential level (logical value O), cutting off the transistor 15, and in the opposite case, the output of the current comparator 16 will be at a high potential level. (fiii logical value 1), making the transistor 15 conductive. Accordingly, in the former case, the current value is obtained by subtracting the drain current of P-channel MOS transistors 1'4a and 14b from the sum of the train currents of N-channel MOS transistor 11a and N-channel MOS transistors 18a, 18b, and 18C. , that is, (Iref +31off -2Ii') is the latter case, N-channel MOS transistors 11a, 1lb, 18a, 18b.

The current value obtained by subtracting the drain currents of P channel MOS transistors 14a and 14b from the sum of the drain currents of 18C, that is, (2Iref +31off -21i
n'') is obtained from the current output terminal 6.

The above operations can be summarized as follows.

B=O (2Iin=≦1ref +2! Joff) 1 (2Iin > Iref +2 Iof
f) Iout j = (ref +3- Ir
ef +3 Ioff -211n- (17) However, lin" is the amount of current flowing out from current input terminal 1, I
ref is the current value of the reference current source 20, B is the output logic value of the digital output terminal 8, 1otJt= is the current inflow amount of the current output terminal 6, and 1off is the current value of the offset current source 30.

FIG. 6 explains the operations expressed by equations (16) and (17). However, here as well, it is assumed that the input current FI I in- of the input terminal 1 has an offset current value added to the true input 1Iin in advance, so that equation (9) holds true. When l+n increases linearly from O to Iref/2, Iin' becomes Io as shown in 204 in Figure 6 (1).
ff to (Iref /2+Ioff). In this range, according to the conditional expression (7), 8=0,
Iout = (l
ref + Ioff) to Ioff.

Next, when Iin changes from Iref/2 to Ire4, 1 in- becomes (Iref/2+Ioff >
It changes from (Iref 11 off). In this range, 8=1 according to the conditional expression (7), and 1OIJt- is expressed as (l rer +Io
ff ) to 1off again. As shown in Figure 6 (2), ■tn is (Iref +1o
ff ) to (l ref/2+Ioff), Iout- decreases from l off to (lref;
1off), B=1, l1n- becomes (Ir
ef /2+ Ioff ) to (Iref + 1o
ff ), Iout = 1off
It increases by another degree from to (l rcf + Ioff), and B=O.

As can be seen from the above explanation, considering equation (9), equation (
16) is B=O(21in+21Off <Iref +21
off) 1 (2Iin+2 Ioff≧I ref + 2
1 off) The conditional expression enclosed in parentheses in equation (18) is
This is equivalent to the comparison expression ref/2. Also, formula (17)
is 1out ”= Ircf 10B −fre “+
Ioff -2I 1n.

As an example using the second embodiment of the present invention, A
An example of the configuration of the /D converter is shown in FIG.

The N circuit blocks are cascaded via a current input terminal 1 and a current output terminal 6. It is also located closest to the input side. The current input terminal 1 of the first bit cell 2 is connected to a current source 32 having an output amount Ioff equal to the input current source 22 and the offset current source 30. A reference current source 20 is commonly connected to a train of diode-connected N-channel MOS transistors 21 and to terminals 9 of all bit cells 2. Also, offset current source 3
0 is commonly connected to the drain of the diode-connected N-channel MOS transistor 31 and the terminal 19 of all bit cells 2. Among the digital output terminals 8 of each bit cell 2, the digital output terminal of the even numbered bit cell 2 is connected to the terminal 100 via an impark, and the digital output terminal of the odd numbered bit cell 2 is directly connected to the terminal 100. The terminal 100 is for outputting the final conversion result of the A/D converter, as will be described later.

The operation of this A/D converter will be described below.

In the following, the input current 3k of the bit cell in Ik′ :k
When the digital output value DI appearing at the digital output terminal 8 of the l-th bit cell <:, the digital output value I appearing at the terminal 100 corresponding to the l-th bit cell: the current value of the current source 22. Here Dk=Bk (if k is an odd number) 100k (
When k is an even number) (20). N-channel MOS transistor 10.11a of all bit cells 2
, 11b and N-channel MOS transistors 17a, 17b, 18a, 18b, 18C (7
) that the train current is equal to the respective reference current I ref and offset current 1off, and that Equation (13)
Considering that the input current of the first bit cell 2 is the sum of the true input current 2 and the offset current 1off, the operation is as follows. First, in the −1st bit cell 2, 2(i+Ioff) and (lror+2Iofr
) are compared. That is, a comparison equivalent to the comparison between I and Iref/2 is performed. Here, if 1 is larger than Iref/2, B1 becomes 1, and in the opposite case, B1 becomes O. This value is directly output to the terminal 100 as the first digit D1 of the A/D conversion result.

At this time, the output current is when B1 is O (lref
ff -21), if 81 is 1 (21ref+)o
ff-21>. In the second bit cell 2'' these currents are doubled and 2 (Iref + Ioff
-21> or 2 (2Iref + Ioff -2
1> is compared with (Iref +2 Ioff>).

A simple calculation shows that this comparison is equivalent to comparing I with 1ref/4 or 31ref/4. The logical value of this result is inverted by the inverter 101,
It is output to the terminal 100 as the second digit D2 of the A/D conversion result. By sequentially determining [)k starting from the most significant bit D1 through such a procedure, an A/D conversion result can be obtained.

The above operation will be explained with reference to FIG. The current value I of the current source 22 changes linearly from O to 1ref, and the input current of the first bit cell 2 becomes (204a>(7)):
Assume that the value changes from l0ff to (1off +Iref). First, in the 11th bit cell 2, 11
= changes from 1Off to (iref/2+Ioff), B1 is O and this is directly output to the terminal "100 as digital output D1 as shown in (205a). Also, the output current of this bit cell, that is, the second bit cell 2 input current 12'' (204b) is (I
ref +Ioff ) to 1off. Next, 11' changes from (lref/2+Ioff) to (1re
f + Joff ), B1 and Dl become 1, and I2 = (204b) becomes (Iref
+Jiff) to loff. In the second bit cell 2, I1' (204a) is I
While increasing once from off to (l ref + Ioff ), I2 (201b) becomes (Ircf + Iof
Since it decreases twice from r ) to l off, 12
= decreases by 1 as shown in Figure 6 (204').
Repeat the change from to O twice. This is inverter 10'
It becomes a digital output D2 through l and becomes the digital output D2 in Fig. 8 (205b).
A two-time O to 1 change appears at the terminal 100, as shown in FIG. Moreover, I3, which is the output of this bit cell 2, is shown in Fig. 6 (
Ioff per decrease of 12” like 206N
For two linear increases from to (Iref +Ioff) and one increase of 11",
Repeat the increase 4 times as shown in C). In the third bit cell 2, 13' (204G) changes from Ioff to (lref+(
off ), B3 increases from O to 1
Repeat the change of 4 times, and digital output D3 (205c
) to make the same change. In addition, I4'', which is the output of this bit cell 2, is (Irer
Repeat the linear decrease from +1off to )loff 8 times. In this way, 11” is from 1off to (i
Dk generated from the output Bk of the k-th bit cell 2 is 2j ・(Iref /2K) ■off≦■1′＜
(2j +1) ・(Iref /2 > +Io
In the case of ff, Dk = O(21) (2j+1) ・(Iref /2') + Io
ff≦■< (2j+2) ・(Iref /2”)
In the case of 10 Ioff, Dk=1,
(22). In this way, a digital binary number [DI B2 . . . DN ] proportional to the analog ff1I is obtained.

Here, considering equation (13), equation (21) and (
22) is exactly equivalent to equations (3) and (4). That is, the conversion result obtained in this embodiment is completely the same as in the conventional example, but as can be seen from FIG. 8, the input current to the bit cell 2 never becomes zero. Therefore, the P-channel MOS transistors 12, 13a, 13b, 14
The current of the current mirror circuit formed by a and 14b does not become zero, and high-speed operation is achieved by 1q.

As explained above, the input current value and output current value of the bit cell are the values obtained by adding the offset current to the true analog current value, and the input offset current value and the output offset current value are made equal, This enables multi-stage cascade connection of bit cells. Further, the value of the current flowing through the current mirror circuit does not become zero regardless of the amount of analog input to the A/D converter.

Note that the above embodiment is an application of the present invention to the configuration of an A/D converter in which the A/D conversion result is determined in a chain from the most significant digit, but the cell to pin 1 is not operated in a pipeline manner. Even when applied to a so-called pipeline type A/D converter (for example, LDSP Group, Miki, Kumamoto, patent A-9105 filed on September 16), a high 1fJa can be achieved.

In addition, current mirror circuits are composed of a diode-connected transistor and a single transistor paired with it, but it can be used as long as it is a functional circuit in which the input current and output current are equal or have a predetermined ratio. ,for example,
A Wilson current mirror circuit or the like may also be used.

〔Effect of the invention〕

As described above, according to the present invention, when the analog input amount compared by the comparison means is less than half of the reference value amount, the result of subtracting the offset amount from twice the analog input input or the reference value Subtract twice the analog input amount from the amount and add three times the offset amount to generate the result as the analog output amount, and - on the other hand, the analog input amount is half of the reference value amount.
If it is larger, calculate the result by subtracting the standard value amount from twice the analog manpower port and then subtracting the offset amount, or subtract twice the analog manpower port from twice the reference value amount and then subtracting the offset amount. Since the configuration is such that the result of adding 3 times is generated as the analog output amount, the offset amount included in the input current and the offset amount included in the output current are equal, so that, for example, the current of a current mirror circuit can be changed regardless of the analog input amount. The value does not become zero, and as a result, the analog/digital conversion speed can be improved.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of a bit cell according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of the operation of a bit cell according to an embodiment, FIG. 3 is a configuration diagram of an analog/digital conversion method according to an embodiment, and FIG. The figure is a diagram explaining the operation of the analog/digital conversion method according to one embodiment, and FIG. 7 is a configuration diagram of the analog/digital conversion method according to the embodiment of Haku.
FIG. 8 is an explanatory diagram of the operation of an analog/digital conversion method according to another embodiment, FIG. 9 is a circuit diagram of a conventional bit cell, FIG. 10 is an explanatory diagram of the operation of a conventional bit cell, and FIG. 11 is a diagram of a conventional analog FIG. 12 is a diagram illustrating the operation of an A/D converter using the conventional analog/digital conversion method. 101.501... Comparison means, 102,502
...Analog output amount generation means.

Claims (1)

[Claims] Comparing means for comparing the magnitude relationship between the analog input amount and one half of the reference value amount and outputting a digital signal corresponding to the analog input amount, and according to the comparison result of the comparing means. and an analog output amount generation means for generating an analog output amount, and when the analog input amount compared by the comparison means is one-half or less of the reference value amount, the analog output amount generation means generates an analog output amount. The result of subtracting the offset amount for the elements of each means mentioned above by twice the amount of
The result of multiplying is generated as an analog output quantity, and on the other hand,
If the analog input amount is greater than half of the reference value amount,
The result is the result of subtracting the reference value amount from twice the analog input amount and then subtracting the offset amount, or the result of subtracting twice the analog input amount from twice the reference value amount and then adding three times the offset amount. An analog-to-digital conversion method characterized by generating the result as an analog output quantity.