JPH02226833A - Clock phase matching circuit - Google Patents

Abstract

PURPOSE:To produce a clock for securely reproducing received data by dividing one cycle of a received clock into three areas and detecting which area the received data is in, and controlling the received clock. CONSTITUTION:The clock phase matching circuit consists of a pattern generator 1, a differentiating circuit 2, AND gates 3-5, R-R flip-flops 6 and 7, an AND gate 8, a clock control circuit 9, a received data input terminal 10, a received clock input terminal 11, and a received clock output terminal. Then one cycle of the received clock is divided into three areas (window) to detect which area the rising clock of the received data containing jitters, etc., is in, thereby controlling the phase of the received clock. Consequently, the clock which is in excellent relation with the received data is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application] This invention relates to nine clocks and data reproduction in synchronization with received data of a wired communication interface circuit.

[Conventional technology]

Figure 3 is '1' if you line up! f It is a nine-clock phase matching device shown in Ura Sho 63-178042, and l in Figure 1.
311 is a bidirectional differential circuit, and (A) is a unidirectional differential circuit.

1 clock generation circuit for multi-point sampling, 134J is an AND gate. (To) is a counting circuit, - is a frequency control pulse generation circuit, (B) is a comparison circuit, (To) is a threshold value. There is a flip-flop on the J- side, a KXOR gate, (40 data signal input terminals, (43 is a continuous shooting clock signal input terminal) and a phase matching clock output terminal.

Next, the operation will be explained. Data signal input terminal 14r
The nine data signals input from J are differentiated by a bidirectional differentiator an. Further, the nine clock signals inputted from the clock signal input terminal are differentiated by the two-sided parallel circuit. By ANDing these two differential pulses (T1, T2), one phase shift is determined and the number is counted. 9 by outputting a control signal (T4) when a certain amount of compensation is reached.
The phase matching clock signal is inverted by KXOR gate +4Q to match the phase of data and clock.

[Problem to be solved by the invention]

Conventional clock phase matching circuits are configured as shown above, so if the received data contains jitter etc., even though the phases of the clocks 7 and 9 match, the jitter 9 There is a problem where it is determined that the phases do not match.

This invention was made in the ninth attempt to eliminate the above-mentioned interference, and its purpose is to provide a circuit that can reliably detect the phase relationship with the received clock even for received data containing jitter. do.

[The tth means of shouting out issues]

The clock phase determination circuit according to the present invention divides the reception clock period into three regions, detects in which region the reception data is present, and controls the reception clock.

[Operation] The clock phase matching circuit in the invention divides one period of the received clock into three regions (windows).

The purpose is to open the phase of the receive clock by detecting in which region of the clock the rising edge of the receive data containing jitter etc. is present.

A clock having a good phase relationship with the received data can be obtained.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

1 to 219K'', (1) is a pattern generator 4, (2) is a differential circuit, (31, +41.
+51 is ant game), +6+, (7) is an R-R clip flop, (8) is an AND gate, 191 is a clock control circuit, fin is a reception data input terminal, nυ is a reception clock input terminal, 732 is a reception This is a clock output terminal.

Next, in FIG. 5, which explains the operation of the present invention, one part of the reception clock is divided into three regions (Wl, Wl, Wst). These Wl and Wl are regions (windows) located before and after the rising edge of the receiving clock.The data input from the receiving data input terminal III generates a rising edge (S4) in the differentiating circuit (2), and the rising edge (S4) of the receiving clock is generated. Determine which area should be ranked 1 (5, 4, 5). If the reception clock fluctuates before and after the rising edge with jitter, both the 9 discrimination signals (S5) and (S6) will be logic "1", and by taking the AND gate (8), it can be easily You can know the location of received data.

By shifting the phase of the reception clock by a predetermined amount using the detection signal (S7), it is possible to create a clock that can reliably reproduce received data.

In the above embodiment, one period of the reception clock is divided into three regions, but the number of regions may be increased.

The transmission clock may be used in seconds instead of the reception clock when the transmission and reception cycles are fixed in the transmission line interface reception circuit.

Furthermore, this circuit may be useful for determining the phase of a signal containing jitter.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to easily determine the phase relationship between the received data containing jitter and the received clock, which has the effect of reducing r-time reproduction errors.

By providing a large number of divided regions, a more accurate phase can be determined.

4. f of the drawing! Brief Description FIG. 1 shows clock phase matching according to an embodiment of the present invention.
A block diagram showing the circuit, FIG. 2 is a timing chart explaining FIG. 1, FIG. 3 is a block layer showing a conventional clock phase matching device, and FIG. 4 is a timing chart explaining FIG. 3. In, (1) is a pattern generator, (2) is a differential circuit, +3), 14),
+51. +8) is an AND gate, 16).

()) is a 8-R flip-flop, and (9) is a clock side flip-flop circuit.

In each figure, the same reference numerals indicate the same or corresponding parts.

Masuo Oiwa, a representative Indian No. figure 1! No. figure hand Continued Supplementary Positive book 3. Person who makes corrections given name name (601) Mitsubishi Electric Corporation Representative Mamoru Shiki Ya 4, generation Reason Man pole Target of correction I.J. Detailed description of the invention in the specification 6゜ Contents of correction The specification is amended as follows.

The drawing in Figure 2 will be corrected as shown in the attached sheet.

Claims (1)

[Claims] In the transmission line interface circuit, there is a pattern generator that divides one period of the received clock into three regions (windows), a differentiator circuit that creates the rising edge of the received clock, and an AND gate that takes the logical product of each region and the received clock edge. A clock phase matching device comprising: an S-R flip-flop indicating region passing; an AND gate indicating passing two regions; and a clock control circuit controlling the phase of the clock by the output of the AND gate. circuit.