JPH02226842A - Cluster interface controller - Google Patents

Abstract

PURPOSE: To make a controller high in performance by providing a node interface logic device, a ring path interface logic device, a link interface and a shared logic block. CONSTITUTION: The shared logic block having FIFO buffers 32 and 34, an output link interface 36, an input link interface 37 is sheared by two separated blocks 40 and 42 which supply an operation made. For example, if a node controller mode is selected by a mode selecting line 43, the node interface logic device 40 is activated, and interface pin 44 is utilized thereto, and the ling path logic device 42 is disenabled. Thus, an improved LAN controller which can be set so as to be connected to many different interfaces and operated in many different modes in a network.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to data processing apparatus, and more particularly to apparatus for controlling message transfer in a local Elijah network.

[Background of the invention]

A local area network, or LAN, is
A data communications system that allows many independent devices to communicate with each other within a moderately large geographic area. The abbreviation LAN is used to describe a network in which most processing tasks are performed by workstations, such as personal combinatorial computers, rather than by shared resources.

A LAN consists of desktop-workstations that perform processing tasks and serve as a user's interface to the network.

A wiring system connects the workstages, and a software-operating system handles the execution of networked tasks.

In one prior art, a nine local area network architecture based on an active star topology is presented. The nodes are attached to the star's hub via decentralized communication links. Messages transferred between nodes are processed by message arbitration (ar
bityati@n) and a hub capable of routing. Unlike a conventional bus topology, ie, a ring topology, each node of an active ring star receives only the messages that are scheduled for it. Message routing is accomplished by the destination address in the message header. The destination address is unique for each node and provides a means for the hub to maintain independent inter-node O communications.

A number of ring controllers are connected together in a closed ring to form a star hub. Node-controllers located at source and destination Φ nodes control the flow of messages to and from the nodes. Ring controllers and node controllers perform many of the same internal functions. However, they outwardly connect to different network media, one to the parallel ring e-bus in the case of a ring controller or one to the DMA type I10 path of the processor in the case of a node controller. There is. The advantage of having only one component is for ring-controllers and node controllers that can operate in different modes depending on the component's position in the network.

However, it is an object of the present invention to provide an improved LSI that can be connected to many different interfaces in a network and configured to operate in many different modes.
AN: 1 controller is provided.

[Summary of the invention]

An object of the present invention is to provide a node interface logic device;
A cluster with a ring-like bus interface logical unit and a link interface and shared logical unit.
This can be accomplished by providing an interface controller. The shared logic unit includes an output FIFO buffer connected to the output link interface and a FIFO buffer connected to the input link interface. The mode selection device selects either the node controller operation mode or the ring φ controller operation mode. A device responsive to the selection device connects a first set of I10 interface pin functions and timing corresponding to the first mode of operation to the internal shared logic device and selects a second mode of operation according to the selected mode. The second set I1 corresponding to
0 interface pin function and timing.

Embodiments of the present invention will be described below with reference to the accompanying drawings.

〔Example〕

FIG. 1 shows a block diagram of a Nine-Eliya e-network incorporating the controller of the present invention. There are two ways to interface nodes 2 and 6 to hub S. IEEE Standard 802.3:
A node (hereinafter referred to as 802
．． 37-code) is based on the XEEE standard 802.3.
and can be attached directly to the hub via one of several different 802.3 media links that may be used. High Performance The node is using a cluster number interface controller (CLIC) for the selected node 11 controller mode. The node-mount controller provides high bandwidth links and supports low latency protocols.

IEEE802.3 link own interface Each CLIC8, 10, 12゜14.16, shown in Figure 1
18.30 has two basic operations:
The Snawachinode controller can work in tube mode and ring controller mode. Furthermore, 1
The selected ring controllers 12
It is set to operate in mode.

In FIG. 2, the common logic block with FIFO buffers 32, 34, output link interfaces 36, and input link φ interfaces 3T is
It is shared by two independent blocks 40, 42 that supply the modes. When node controller mode is selected by mote select line 43, node interface logic 40 is activated, interface pins 44 are used for it, and ring bus hub logic 42 is disabled. enabled. The function and timing of the I10 interface Φ pin depends on the selected mode.

NODE CONTROLLER OPERATION MODES In FIG. 3, the node controller mode is selected by mode selection line 43.

Node interface logic 40 is activated and places input data instruction register 50 in the path between the data input pin and output PIFO 32 and places output data instruction register 52 in the path between input PIFO 14 and the data output pin. .

Memory instruction map control/status interface node controller mode μ, address register 54
and control/status registers 56 and whose signals control them. Either the 16 or 32 bit data bus is
10 mode select 43 along with the Kl 6736 path select pin (not shown).

Once the CLIC is reset and basic mode is selected, node controller operations are controlled by writing to control/status register 58. These are the node controller operations 1IJllt, 6x sets of memory and map registers.

The control/status interface is a RAM memory
It is similar to Inter 7 Eighth. This can be read and written in the register to be used selected by the address line to address register 54. To simplify decoding and minimize the number of pins required, three address lines and one
Access registers using only one chip select.

All accesses are two clocks long and are synchronized with the bus clock T.

All registers in the node-controller are of length 3
With 2 bits, messages are transferred in 32-bit φ words. A 16-bit bus operation divides a word operation into two 16-bit overages. K to complete a register access must have two halves, with the second half completing the operation.

Interrupts Interrupts are used to signal various events to protocol processor 2, such as when a message arrives, when an error occurs, when output data is needed, and so on.

Formatting and processing options are
Provided to handle various interrupts. One or two interrupt lines can be used, with the input and output channels sharing a single line or each using separate lines. The default mode is single interrupt.

The message is the node Φ controller! from the protocol processor 2 to the node controller 6 as successive columns of words on the 10 bus 17. The protocol processor controls the transmission of one message without interruption. 32 bits! Only full words can be transferred in 10 bus mode, and only half words in 16 bit contention mode. Metsuryuji whose length is less than an integer number of words are
Processed by control/status registers in the node controller. The message length is used to determine the actual number of bytes transferred and transmitted on the link when initiating output. If the message length is less than an integer number of words, then ! The last word transferred on the 10 bus (ie, the half-0 word) is truncated at the node exposure controller.

When a message is received, the full word containing the last byte of the message is transferred to the node controller. The input status register indicates the number of valid bytes in the last word.

All data alignment, message assembly and disassembly is the responsibility of the protocol processor with its DMA controller. node·
The controller specifies the actual message length at the start of output and signals the number of bytes in the last word of the input transfer status.

The DMA interface 17 for the Prodor processor uses two sets of DMA request/accept signals. One is for input and the other is for output. The DMAIJ quest signal of the node/controller color is
Indicates that data transfer is requested and the protocol
DMA in the Processor: An acknowledgment from the controller indicates that the request has been accepted.

The timing of the actual transfer is controlled by the write/read signal from the DMA controller and the ready signal from the node controller. The input and output logic units are completely independent and allow full deplex operation. Once a DMA transfer is received, the entire data transfer to or from the node-controller requires two clock cycles. Therefore, vibration line transfer can be performed.

The node controller 10A bus 17 is synchronized with the bus clock lT of the subsystem shown in FIG. The bus clock is derived from the 2x clock supplied to all parts, and the bus clock is shown as a reset signal to the parts and subsystems. All output and input timings are shown as the bus clock edges low.

The DMA request line is the only exception since it must be deasaarted for the assertion of the DMA request. Two alternatives are provided for handling the start of a transfer cycle. Each alternative has its own I10 pin pair and another pair must be disabled. They are disabled by connecting the pins to Vcc K.

No more than one signal is used to interface to the bus signal node interface 40. All inputs are sampled at the falling edge at the end of the bus cycle,
Full power will be driven after the falling edge unless special care is taken.

CLK: Entering car I! Cycle WRe: Control signal used to initiate a write transfer to the incoming car node contention controller. WRe is 1
asserted in one bus cycle, the data is
Transferred to node controller on next bus cycle. (Must be connected to Vcc if ADS# is used e3) RD$: Control signal used to initiate a read transfer from the incoming car node cooler.

RD is asserted for one bus cycle and the node controller returns data on the next bus cycle. (VccK if ADS$ is used
Must be connected. ) Ready: A control signal from the node controller used to terminate an outgoing read or write transfer. Ready # is WRe,
It is asserted in the bus own cycle following vc D * or another control signal AD8+. Two cycle timing intersections may be interfered with under mode control for pipelined DMAK requiring different timing to complete a transfer.

DREQ0. DREQI: Output - Two DMA request number lines are provided. One for the input channel and one for the output channel. The timing for the signals varies depending on whether pipeline requests are enabled. DREQn# is
It is asserted synchronously with the clock, but is deasserted asynchronously in non-pipelined mode.

DACKQ$, DACK1+: Inputs - Two DMA output inputs are paired with their corresponding DREQn1k signals. Data transfers can occur clock cycles after DACKn+ is asserted. wu#, RD# f or kD8# starts actual data transfer after DACKn* is asserted 7 times.

ADg Reference: Input - Node; Control signal used to initiate a write or read transfer on a controller. W
/R$%' (when used with respect to it, it replaces the WR$ and RD value signals.

(Must be connected to Wee if wB reference and RD+ are used.) W/R reference: AC3 to initiate input-pass cycle.
A control signal used to identify a bus transfer as a write or read, if a reference is used. (Must be connected to Vce JC if WRI and RD# are used.) CB#: Chip selection used to select the node controller when incoming memory access is performed. C8+# is typically generated from a higher order address line and is used as a transfer start control signal (W) at the trailing edge of a bus cycle.
End with R+, RD# or ^DS$). Both C8# and the transfer control signal must be asserted to form a memory φ map transfer.

Addr2 4 :Input - These address lines select the register t&aX10 port to be accessed in a map transfer. Since each register is 32 bits long, the address bits start at 2 instead of 0. The address line is cs41
and the falling edge of the bus cycle.

Addrl: input - this address - bit is 1.1
Sampled only if 6-bit mode is enabled. When transferring from the register to the welfare register,
The higher order half word must be transferred first, followed by the lower order half word.

The second cycle begins loading the registers.

Data O~31: Bidirectional data line used to transfer information to and from the input/output carnode controller.

! nt O~l: Output - Two interrupt signals are provided to indicate to the protocol grossenete a change of state in the node-controller. Depending on the selected mode, one or both interrupts are used.

Two types of registers are used in the register definition node controller: direct access and indirect access registers.

Direct registers are used to handle normal message flow. Indirect registers are used for initialization and diagnostic registers. Three word address lines (ADDR4-2) are decoded and directly access registers. Direct register number 6, called indirect address register, is the second
Used to address levels.

This second level addressing is invoked when indirect registers or direct registers are accessed. This allows further access to internal registers without connecting multiple address lines. The register addresses and names are as follows:

Control/Status Register Direct Access Register Indirect Access Register In FIG. 1, the connection 18 between the node controller 6 and the hub 9 is called a link.

Hub link 18 has CLIC6 for the selected node controller mode and CLIClo for the selected ring controller mode at hub 9.
We need a node consisting of .

Hough Link supports high speed full duplex operation with full message buffering and flow control.

Link/Connection: 82501 Manchester Encoding/Decoding Component and TAXI
Off-the-shelf components such as FDDI interface 11:2 components
) using the media interface. These components are special to interconnect them! 10 interfaces have different signaling and data formatting requirements.

Flow control of the two CLIClsI'l terminating the link is maintained by transmitting control information in both directions. When a message is transmitted over a link, the bucket)
K is formed and a header is added to the message regarding control information. The header is generated by the north CLIC and removed by the CLIC receiving it at the other end of the link.

Message packets are transmitted simultaneously in both directions over a full duplex link.

Control information for messages transmitted in one direction is placed in a bucket (K) that flows in the opposite direction.

Flow control can maximize the use of available bandwidth while reducing the input FIF at the CLIC receiving the message.
Used to prevent O overrun. This mechanism minimizes shock on links that span long distances or operate at very high performance levels. In either case, an infinitesimal amount of messages can be transported on the link at any time with respect to the size of the available buffer.

Control information and smaller packet-sizes can eliminate pipeline effects on bandwidth usage and latency.

The CLIC operates in a synchronous physical environment, whether it is configured as a ring controller or as a node-controller.

The ring controller at the hub receives the same synchronous clock that drives the internal logic and provides a reference for the ring φ bus.

The node controller uses the bus fist clock,
Drives the internal logic device and! 10 provides a reference for bus timing. However, link-interface a, CL
It is asynchronous with the internal logic device of the IC and operates at a higher frequency than the internal logic device.

The media interface is responsive to provide synchronization signals to outgoing messages from the CLIC and to provide synchronization on large signals. A suitable example, 82501, is
CLICK supplies the transmission lock that CLIC uses to time outgoing data. 82501 is
Encode the data and send it to the line Φ driver component. Upon receiving data, it decodes the data from the input signal and provides it to the CIdC along with the receive clock.

The CLIC input and output ports operate separately and independently of each other. Two sets of input and output boats are provided. The serial input/output port provides a direct 82501 interface. The parallel manpower/output boat directly interfaces with the TAXI component.

The 802.3 link uses the same interface, but uses different internal logic to handle CLIC mode.

In Figure 3, input FIFO 34 and output FIFO 32
collects data from the nodes via the link write interface before it is transferred to the ring bus 24 and buffers it to receive data from the ring bus at ring bus speed. Broadcast fist buffer 31 is used to receive and buffer message-broadcasts from one node to several nodes.

The ring bus can be used to transfer data packets between other Ring Fist controllers while the next packet of messages is collected at the Ring controller's input yxro 34. A large FIFO allows data to be collected at the source node controller until the destination path is free to accept the data.

Each ring controller has an input port and an output port that are used to receive packets from an upstream ring controller and send packets to a downstream ring controller. These are unidirectional boats, one for receiving and one for transmitting. Data is transferred from each output port to each input port on each ring bus cycle. The monitor signal M is used by the next monior ring controller to identify packets with errors.

Ring Packet Header The packet-header is constructed by the ring controller at the source of the packet. The header information is used for ring-controller communication and is not included in messages transmitted to the nodes. The packet header contains the source ID of the ring-controller color and the destination address of the message.

A 5-bit coded packet identifier defines the function of the packet and how the remaining fields are interpreted. New packets are sent to the bypass FIFO (first-
1n first-out) registers 35 and control logic 41 via a "register insertion" mechanism. New packets are transferred to the next ring-controller, while incoming packets via the ring-bus 24 are stored in the bypass PIFO 35.

A controller in one hub is identified as a ring controller by asserting ring monitor pin 38 before reset 311 is deasserted. It must be asserted by the last clock that reset is asserted. The controller O-ring monitor pin 1, shown as ring monitor, is
The hub of the ring hub it is attached to! Used to input D. The hub ID is sent to other ring controllers.

vinegar? The cluster interface controller works as either a node controller or a ring fist controller.
The CLxe monitor stop pin 43 is asserted while the tll is asserted and before the time reset 39 is asserted.

It identifies the use of the I10 pin for the selected mode, thereby identifying other valid inputs during reset.

Ring Monitor The ring monitor 12 in FIG.
Used to adjudicate messages.

1) Provides a central coordination point for the source that requests the broadcast of messages. Transfer requests regarding broadcast conference messages are made to the broadcast monitor. The Ring Controller queues broadcast requests as if they were normal requests, as any destination-transferring Ring e-controller does.

Then it starts the actual transfer and interacts with the source controller. Other ring controllers examine the broadcast font encoding in the packet header and copy the packet to their broadcast buffers.

As mentioned above, although the present invention has been described based on the present embodiments, it will be obvious to those skilled in the art that the present invention is not limited to these specific descriptions and can be modified in various ways.

[Brief explanation of the drawing]

FIG. 1 is a functional block diagram of a local area network having the present invention, and FIG. 2 is a functional block diagram of a local area network having the present invention. The functional block diagram of the AO interface φ controller, Figure 3, is
FIG. 3 is a detailed block diagram of the interface controller shown in FIG. 2; 2.31----Protocol Processor, 6°30.
18---Node controller, 10°14.16
・1・Ring controller, 12Φ・War・Ring Φ
Monitor, 17, 19...Gallery hub interface, 3
1...φ broadcast buffer, 32 fists, 11 fists, output FIF0, 34...input FIF0.36 @
...Input link interface, 37・a*Jkarinkkenifinterface 0φφφ・node interface 7
Eighth, 42--ring bus working interface,
43...Φ mode selection, 44.45--@hayashi sharing hint, 50...φ input data register, 52 rumor 1111
11 output data register, 54 . . . φ address register, 56 . . control/status register.

Claims (1)

[Claims] A node interface logic device, a ring bus interface logic device, a set of input pins, a set of output pins, and the node interface logic device and the ring bus interface logic device. an output FIFO buffer connected to the face logic device and connected to the output link interface; and an input FIFO buffer connected to the input link interface.
a shared logical unit containing a buffer; and when set to the first state, selects the node controller mode of operation; and when set to the second state, selects the ring controller mode of operation; a mode selection device for selecting, the node interface device being responsive to the selection device, when the selection device is set to the first state;
activating said pin with respect to said node interface device; said ring bus interface device being responsive to said selection device to cause said ring bus interface device to A cluster interface controller for activating said pins with respect to interface devices.