JPH0222717A - Computer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] The purpose of this invention is to provide a computer having a direct memory access controller (hereinafter referred to as a DMA controller) that can shorten the time required to initialize memory when the power is turned on. , a latch means that outputs a clear request signal to the DMA controller and also outputs an H level signal to the AND circuit, and when the power is turned on, the DMA controller
A writing means for writing the first address and the last address of the memory to be initialized is provided, and a forcing circuit for forcing the data hash to the memory to be 0 at the output of the AND circuit, and the DMA controller is arranged so that the clear request signal is Input,
When the first address to be initialized and the R Hiragi address have been written, an H level signal indicating completion of preparation is sent to the AND circuit, and the forcing circuit forces the data bus to the memory to be turned off.
The liquid memory is configured to initialize the memory by sending a write signal to the memory and sequentially outputting addresses from the first address to the last address to be initialized via an address bus to the liquid memory.

[Industrial application field]

The present invention relates to a computer having a DMA controller and memory, which can shorten the time required to initialize the memory when the computer is powered on.

[Conventional technology]

A conventional example will be explained below using figures.

FIG. 3 is a diagram showing a conventional memory initialization program.

In a conventional computer, when the power is turned on, the memory, for example, r
Each 1 from o 000J address to rl 000J address
The bytes were initialized using the program shown in FIG.

That is, in step 1, the first address roOOOJ to be initialized is written to the X register for address instruction, and in step 2, the hexadecimal number "0" is written to the A register for data storage.
0” is written.

Next, in step 3, the content "00" of the A register is written to the address r0000J specified by the X register.

Next, in step 4, add +1 to the value in the X register,
Proceed to step 5 and the value in the X register is rl 001J
If it is smaller, the process returns to step 3, and the operations from steps 3 to 5 are repeated until the value in the X register becomes rloooJ, and when the value in the X register becomes rlOOIJ, the process proceeds to step 6 and ends.

In this case, each step usually takes two cycles, so it takes a total of 6010 cycles, which is a lot of time.

[Problem to be solved by the invention]

As explained above, the conventional method has the problem that it takes a lot of time to initialize the memory when the power is turned on.

An object of the present invention is to provide a computer that can shorten the time required to initialize the memory when the power is turned on.

[Means to solve the problem]

FIG. 1 is a block diagram of the principle of the present invention.

As shown in Figure 1, when the power is turned on, the DMA controller 1
a latch means 3 which outputs a clear request signal to the AND circuit 4 and outputs an H level signal to the AND circuit 4, and when the power is turned on;
A writing means 5 for writing the first address and the last address of the memory 2 to be initialized into the DMA controller 1, and a forcing circuit 6 for forcing the data bus to the memory 2 to 0 using the output of the AND circuit 4. establish.

Then, when the clear request signal is input and the initialization start address and final address are written, the DMA controller 1 sends an H level signal to the AND circuit 4 to indicate completion of direct memory access preparation, and the forcing circuit 6 , the data bus to the memory 2 is forced to O, and the data bus to the memory 2 is
A write signal is sent to the address bus, and addresses from the first address to the last address to be initialized are sequentially output to the liquid memory 2 to initialize the memory 2.

[For production]

According to the present invention, when the power is turned on, the launch means 3 outputs a clear request signal to the DMA controller 1 and outputs an H level signal to the AND circuit 4.

When the power is turned on, the writing means 5 writes the start address and the end address for initializing the memory 2 into the DMA controller 1.

Then, the DMA controller 1 sends an H level signal to the AND circuit 4, uses the output from the AND circuit 4, uses the forcing circuit 6 to set the data bus to the memory 2 to 0, and also writes data to the memory 2. It outputs a signal, and sequentially outputs addresses from the first address to be initialized to the final address via the address bus.

Therefore, each time an address from the first address to the last address is sent, the memory 2 initializes the corresponding address part to 0.

In this case, it will be initialized when the address is sent, so
One step corresponds to one cycle. Therefore, the address is 100
If it is 0, it will take 1000 cycles to initialize.

It takes about 20 cycles to write the initialization start address and final address to DMA controller 1, so
The total number of cycles is 1020, and the initialization time can be significantly shortened.

〔Example〕

An embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 2 is a block diagram of a computer according to an embodiment of the present invention.

The ROM 7 in FIG. 2 stores a program that writes the start address and end address for initializing the memory 2 to the DMA controller 1 when the power is turned on.When the power is turned on, the processor 8 uses this program to Write the start address and end address to be initialized into the DMA controller 1.

On the other hand, the launch unit 3 issues an initialization request to the DMA controller 1, and also outputs an H level signal to the AND circuit 4 (if the initialization request is an H level signal, this is used).

Then, the DMA controller 1 issues a stop command to the processor 8 as in normal DMA control.

As a result, the processor 8 releases the bus after the current cycle ends, and sends a bus release signal to the gate 9.
and the bus, and sends a lotus release signal to the DMA controller 1.

Then, the DMA controller 1 sends an H level signal to the AND circuit 4 to indicate that the preparation is complete, and the forcing circuit 6 causes the memory 2
For example, eight of the data buses connected to the terminal are forcibly grounded to O.

At the same time, a write signal is sent to the memory 2, and a start address to be initialized via the address bus is output from the address bus.

Then, a hexadecimal number "00" is written to the start address of the memory 2, for example, address "0000", and the memory 2 is initialized.

Next is address roo01J, first address is ro002J, etc.
The address signal of ... is the final address, for example rlooOJ
It is output and initialized continuously until it reaches the address.

When the initialization up to the final address is completed, the DMA controller 1 sends a DMAEND signal to the launch unit 3.

The latch unit 3 releases the launch with this END signal, drops the initialization request signal, completes the clearing work of the memory 2,
At the same time, the forcing circuit 6 stops pulling the data bus to ground.

In this case, it takes about 20 cycles to write the first address and the last address to be initialized to the DMA controller l, and it is initialized when the address is sent, so if the address is 1001, it will be initialized. It takes 1001 cycles to do this, and the total is 1021 cycles.

Therefore, initialization can be performed in about 1/6 of the cycle required in the conventional case.

〔Effect of the invention〕

As explained in detail above, according to the present invention, when the power is turned on,
This has the effect of significantly shortening the time to initialize memory.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of a computer according to an embodiment of the present invention, and FIG. 3 is a diagram showing a conventional memory initialization program. In the figure, 1 is a direct memory access controller, 2 is a memory, 3 is a latch means, a latch section, 4 is an AND circuit, 5 is a write means, 6 is a forcing circuit, and 7 is a ROM. 8 represents a processor, and 9 represents a gate. Kibatsu Sungetsu's original construction book opening/tsuku map No. 1 Preface n

Claims (1)

[Claims] Direct memory access controller (1) and memory (2)
), when the power is turned on, the direct memory access controller (1)
a latch means (3) which outputs a clear request signal to the AND circuit (4) and an H level signal to the AND circuit (4), and when the power is turned on, the direct memory access controller (1);
a writing means (5) for writing the start address and end address of the memory (2) to be initialized; and the AND circuit (
A forcing circuit (6) is provided which forcibly sets the data bus to the memory (2) to 0 at the output of step 4), and the direct memory access controller (1) is initialized when the clear request signal is input. When the first address and the last address are written, an H level signal is sent to the AND circuit (4) to indicate that memory access is ready, and the forcing circuit (6) forces the data bus to the memory (2). is set to 0, sends a write signal to the memory (2), and sequentially outputs the addresses from the first address to the last address to be initialized via the address bus to the memory (2) to initialize the memory (2). A computer characterized by being designed to