JPH02227761A - Data transfer controller and data processing system - Google Patents

Abstract

PURPOSE:To shorten the initializing time by using a memory means to set the information which designates a memory area and the initialization data and controlling the writing operations based on the set information. CONSTITUTION:A DMAC 2 performs the data transfer control in place of the access control of a CPU 1 and carries out the data control between memories as well as between a memory 3 and an input/output circuit. A function is added to initialize the memory 3 in a prescribed timing in a system working state and to rewrite a memory cell array of the memory 3 into a prescribed data pattern. The information which designates a memory area in the memory 3 and the initialization data are set based on the control information produced by the CPU 1. The CPU 1 writes the initialization data into the memory area and controls it based on the information set in the memory 3. As a result, the access time is minimized and the initializing time is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory initialization technique and a data processing system including a data transfer control device and a memory. The present invention relates to technology that is effective when applied to board computers.

[Prior art]

In a data processing system including a processor and memory, the memory is initialized when the power is turned on or when the data area of the memory is set. Such initialization is necessary to stabilize system operation and improve reliability. For example, when checking the system status after power is turned on, the memory is set to logic "1" or logic rOJ. It is initialized to a certain data pattern such as In addition, video RAM (
Image memories such as random access memory (random access memory) may need to be initialized even during system operation due to the nature of drawing.

Initializing memory is basically done by repeating write cycles, so if the processor that controls the entire system were to initialize the memory, it would place a burden on the processor, and it would be difficult to use the memory efficiently or quickly. Unable to initialize.

Therefore, there is no direct memory access in the system.
When a controller is included, the memory access controller can be used from the viewpoint of reducing the burden on the processor and speeding up the initialization operation.

By the way, data transfer control by the direct memory access controller 1-roller is broadly divided into dual addressing method and single addressing method. In the former case, the direct memory access controller controls the transfer source circuit. Read data is read, and the read data is accessed to the transfer destination circuit. In the latter case, for example, in addition to read accessing the transfer source circuit and reading the data onto the bus, the operation of the transfer destination circuit such as the input/output circuit is controlled by a strobe signal, etc., and the data on the bus is directly read. Write control. Furthermore, in single addressing mode, it can also be used for data transfer from a transfer source circuit such as an input/output circuit to a transfer destination circuit such as a memory.

Therefore, when a memory is initialized using the dual addressing method, the transfer source circuit must be read accessed by the number of times the memory is accessed as the data transfer destination circuit, which increases the number of bus cycle activations. Furthermore, even when the memory is initialized using the single addressing method, the direct memory access controller must control both the external transfer source circuit and the transfer destination circuit. , Dairef 1 - The memory access controller must spend time on various processes for controlling access to both the transfer source circuit and the transfer destination circuit.

An example of a document describing direct memory access controllers is "Hitachi Microcomputer Data Book 8/16-bit Microcomputer Peripheral LSI" published by Hitachi, Ltd. in September 1985.
There are JP389 to P442.

[Problem to be solved by the invention]

However, there is no direct way to initialize memory.
Even if a memory access controller is used, conventional direct memory access controllers do not have a dedicated function to initialize memory, so only the number of times the memory to be initialized is accessed is transferred. It becomes necessary to read access the source circuit, perform various types of control over both the external transfer source circuit and the transfer destination circuit, and as the storage capacity of the memory to be initialized increases, the memory is initialized. There was a problem in that the time required for this process increased significantly.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data transfer control device that can shorten memory initialization time, and a data processing system including the data transfer control device.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a data transfer control device such as a direct memory access controller is provided with a storage means that can arbitrarily set information for specifying a memory area and initialization data, and the above-mentioned information is stored in accordance with the information set in this storage means. A control means for initializing the memory area by controlling writing of initialization data into the memory area is provided. At this time, the control means
By receiving specific control information, it is possible to instruct a data transfer channel that can also be used for other data transfer formats to perform an operation for initializing a memory area.

A data processing system including at least a central processing unit and a memory may include the data transfer control device, and in this case, the data transfer control device may be controlled by specific control information such as an initialization command issued from the central processing unit. It is possible to configure an operation mode in which writing control of initialization data is performed when a request is received.

In such a data processing system, a first bus connecting the data transfer control device and memory and a second bus connecting the central processing unit can be selectively separated via gate means, It is possible to separate the memory when initializing it.

[For production]

According to the above-mentioned means, the data transfer control device that performs the memory initialization operation only needs to exchange initialization data, memory addresses, and necessary handshake signals with the memory to be initialized. The transfer control device acts to minimize the number of bus cycles to be activated and the time required to control access to the outside, and as a result, the initialization time for the memory can be shortened.

Performing the memory initialization operation using a data transfer channel that can also be used for other data transfer formats based on specific control information issued from the central processing unit is an effective method for initializing the initialization operation. Since there is no need to dedicate and add a data transfer channel, the memory initialization function can be easily incorporated into an existing data transfer control device.

Further, when initializing the memory, the separation state between the first bus and the second bus achieved by the gate means acts to enable external access operations of the central processing unit in parallel with the memory initialization operation.

〔Example〕

FIG. 2 shows a block diagram of a single board computer which is an embodiment of the present invention. The single-board computer shown in the figure includes, but is not particularly limited to, a central processing unit (hereinafter simply referred to as CPU) 1, which is composed of separate chips or semiconductor integrated circuits, and a direct processor.
A memory access controller (hereinafter simply referred to as DMAC) 2, a memory 3 that does not include a CPU operation program, and a peripheral circuit group 4 that individually includes other memories, controllers, and input/output circuits are mounted on the wiring board. The DMAC 2 and memory 3 are coupled to, for example, an 8-bit first bus 5, and the CPU and peripheral circuit group 4
are connected to, for example, an 8-bit second bus 6, and both buses 5 and 6 can be selectively connected/separated by a bidirectional buffer circuit 7, which is an example of a grouping means.

The DMAC 2 is a controller for controlling data transfer in place of CPUI access control. This DM
It goes without saying that AC2 is used to control data transfer between memories and between memory and input/output circuits, but in particular, AC2 is used to control data transfer between memories and between memory and input/output circuits. It has a function to initialize. Here, initializing the memory 3 means rewriting a memory cell array (not shown) of the memory 3 to a predetermined data pattern such as logic "1" or logic rOJ.

According to FIG. 1, which shows a detailed example of the DMAC 2, the DMAC 2 includes a first channel and a second channel for data transfer, although this is not particularly limited.

The first channel is used for data transfer between memories and data transfer between memory and input/output circuit, and includes a second register REG2 that specifies the transfer source address, a second register REG2 that specifies the transfer destination address, and a third register REG3 that specifies the number of words to be transferred.
Data is arbitrarily set by I. On the other hand, the second channel is used for data transfer between the memory and the input/output circuit, and in this embodiment, it is also used for initializing the memory 3 in particular.

This second channel has a fourth register REG 4 and a fifth register RE, which can be set arbitrarily by the CPU.
In data transfer between the memory and the input/output circuit, the memory address is set in the fourth register REG4, and the address of the input/output circuit is set in the fifth register REG5. , sixth register REG6
The number of words to be transferred is set. When initializing the memory 3, the access address of the memory 3 is set in the fourth register REG4, the initialization data to be written to the memory 3 is set in the fifth register 5, and the data necessary for initialization is set in the sixth register REG6. The number of data transfer words is set. In addition, the initialization data is
It corresponds to the number of data input/output bits of the memory 3. For example, when the memory 3 inputs/outputs data in the by-l-middle order,
The initialization data is byte data.

Information such as enable bits for the first and second channels is set in the status register 5REG. For example, when "1" is written to the enable bit corresponding to the first channel, data transfer operation by the first channel is enabled, and the enable bit corresponding to the second channel is written to "1".
When "1" is written in , data transfer operation via the second channel becomes possible.

The operation mode for the first and second channels is determined by the settings of the mode register MREG and the initialization command register (REG), which is a type of mode register.
G is a dedicated register for causing the second channel to initialize the memory 3, and control information such as an initialization command consisting of one or more bits is set by the CPU via the first bus 5 and the second bus 6. Ru. The mode register MREG is a register for specifying other data transfer modes in the first and second channels, and has a control bit group set therein for specifying data transfer modes in the first and second channels.

Requests for data transfer control operations for the DMAC 2 differ depending on the data transfer format, and data transfer requests between peripheral circuits and memory are instructed by transfer request signals DREQI and DREQ2 applied from input/output circuits included in the peripheral circuit group 4. Further, data transfer requests between memories are given in response to predetermined condition settings for the status register 5REG and mode register MREG by the CPU, and furthermore, the initialization operation of the memory 3 is performed by the CPU.
It is given by the initialize command given from . The transfer request signal DREQI corresponds to the first channel, and the transfer request signal DREQ2 corresponds to the second channel, and these signals are applied to the transfer request controller 10.

Although not particularly limited, the transfer request controller 10 arbitrates the requests from the two in accordance with a predetermined priority when the transfer request signals DREQI and DREQ2 conflict, and also generates a transfer acknowledge signal DA in response to an accepted transfer request.
Return CKI or DACK2 to the corresponding transfer request source. The input/output circuit for which the data transfer request has been accepted instructs the CPU to set conditions necessary for data transfer control by the DMAC 2 by means such as an interrupt, although this is not particularly limited. For example, when data is transferred from the input/output circuit to the memory using the first channel, the address of the input/output circuit is stored in the first register REGI, the start address of the memory is stored in the second register REG2, and the third register REG3 The number of words to be transferred is set in , and the status register 5REG
``U'' is written in the enable bit of the first channel, and control information instructing the data transfer mode is written in the mode register MREG.

When the CPUI requests data transfer between memories,
Before that, the CPUI registers RE for the first channel.
In addition to setting the start address of the transfer source memory in GI,
Set the start address of the transfer destination memory in register REG2, further set the number of transfer words in register REG3, then write control information instructing the data transfer form in mode register MREG, and then write control information instructing the data transfer form to mode register MREG.
Set "1" to the enable bit of the first channel in REG.
Write.

When the CPUI requests the initialization operation of the memory 3, first set the start address of the memory 3 in the register REG4 for the second channel, the initialization data in the register REG5, and then set the initialization data in the register REG6.
Set the number of words to be transferred. After that, an initialize command is written to the initialize command register CREG.

Above status register 5REG, mode register MR
EG and initialize command register CREG
The setting contents and the type of channel accepted by the transfer request controller 10 are referenced by the data transfer controller 11, and in accordance with this, the data transfer controller 11 performs data transfer control for one of the various data transfer requests. conduct. In data transfer control, the data transfer controller 11 causes the bus controller 12 to assert the bus request signal BREQ, and when the pass acknowledge signal BACK is asserted as a response signal to this, the data transfer controller 11 acquires the bus right and starts the data transfer operation.

When data is transferred between memories via the first channel, the transfer source circuit is read accessed using the transfer source address of the second register REG2, data is read into a register (not shown), and the read data is transferred to the second register REG2.
Write access to the memory area specified by the transfer destination address in step 2.

Handshake signals such as access control signals and response signals from the memory necessary for memory read/write access at this time are exchanged via predetermined signal lines included in the signal line group 14. When data is transferred in 1-byte units in this way, incrementer/decrementer 1
3 increments or increments the transfer source start memory address set in the first register REGI and the transfer destination start memory address set in the second register REG2 according to the settings of the mode register MREG for each 1-byte data transfer operation. Decrement the first register REGI
And the next address is held in the second register REG2. The number of transfer words set in the third register REG3 is decremented by the incrementer/decrementer 13 for each 1-byte pig transfer operation, and when the data transfer controller 11 detects that the value has been cleared to zero, the DMAC2 transfers the data. Ends the transfer operation. The end of the data transfer operation is notified to the CPUI by the bus controller 12 negating the bus request signal BREQ.

When data is transferred between the memory and the input/output circuit via the first channel or the second channel, the register R
The start memory address of the transfer source or transfer destination set in EGI, REG2, or REG4 is incremented or decremented by the incrementer/decrementer 13 according to the settings of the mode register MREG for each 1-byte data transfer operation, and holds the next address. However, the address list of the input/output circuit is the mode register MR.
Depending on the settings of the EG, it can be fixed or updated sequentially by the incrementer/decrementer 13. In this data transfer, it is possible to select an operation mode in which the transfer source circuit is read accessed to read data onto the bus, and the data on the bus is directly written to the transfer destination circuit. At this time, handshake signals such as access control signals and response signals for read/write access to the memory and input/output circuits are exchanged via predetermined signal lines included in the signal line 14. At this time, the number of transfer words set in the third register REG3 is decremented by the incrementer/decrementer 13 for each 1-byte data transfer operation, and when the data transfer controller 11 detects that the value has been cleared to zero, the DMA
C2 ends the data transfer operation. The end of such a data transfer operation is achieved by the bus controller 12 negating the bus request signal BREQ to 1 or higher as described above.
The UI will be notified.

When initializing the memory 3 via the second channel, the memory 3 is initialized every write access using the memory address of the fourth register REG4 and the initialization data of the fifth register. At this time, an access control signal to the memory 3 is given via a predetermined signal line included in the signal line 14, but since only the memory 3 is accessed, the hunt shake signal given from the memory 3 to the DMAC 2 is the write response signal MREP. It is said that only

This response signal MREP is asserted every time a write access is made to the memory 3 in response to the write end timing of the memory 3. The data transfer controller 11 confirms the completion of writing one byte data by asserting this response signal MREP. When transferring data in 1-byte units in this way, the incrementer/decrementer 13
The first memory address of the transfer destination of the memory 3 set in the fourth register REG4 is incremented or decremented according to the settings of the mode register MREG for each 1-byte data transfer operation, and the next address is held in the fourth register REG4. To go. 6th register RE
The number of transfer words set in G6 is decremented by the incrementer/decrementer 13 for each 1-byte data transfer operation, and when the data transfer controller 11 detects that the value has been cleared to zero, the DMAC 2 ends the data transfer operation. do. The end of such data transfer operation is notified to the CPUI by the bus controller 12 negating the bus request signal BREQ, as described above. The initialization data set in the fifth register REG5 is output to the first bus 5 every 1-byte data transfer operation. In particular, the data transfer controller 11
When executing the initialization mode, the gate control signal BCONT is asserted to the buffer circuit 7 to electrically separate and control the first bus 5 and the second bus 6, and during the execution of the initialization mode, the CPU is connected to the second bus 6. The connected peripheral circuit group 4 and the like are made accessible. Therefore, even if BREQ is asserted when the CPUI issues an initialize command, the CPU 1 does not relinquish the bus right.

Next, the initializing operation of the memory 3 by the DMAC 2 will be explained with reference to FIG.

When initializing memory 3, the CPU
The start address of the memory 3 is set in the fourth register REG4 of C2, the initialization data is set in the fifth register REG5, and the number of data transfer words required to initialize the memory 3 is set in the sixth register REG (step Sl). ). and initialize command register C
An initialize command is written to REG (step S2). In the initial settings by the CPU for the initialization operation, although there are no particular restrictions, it is not necessary to set the enable bit for the second channel or information instructing the data transfer direction in the status register 5REG or the mode 1 register MREG. . This is because the data transfer controller] 1 uniquely recognizes the contents corresponding to the information by the initialize command.

When the DMAC 2 receives the initialize command, it asserts the bus request signal BREQ, acquires the bus right by receiving a response to this with the pass acknowledge signal BACK, and then outputs the gate control signal BCONT.
to Asser 1 to separate the first bus 5 and the second bus 6 (
Step S3).

At this time, the CPU does not relinquish bus ownership, and can access circuit blocks included in the peripheral circuit group 4 connected to the second bus 6 to perform data processing and initialization, if necessary. Even if the CPU 1 and the DMAC 2 have bus rights in parallel, data collision will not occur because the first bus 5 and the second bus 6 are separated. And DMAC2
outputs the start address of the memory 3 set in the fourth register REG4 to the first bus 5 (step S
4) Write access control of the memory 3 is performed by outputting the initialization data set in the fifth register REG5 to the first bus 5 (step S5).

As a result, the initialization data is written to the first address of the memory 3 (step s6), and the memory 3 asserts the response signal MREP at the timing corresponding to the end of writing, and ends the first write operation (step s6).
7).

When the DMAC 2 receives the response signal MREP (step S8), it decrements the set value of the sixth register using the increment/decrementer 13 (step S9), and also writes the memory based on whether the decremented value has been cleared to zero or not. Determine whether initialization has been performed up to the end address of 3 (step 510)
. If it is determined that the end address has not been reached, the increment/decrementer 13 updates the memory address of the fourth register 4 to the next address (
Step 5ll), the process returns to step S5, and the initialization data write cycle is repeated until the end address while sequentially updating the memory addresses in the same manner.

When it is determined in step S10 that the final address has been reached, the bus request signal BREQ
(step S12) to notify the CPUI of the end of the memory initialization operation, and then negates the gate control signal BCONT (step 513).
The buffer circuit 7 is returned to the connected state.

According to the above embodiment, the following effects can be obtained.

(1) DMAC2 contains the start address of memory 3 on the fourth register REG4 initialized by the CPUI, the initialization data on the fifth register REG5, the number of transfer words on the sixth register RE'G6, and the initialization command register CREG. Based on the initialization command written in the DM, the memory 3 is initialized using the second channel, and at this time, the DM
AC2 only needs to exchange initialization data, memory addresses, and necessary handshake signals with memory 3. In other words, a data transfer operation of 1 byte only requires activating one bus cycle, and 1 It is only necessary to exchange access control signals and handshake signals such as the response signal MREP with one memory 3, and thereby, access control signals and handshake signals can be exchanged with both the external transfer source circuit and transfer destination circuit. Compared to the case where the memory 3 is initialized using a normal direct memory access method in which access is controlled by the memory 3, the initialization time of the memory 3 can be shortened.

(2) The initialization operation of the memory 3 is instructed by the initialization command given from the CPUI, and the initialization operation instructed by this is executed using the second channel that can also be used for other data transfer forms. There is no need to dedicate and add a data transfer channel for this purpose, and the memory initialization function can be easily incorporated into an existing DMAC.

(3) In a data processing system such as a single-board computer, the first bus 5 and the second bus 6 can be selectively connected/separated by a buffer circuit 7, and this buffer circuit 7 is used when the memory 3 is initialized. Since it is separated, the CPUI can initialize other circuit blocks and perform other necessary external accesses in parallel with the initialization operation by the DMAC2.

Although the invention made by the present inventor has been specifically described above based on examples, the present invention is not limited thereto, and various changes can be made without departing from the gist thereof.

For example, in the above embodiment, the memory initialization operation is performed using the second channel which can also be used for other data transfer formats, but a dedicated channel for memory initialization may be provided. Alternatively, an end address may be set in a register instead of the number of data transfer words, and this end address may be compared with the access address each time to determine whether the initialization operation is complete. Further, the number of data transfer channels included in the DMAC and the control method therefor are not limited to the above embodiments, but can be changed as appropriate. It is sufficient that the initialize command is control information for instructing the DMAC to perform an initialize operation. In addition, in the embodiment described in -, the first bus 5 and the first bus 6
A rose can be placed in between. Furthermore, when the memory 3 is an image memory, the initialization operation for it is not limited to being performed at power-on or system reset, but can also be performed at a predetermined timing during data processing. In addition, in this specification, the central processing unit is
It can be understood as a microprocessor or microcomputer.

In the above description, the invention made by the present inventor was mainly applied to a single board computer, which is the background field of application, but the present invention is not limited thereto; It can be widely applied to single-chip microcomputers including direct memory access controllers and memory. The present invention can be applied at least to conditions for initializing memory.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, the data transfer control device initializes the memory by exchanging initialization data, memory addresses, and necessary handshake signals only with the memory to be initialized. The number of cycles and the time for controlling access to the outside can be minimized, which has the effect of shortening the initialization time for the memory.

Furthermore, by performing the memory initialization operation using a data transfer channel that can also be used for other data transfer formats, based on specific control information issued from the central processing unit, the initialization operation can be performed. Since there is no need to dedicate and add a data transfer channel for this purpose, it is possible to easily incorporate a memory initialization function into an existing data transfer control device.

In a data processing system including a central processing unit and memory together with the data transfer control device, a first bus connecting the data transfer control device and the memory and a second bus connecting the central processing unit to the memory are connected to each other. By separating in response to the initialization operation, the central processing unit can perform the
This has the advantage that necessary data processing can be efficiently performed by initializing or accessing other circuit blocks connected to the second bus.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a DMAC that is an embodiment of the present invention, FIG. 2 is a block diagram of a single board computer that is another embodiment of the invention that includes the DMAC of FIG. 1, and FIG. 3 is a block diagram of a DMAC that is an embodiment of the present invention. 3 is a flowchart illustrating an example of a memory initialization operation procedure according to the present invention. 1...CPU, 2.DMACl3, memory, 4...
Peripheral circuit group, 5...1st bus, 6.2nd bus, 7.buffer circuit, 10..transfer request controller 1-roller, 1.data transfer controller, 12.pass controller l-roller,
13... Incrementer/decrementer, REG4.
...4th register, REG5...5th register, REG
6... 6th register, 5REG... status register, MREG... mode register, CREG... command register, MREP... response signal, BCONT...
・Gate control signal.

Claims (1)

[Claims] 1. A data transfer control device that performs direct memory access control, comprising a storage means in which information for specifying a memory area and initialization data can be arbitrarily set; and control means for initializing the memory area by controlling the writing of initialization data into the memory area according to the information stored in the memory area. 2. Claim 1, wherein the control means instructs a data transfer channel that can also be used for other data transfer formats to perform an operation for initializing a memory area by receiving specific control information. The data transfer control device described. 3. In a data processing system in which a data transfer control device capable of data transfer using a direct memory access method, a memory, and a central processing unit are coupled via a bus, the data transfer control device has information for specifying a memory area. It has a storage means that can arbitrarily set initialization data, and initializes the area defined by the memory area designation information set in the storage means based on specific control information issued from the central processing unit. A data processing system capable of executing an initialization operation mode for controlling data writing. 4. A first bus connecting the data transfer control device and the memory and a second bus connecting the central processing unit are connected via gate means, and the gate means is configured to connect the data transfer control device 3. The data processing system according to claim 2, wherein the first bus and the second bus are electrically separated by a control signal that is enabled when controlling the writing of initialization data.