JPH02228057A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH02228057A
JPH02228057A JP1049314A JP4931489A JPH02228057A JP H02228057 A JPH02228057 A JP H02228057A JP 1049314 A JP1049314 A JP 1049314A JP 4931489 A JP4931489 A JP 4931489A JP H02228057 A JPH02228057 A JP H02228057A
Authority
JP
Japan
Prior art keywords
lead
semiconductor device
inner end
leads
wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1049314A
Other languages
Japanese (ja)
Inventor
Kazunari Michii
一成 道井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1049314A priority Critical patent/JPH02228057A/en
Publication of JPH02228057A publication Critical patent/JPH02228057A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/536Shapes of wire connectors the connected ends being ball-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/5363Shapes of wire connectors the connected ends being wedge-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/5449Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体装置、特に多ピンの樹脂封止型半導体
装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a multi-pin resin-sealed semiconductor device.

〔従来の技術〕[Conventional technology]

第3図は従来の多ビンの樹脂封止型半導体装置の構成を
示す透視平面図である。この図において(1)は半導体
素子装着用のタブ、+21はこのタブに接合装着された
半導体素子、(3)はこの半導体素子の電極で、素子の
周縁部に沿って複数個配設されている。(4)は半導体
素子の周辺に上記電極(3)と対応して配設された複数
個のリードで、後述する樹脂封止を行った際、樹脂内に
位置する内部リード(5)と、樹脂外に位置する外部リ
ード(6)とから構成されている。(7)は内部リード
(51の先端部と、電極(3)とを接続する金線などの
ワイヤ、ts+は樹脂製のパッケージ本体で、上記半導
体素子し)、タブ(1)、ワイヤ(7)及び内部リード
((5)を封止するものである。
FIG. 3 is a perspective plan view showing the structure of a conventional multi-bin resin-sealed semiconductor device. In this figure, (1) is a tab for mounting a semiconductor element, +21 is a semiconductor element bonded to this tab, and (3) is an electrode of this semiconductor element, which is arranged in plural along the periphery of the element. There is. (4) is a plurality of leads disposed around the semiconductor element in correspondence with the electrodes (3), and when resin encapsulation (described later) is performed, internal leads (5) located within the resin; It is composed of an external lead (6) located outside the resin. (7) is a wire such as a gold wire that connects the tip of 51 and the electrode (3), ts+ is a resin package body, which is connected to the semiconductor element), tab (1), and wire (7). ) and internal leads ((5)).

このように構成された従来の半導体装置において、タブ
(1)及びリード(4)は周知のリードフレームとして
構成されるもので、スタンピング法又はエツチング法に
よって加工されるものである。
In the conventional semiconductor device constructed in this way, the tab (1) and the lead (4) are constructed as a well-known lead frame, and are processed by a stamping method or an etching method.

第4図はこのようなリードフレームの一部を拡大して示
すもので図中Pはリード(イ)の内端部のピッチを示し
ている。この種リードフレームを加工する場合の加工限
界値は、リードフレームの板厚が0.15+amの場合
、スタンピング法でP = 0.24mm、エツチング
法でP = 0.21011程度であり、Pの値がこれ
以下になるとパンチが破損したり、ワイヤ接続に必要な
リード巾を確保することができなくなる。
FIG. 4 shows an enlarged view of a part of such a lead frame, and P in the figure indicates the pitch of the inner end portions of the leads (A). When processing this type of lead frame, the processing limit value is about P = 0.24 mm for the stamping method and P = 0.21011 for the etching method when the lead frame thickness is 0.15 + am, and the value of P is If it is less than this, the punch may be damaged or it will not be possible to secure the lead width necessary for wire connection.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

半導体装置の高機能化に伴って、リードフレームも25
0ビンを超えるような超多ビンが要求されるようになっ
てきているが、このような場合、リードの内端部のピッ
チPを上述した加工限界値以上にすると内部リードf5
1の先端部の位置を半導体素子(2)から遠ざけて配設
せざるを得ないため組立作業に困難を伴う。一方、組立
て作業に支障を来たさないように内部リード(5)の先
端部を所定の位置に設定しようとすればピッチPをフレ
ームの加工限界値より小さくしなければならないという
問題がある。なお、リード(イ)の板厚を薄くすれば加
工限界値を小さくすることができるが外部リード(6)
が弱くなって実用に供し得なくなるため、その改善策と
してリード(4)の内端部のみを肉薄にすることが例え
ば特公昭49−47590号公報によって提案されてい
る。この種の肉薄部はフォトエツチング法によって容易
に加工できるが、第5図に内部リード(5)の内端部を
拡大して示すように、その肉薄加工面(9)は荒れてい
るため、この部分に半導体素子の電極(3)に接続する
ためのワイヤ■を接合固着することができない、この場
合、第6図に示すように、内部リード((5)を反転し
て肉薄加工面(9)の裏面の平坦な面側にワイヤ口を接
合する方法もあるが、接合に際して内部リード(9の平
坦な面QOIに力が加わった時、肉薄部分が図示のよう
に下方に折れ曲がるため、ワイヤ■の接合部が不安定に
なるという問題点がある。
As semiconductor devices become more sophisticated, lead frames also become more sophisticated.
There is a growing demand for extremely large numbers of bins exceeding 0 bins, but in such cases, if the pitch P of the inner end of the leads is made equal to or greater than the processing limit value described above, the internal lead f5
Since the tip of the semiconductor element (2) must be located away from the semiconductor element (2), assembly work is difficult. On the other hand, in order to set the tips of the internal leads (5) at predetermined positions so as not to interfere with the assembly work, there is a problem in that the pitch P must be made smaller than the processing limit value of the frame. Note that the processing limit value can be reduced by reducing the thickness of the lead (A), but the external lead (6)
As a countermeasure to this problem, it has been proposed, for example, in Japanese Patent Publication No. 49-47590, to make only the inner end of the lead (4) thinner. This type of thin part can be easily processed by photoetching, but as shown in FIG. 5, which shows an enlarged view of the inner end of the internal lead (5), the thin processed surface (9) is rough. In this case, it is not possible to bond and secure the wire (2) for connecting to the electrode (3) of the semiconductor element to this part. In this case, as shown in FIG. There is also a method of joining the wire port to the flat surface side of the back side of the internal lead (9), but when a force is applied to the flat surface QOI of the internal lead (9) during joining, the thin part bends downward as shown in the figure. There is a problem that the joint of the wire (2) becomes unstable.

この発明はこのような問題点を解消するためになされた
もので、内端部を肉薄としたリードにワイヤを的確に接
合固着し得る半導体装置を提供しようとするものである
The present invention has been made to solve these problems, and it is an object of the present invention to provide a semiconductor device in which a wire can be accurately bonded and fixed to a lead having a thinner inner end.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る半導体装置は、リード内端部をエツチン
グによって肉薄にすると共に、肉薄部のエツチング面を
矯正加工することによって平坦化するようにしたもので
ある。
In the semiconductor device according to the present invention, the inner ends of the leads are made thinner by etching, and the etched surfaces of the thinner parts are flattened by correction processing.

〔作  用〕[For production]

この発明によれば、リード内端部における肉薄部のエツ
チング面が平坦に矯正加工されているため、この面に対
するワイヤの接合固着を容易に行うことができる。
According to this invention, since the etched surface of the thin portion at the inner end of the lead is flattened, the wire can be easily bonded and fixed to this surface.

〔発明の実施例〕[Embodiments of the invention]

以下、この発明の一実施例を第1図及び第2図について
説明する。第1図は数個の内部リード(9の内端部を示
す平面図であり、第2図は1個の内部リード+51の内
端部を示す拡大斜視図である。これらの図において、(
5)は内部リード、(9)は内部リードの内端部に設け
られた肉薄部で、片面をフォトエツチングすることによ
って形成されたものである。 (11)は肉薄部のエツ
チング面のうち先端部にたたき加工等の矯正加工を施し
て形成された矯正加工面で、エツチング面が荒れた表面
であるのに対し、矯正加工面(11)は平坦な表面とな
り、ワイヤ(7)を接合固着することが容易である。
An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. FIG. 1 is a plan view showing the inner end of several internal leads (9), and FIG. 2 is an enlarged perspective view showing the inner end of one internal lead +51.
5) is an internal lead, and (9) is a thin portion provided at the inner end of the internal lead, which is formed by photo-etching one side. (11) is a straightened surface formed by applying straightening processing such as pounding to the tip of the etched surface of the thin part.While the etched surface is a rough surface, the straightened surface (11) is It becomes a flat surface, and it is easy to bond and fix the wire (7).

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によれば、リードの内端部にエツ
チングによって肉薄部を形成すると共に、肉薄部のエツ
チング面を矯正加工によって平坦化し、ワイヤの接合固
着を可能としたため、フレームの加工限界値を小さくす
ることができ、超多ピン化に対応することが可能となる
ものである。
As described above, according to the present invention, a thin part is formed at the inner end of the lead by etching, and the etched surface of the thin part is flattened by correction processing, making it possible to bond and fix the wire, which limits the processing limit of the frame. The value can be made small, and it is possible to cope with an extremely large number of pins.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例を示すリード内端部の平面
図、第2図は1個のリード内端部の構成を示す拡大斜視
図、第3図は従来の多ビンの樹脂封止型半導体装置の構
成を示す透視平面図、第4図は従来の半導体装置におけ
るリードフレームの構成を示す拡大説明図、第5図及び
第6図は従来の半導体装置におけるリードの内端部を示
す拡大図である。 図において(1)はタブ、(2)は半導体素子、B)は
電極、(イ)はリード、+51は内部リード、(6)は
外部リード、口はワイヤ、0131はパッケージ本体、
(9)は肉薄部、(l!)は矯正加工面である。 なお、図中、同一符号は同−又は相当部分を示す。
Fig. 1 is a plan view of the inner end of a lead showing an embodiment of the present invention, Fig. 2 is an enlarged perspective view showing the structure of the inner end of one lead, and Fig. 3 is a conventional multi-bin resin seal. FIG. 4 is an enlarged explanatory view showing the structure of a lead frame in a conventional semiconductor device, and FIGS. 5 and 6 show the inner ends of leads in a conventional semiconductor device. FIG. In the figure, (1) is a tab, (2) is a semiconductor element, B) is an electrode, (A) is a lead, +51 is an internal lead, (6) is an external lead, the opening is a wire, 0131 is the package body,
(9) is the thin part, and (l!) is the straightened surface. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] 複数個の電極を有する半導体素子が装着されたタブと、
このタブの周辺に上記電極に対応して配設され、上記電
極に接続された複数個のリードと、このリードの一部を
含み上記半導体素子及びタブを封止する樹脂製のパッケ
ージ本体とを有するものにおいて、上記各リードの内端
部をエッチングによってその他の部分よりも肉薄に形成
すると共に、肉薄部の表面が平坦となるように矯正加工
したことを特徴とする半導体装置。
a tab equipped with a semiconductor element having a plurality of electrodes;
A plurality of leads are arranged around the tab in correspondence with the electrodes and connected to the electrodes, and a resin package body includes a portion of the leads and seals the semiconductor element and the tab. 2. A semiconductor device comprising: an inner end portion of each lead formed by etching to be thinner than the other portion; and a straightening process such that the surface of the thin portion is flattened.
JP1049314A 1989-03-01 1989-03-01 Semiconductor device Pending JPH02228057A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1049314A JPH02228057A (en) 1989-03-01 1989-03-01 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1049314A JPH02228057A (en) 1989-03-01 1989-03-01 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH02228057A true JPH02228057A (en) 1990-09-11

Family

ID=12827500

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1049314A Pending JPH02228057A (en) 1989-03-01 1989-03-01 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH02228057A (en)

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