JPH02228064A - Detection circuit - Google Patents

Abstract

PURPOSE:In a system which operates up to ultralow voltage, to enable prevention of the malfunction of a circuit by taking it into one semiconductor chip together with a boosting circuit, and detecting the boosted voltage of the boosting circuit, and automatically outputting detection signals to circuits such as a logic IC, etc. CONSTITUTION:This is provided with a boosting circuit 13, which consists of a bipolar element and boosts the power source voltage Vcc being supplied to the bipolar and supplies voltage to a CMOS element, a reference voltage generating means, which generates the first voltage to become the standard, and a voltage dividing means 17, which divides the voltage being boosted by the boosting circuit 13 and generates a second voltage. And this is equipped with a comparator, which compares respective magnitudes of the first and second voltages and outputs those results, and an interface circuit 21, which receives the output of this comparator and transmits detection signals to a specified circuit. Hereby, malfunction at the time of rise of the power source voltage or by the drop, etc., of the boosted voltage during operation can be prevented.

Description

Detailed Description of the Invention [Object of the Invention] (Industrial Application Field) The present invention provides bipolar elements and
This relates to a voltage detection circuit mounted on a so-called B1CMOS chip in which MO8 elements are mixed.For example, CM
When applying a low voltage at which the OS does not operate as a driving voltage to a bipolar element and boosting this voltage with the bipolar element to drive a CMOS, it is necessary to detect the boosted voltage and output a signal to the CMOS logic. There are things that will be used.

(Prior Art) A circuit may malfunction due to a voltage rise when the power is turned on or a drop in the power supply voltage during operation, and to prevent this, a power supply voltage detection circuit is provided. In the field of CMOS in the prior art, this detection circuit is used, for example, as shown in FIG. 6, in which a CMOS power supply is applied to a comparator based on the MOS level.

This figure is a circuit diagram showing the basic configuration of the detection circuit.

Reference numeral 1 is a CMOS power supply terminal, and a voltage VO [l power supply for CMO3 (not shown) is connected between terminal 1 and ground.
is connected. Resistor R, connected in series at connection point 2
R2 and a PN junction diode D1. which is not connected in series at the connection point 3. A resistor R3 and a comparator 6 composed of 0 MO8 are provided in parallel between the terminal 1 and the ground. The connection point 2 and the connection point 3 are connected to the first input terminal 4 and the second input terminal @5 of the comparator 6, respectively, and the output terminal 7 of the comparator 6 outputs a detection signal through the inverter 8 of 0MO8 configuration.

Figure 7 is a diagram for explaining the outline of the operation of the above detection circuit, where the horizontal axis is time and the vertical axis is voltage (potential difference with ground).
When the CMO3 power supply voltage Voo (j) increases linearly from 0 as shown by fold aI in the same figure, the voltage V2 (t) at the connection point 2 and the voltage V3 (t) at the connection point 3 are respectively Changes occur as shown by broken lines l and folded in.
However, for convenience, it is assumed that the diode D has ideal constant voltage characteristics. In the case of normal diode characteristics, the broken line n becomes a curve, but similar results can be obtained. straight lines 1 and n
The value of the power supply voltage Voo(t) corresponding to the intersection with Voo
(j,), then Voo (t) <Vo.

(t,), the low level detection signal is Vo.

When (t) >Voo (t,), a high-level detection signal is output from the inverter 8. This detection signal is sent to the internal CMOS logic to prevent malfunctions when the power supply voltage rises.

The above detection circuit has a high threshold voltage of CMO3, and low voltage operation (for example, operation guaranteed up to 0.9V) is impossible with current technology, or even if it is possible, the manufacturing cost is extremely high. This is large and difficult to put into practical use. Further, when a PN junction diode D1 as shown in FIG. 6 is used, there is a large variation in forward voltage (VP), and there is a limit to the performance.

A system that operates at ultra-low voltage (minimum 0.9V) and t, for example, to operate CMO3 with a single 1.5-inch battery,
CMO with external DC-DC converter (boost circuit)
When creating a voltage for S drive, it is necessary to create a detection circuit to detect whether the boosted voltage has risen completely, and if the boosted voltage drops during operation due to battery life etc.
It is necessary to create a detection circuit to detect this externally.

(Issues that the invention aims to solve!) There is an extremely large need in the market for a system that operates CMOS logic with a single dry cell battery at low voltage, i.e., 1.5cm. Therefore, the low voltage is boosted to the voltage at which 0MO8 is fully operational. A booster circuit to detect the boosted voltage and a detection circuit to detect the boosted voltage are required.
In the field of , there is no conventional example in which a booster circuit and its boosted voltage detection circuit are incorporated into one chip.

The present invention is a system that operates down to an ultra-low voltage (fi low 0.9V), which is incorporated together with a booster circuit into one semiconductor chip, detects the boosted voltage of the booster circuit, and converts, for example, a CMOS
It is an object of the present invention to provide a detection circuit that transmits a detection signal to a predetermined circuit such as a logic circuit, thereby preventing malfunctions caused by a rise in power supply voltage or a drop in boosted voltage during operation.

[Structure of the Invention] (Means for Solving the Problems) The detection circuit of the present invention is mounted on one semiconductor chip in which bipolar elements and 0MO8 elements are mixed, (b) a reference voltage generating means that is composed of a bipolar element and generates a first voltage serving as a reference; (c) the booster circuit It consists of a voltage dividing means that divides the boosted voltage to generate a second voltage, and (d) a bipolar element, which compares the respective magnitudes of the first voltage and the second voltage, and calculates the comparison result. The present invention is characterized in that it includes a comparator that outputs , and an interface circuit that is made of a (+3) bipolar element, receives the output of the comparator, and transmits a detection signal to a predetermined circuit.

(Function) The detection circuit having the above configuration is manufactured using a Bi 0 MO8 process in which bipolar elements and 0 MO8 elements can coexist, and is composed of bipolar elements that can operate at ultra-low voltages and passive elements such as resistors.

Next, an outline of the operation of the detection circuit described above will be explained with reference to FIG. FIG. 1 is a block diagram showing an outline of the configuration of a detection circuit according to the present invention. Reference numeral 11 is a bipolar power supply terminal, and reference numeral 12 is a common potential terminal E (often grounded).
A bipolar power supply voltage vcc is applied between both terminals. The booster circuit 13 is composed of a DC-DC converter, and its input terminal is connected to the bipolar power supply terminal 11 and its output terminal is connected to the boosted voltage output terminal 14, respectively, and outputs a boosted voltage VO(l) of the input voltage VCC. The reference voltage generating means 15 is inserted between the bipolar power supply terminal 11 and the common potential terminal 12, and generates a first voltage vN as a reference.
is generated between the reference voltage terminal 16 and the common potential terminal 12. Note that the first voltage vN always has a substantially constant voltage value within the guaranteed fluctuation range of the voltage Vcc.
A second voltage Vd obtained by dividing the boosted voltage VOO is generated between the second voltage terminal 18 and the common potential terminal 12. 21st! The voltage vd only needs to have a fixed one-to-one correspondence with the boosted voltage VOD, and the voltage division ratio (V
d/Voo) may vary depending on the value of VOO. The comparator (also called a comparator) 19 has two analog input terminals IN1 and IN2 and one output terminal OUT.

The input terminal IN is connected to the second voltage terminal 18, and the other input terminal IN2 is connected to the reference voltage terminal 16.

Further, the output terminal OUT is connected to an interface circuit 21 via a terminal 20.

Comparator 19 has two analog human inputs Vd and VN
If V d < V N, a high level voltage, for example, is output to terminal 2°, and V d > V.

In this case, a low level voltage is output. That is, the comparator 19 is a differential amplifier having the function of an A/D converter.
The interface circuit 21 is provided at the boundary between the detection circuit (the part surrounded by the broken line) 50 and a predetermined circuit (for example, a CMOS logic circuit) not shown,
Voltage information of the output terminal 20 of the comparator 19 ■. , and transmits the detection signal v02 to a predetermined circuit.

FIG. 2 is a diagram for explaining the outline of the operation of the detection circuit 50, in which the horizontal axis represents time t, and the vertical axis represents the reference voltage (first voltage).
9. The boosted voltage ■oo and the second voltage (divided voltage) Vd are in standby mode (Stand) at time 1=0.
-by mode) is canceled and the booster circuit N113 starts operating. Curves 41, 42 and 4 in the same figure
3 are V, Vo, respectively.

and represents the rIIJ relationship between Vd and time t, where V is a desired boosted voltage to be detected that is set in advance. Boost voltage V
, the circuit constants of the reference voltage generating means 15 and the voltage dividing means 17 are set in advance so that the divided voltage (dx) of IX is equal to the base Mi-voltage VN. As a result, V on <
In the case of V oax, the voltage information at the output terminal 20 of the comparator is Vd minus VN. , becomes high level, and V
In the case of on > V an, voltage information ■ if Vd > Vs. , becomes low level, and the detected boosted voltage v can be detected.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 3 is a schematic diagram showing the configuration of the detection circuit according to the present invention. Note that the same reference numerals as in FIG. 1 represent the same or corresponding parts.

Detection port FI! 150 includes a booster circuit 13, a reference voltage generating means 15, a voltage dividing means 17, a comparator 19, and an interface circuit 21, and includes a bipolar element and a CMO8.
A single semiconductor chip includes a mixture of elements.

The booster circuit 13 has a configuration similar to a known DC-DC converter, converts the bipolar power supply voltage Vcc (for example, L5V) input from the terminal 11 into an AC voltage, boosts the voltage, and then converts it back into DC, converting the voltage to 0MO8. Voltage Vo that can be driven
o (for example, 3.6 V), and the voltage ■
. o) Output to CMOS logic circuit (not shown).

The reference voltage generating means 15 includes a constant current source IO1, a resistor R1, and a PN junction diode Q, and generates a first voltage vN serving as a reference at a connection point A (corresponding to the reference voltage terminal 16). By changing the value of the resistor R1, vN can be set to a desired value. Diode Q is NPN
) - connected between the base and emitter of transistor Q2,
This causes transistor Q2 to operate as a current source.

The voltage dividing means 17 consists of resistors R7 and R, and has a connection point B (
A second voltage vd is generated by dividing the boosted voltage Voo (corresponding to the second voltage terminal 18). That is, Vd=VooX (R
T3/(R12+R+z)).

Comparator 19 is PNP transistor Q5, Q6
This is a differential amplifier in which NPN transistor Q3 and Q4 are used as a load element, transistors Q3 and Q4 are used as drive elements, and NPN transistor Q2 is used as a current source element. One input terminal IN is connected to the connection point B, the other input terminal IN2 is connected to the connection point A, and the output 1110UT is connected to the interface circuit 121 via the terminal 20.

The interface circuit 21 consists of a resistor R+a and an NPN transistor Q7, and the voltage V at the output terminal 20 of the comparator. , is at a high level, the voltage v02 at the detection signal transmission terminal 22 (connection point C) is equal to the collector-emitter saturation voltage Vat (Sat) of the transistor Q7, and the voltage V0. When is low level, voltage vo2
It becomes VoD.

Next, with reference to FIGS. 4 and 5, the characteristics of the detection circuit shown in FIG. 3 after the start of boosting will be described.

In Figure 4, the horizontal axis is time, and the vertical axis is the boosted voltage output to the CMOS logic circuit, and the bipolar power supply voltage c.
Standby mode is canceled when 1 = 0, representing c.
The booster circuit 13 starts boosting the voltage, and the boosted voltage van reaches the broken line 5.
1 and reaches a constant value VOO(TVll).

Also, the power supply voltage for bipolar is Vcc (Tyo
) and has a constant value as shown by a straight line 52.

A broken line (broken line) 53 shows the transition of the voltage V02 of the detection signal transmission terminal 22 (point 0), and the vertical axis Voo (T,).

) is a typical value (for example, 3.6 [V]) of the power supply voltage for 0MO8, and VOON is the minimum value at which the 0MO8 element can operate (for example, 2.2 [V]).
Further, Vcc (Tya) is a typical value of the bipolar power supply voltage (for example, 1.5 [V]), and Vcc (M
I N ) is the minimum value at which the bipolar element can operate (e.g., 0.9 [V]). ■ Acceptable means the value of VOO when the voltage vd at point B becomes equal to the voltage at point A (e.g. 2.8 [■]).

vcc(MIN)≦VCc and VOwl<Vg
In the case of 4, the bipolar part circuit is turned on, but the CMO third part circuit is in the off state. As VoD increases, ■yu≦”
In the case of op < V, XIX, that is, when voo exceeds V, the 0M03 section operates and the voltage at point B in the V quadrant becomes A.
The voltage at point 0 remains at a high level until it becomes equal to the voltage at point 0. ■The hitting increases further, and v fish≦voo≦vo.

In the case of (T yp ), the voltage at point B is higher than the voltage at point A, so the voltage at point 0 becomes low level.

The detection method after the start of boosting by the booster circuit is shown in Figure 5.
In other words, the standby mode is released (t=0), the booster circuit starts boosting the voltage, and the minimum value VmN at which the CMOS can operate is reached.
When the voltage at the 0 point reaches the high level, a reset or clear signal (0 level) is transmitted to the CMOS logic circuit via the inverter 8 made up of 0 MO8 elements.

The boosted voltage Voo further increases and remains in a clear state until its divided voltage vd reaches a preset reference voltage VN, that is, until it reaches v (from t to t2).
When Voo exceeds VOOM, the comparator output is inverted and the CMOS logic circuit enters the full operating region. V
oo further increases and reaches VOD (TVll), resulting in steady operation.

[Effects of the Invention] 7. The detection circuit of the present invention is incorporated into one semiconductor chip together with a booster circuit in a system that operates down to ultra-low voltages, detects the boosted voltage of the booster circuit, and sends a detection signal to a circuit such as a logic IC. can be automatically output, so
It has become possible to prevent these circuits from malfunctioning.

In other words, when boosting the voltage with a booster circuit, etc., the boosted voltage may suddenly drop if, for example, the MOS section begins to operate in an incomplete state, or if a battery near the end of its life draws a large current in a certain mode. However, the detection circuit of the present invention makes it possible to take measures to prevent these malfunctions.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an overview of the configuration of the detection circuit of the invention, FIG. 2 is a diagram for explaining an overview of the operation of the detection circuit of the invention, and FIG. 3 is an embodiment of the detection circuit of the invention. FIG. 4 is an explanatory diagram of the characteristics of the detection circuit in FIG. 3 after the start of boosting, FIG. 5 is a diagram showing the detection method of the detection circuit in FIG. 3 after the start of boosting, and FIG. The figure is a detection circuit diagram of a conventional CMO3 circuit alone, and FIG. 7 is a diagram for explaining the operation of the detection circuit of FIG. 6. 11... Bipolar power supply terminal, 13... Boost circuit, 14... Boosted voltage extraction terminal, 15... Reference voltage (first voltage) generation means, 16... Reference voltage (
1st voltage) r4A (connection point A), 17... Voltage dividing means, 18... 21st! Pressure terminal, 19... Comparator, 21... Interface circuit, 50.
...Detection circuit. Figure Figure

Claims (1)

[Claims] 1 mounted on one semiconductor chip in which bipolar elements and CMOS elements are mixed; (a) a booster circuit made of bipolar elements and boosting the bipolar power supply voltage to supply voltage to the CMOS elements; and (b) bipolar elements. a reference voltage generating means for generating a first voltage serving as a reference;
(c) a voltage dividing means for generating a second voltage by dividing the voltage boosted by the booster circuit; and (d) a bipolar element, the respective magnitudes of the first voltage and the second voltage are A comparator that compares and outputs the comparison result,
(e) A detection circuit comprising: an interface circuit made of a bipolar element, which receives the output of the comparator and transmits a detection signal to a predetermined circuit.