JPH02228725A - Data processor and controller for image forming device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device including a D/A converter, and a control device for an image forming device such as a copying machine or a printer using the data processing device. It is.

(Prior Art) Conventionally, the electrical components of image forming apparatuses such as copying machines and printers include a sequence controller circuit centered on a microprocessor that controls the entire print sequence, and a DC
Since various components such as a power source, an exposure power source, and high voltages for charging and the like were independent, there was a limit to miniaturization and cost reduction.

Therefore, in order to form the above-mentioned components on one board, a microprocessor and a RAM.

ROM and digital peripheral circuits, as well as A/D converter, D/A converter, and pulse width modulation (PWM) for controlling the Mti system.
Proposals have been made to integrate circuits, etc., into a single chip.

(Problem to be solved by the invention) However, since an extremely large number of functions are integrated, it is difficult to test the chip using only the output port and manual port functions inherent in the chip, or to test the chip by placing a large burden on the test program. This method took a long time to test, which resulted in an increase in costs.

The present invention was made under these circumstances, and provides a control device for a data processing device and an image forming device that can shorten the inspection time related to the D/A converter, which plays a particularly important role in this type of device. The purpose is to provide the following.

[Means to solve the problem]

In order to achieve the above object, the present invention configures a data processing device as shown in (1) below, and as shown in (2) of the r#AI control device for an image forming apparatus.

(1) The data processing device is provided with the following components a''-8.

a, CPU, ROM, D/A inverter, test terminal, ? 3. Several groups of digital ports and analog ports.

b. A latch in which data to be D/A converted is set and which supplies the data to the ROM/A converter.

c. When the test terminal is at one logic level, read data from the previous ROM and set it in the latch, and when the test terminal is at the other logic level, according to the state of the group of digital ports; Means for setting data into the latch.

d. means for co-feeding the data of the latch to another group of the digital ports when the test terminal is at the other logic level;

, e when the test terminal is at the other logic level,
Means for supplying the output of the D/A converter to the analog port.

(2) A ROM storing the data processing device described in (1) above and a control program for the image forming device.

Digital peripheral circuits such as a RAM and a timer, and IIJ circuits such as various power sources of the image forming apparatus are formed on the same chip to constitute a control device for the image forming apparatus.

[Effect]

According to the configurations (1) and (2) above, when the test terminal is set to the other logic level, D is output from the - group digital port.
The data to be supplied to the A/A converter can be directed through the CPU and retrieved from another set of digital ports, and the output of the D/A converter can be retrieved from the analog port.

〔Example〕

The present invention will be explained below with reference to Examples.

FIG. 2 is a block diagram of a "copying machine control device" which is an embodiment of the present invention.

As shown in the figure, this control device includes a microcomputer, peripheral memory, timer, and other digital circuits, as well as D/A
Converter 9 Analog circuits such as comparators, one MAIN PWM circuit as a pulse width modulation circuit, and three SUB PWM circuits are integrated on one chip, and are used for most of the sequence control, power supply control, etc. of 2rM photo machines and printers. Control functions are integrated into this chip.

This control device includes a CPU core (CPU C0RE).
) in the center niD^'rA lilEMORY, PROGR
AM MEMORYjNTERRUPT CONTROL
1, a reset function 2, a watchdog timer (lfATcHDOG TIMER) for monitoring program runaway, 3, a 7-bit block that stores data to be converted from digital to analog based on CPU information. latches 21 to 24, a D/A converter 4, and an A that is used together with the D/A converter 4 and comparator circuit 5 to function as an analog-to-digital converter.
A timing controller 25 controls the operation timing of the /D converter 6, D/A converter, A/D conversion block, etc.; ) 8 etc. is built-in.

The A/D conversion block is used to read various voltages of the fixing thermistor, copy density adjustment volume, etc. of the copying machine. The D/A converter is used in the A/D conversion block, and is also used as a reference voltage for a comparator in a pulse width modulation circuit for fluorescent light dimming control, high voltage control, etc. of a copying machine.

The development AC bias drive pulse generator includes a 4-bit frequency divider 15 and a 5-bit frequency divider 15 to divide the CPU internal clock.
A 1/2 frequency divider 14 is used to set the duty of the C bias drive pulse to 50%.

The pulse width modulation circuits 10 to 13 are used for fluorescent lamp dimming control, high voltage power supply, and low voltage power supply control. The MAIN PWM circuit 10 with a digital 7-bit configuration is used for controlling the low voltage power supply, and the above-mentioned comparator is used for other controls. The SUB PW has a configuration in which the output result is directly a pulse width modulation output.
M circuits 11 to 13 are used. In addition, P of low voltage power supply control
The WM circuit IO has an instantaneous shutdown function for pulse width modulation output in the event of a power failure, and when a certain specified value is exceeded, the pulse width modulation output is immediately turned off, protecting the circuit and increasing the safety of the copier. .

This control device is also equipped with a human-powered boat for human-powered operation including various sensors, copy start, copy number setting, etc., an output boat for controlling 5 motors, heaters, solenoids, etc., and a display boat. L.E.
There is an output boat for the D drive, etc.

In addition, a checker is connected to the main body of the machine to check the operation of the copying machine at factories, markets, etc., and a serial communication boat is also included for this purpose.

A test terminal 20 is provided as a mode switching terminal for performing a chip test. The human power of analog multiplexer 8 is fixed thermistor as described in 6η,! These are a signal to be A/D converted, such as a one-time adjustment volume, and a feedback signal from the output of a low-voltage power supply, a high-voltage power supply, etc., to be controlled by pulse width modulation. Also latch (LATCH) 21
24 are held by writing digital data corresponding to the reference voltage of the output to be controlled by pulse width modulation from the CPU 37 section 1. Note that the output stages of latches 21 to 24 are as follows:
It has a three-state configuration in which the held contents are output by a signal from the timing controller 25.

The A/D converter 6 includes a latch that holds the final result, a latch that holds data that is being converted, and a logic circuit that updates the converted data based on the comparison result. The latch that holds the final result has the same configuration as the latches 21 to 24, and sends the held contents onto the data bus on the CPU side when selected by the CPU 37 section 1.

Here, the entire A/D conversion operation and pulse width modulation operation will be explained in detail. First, the CPU core 1 writes the control values of each PWM output into the latches 21 to 24, and also writes various data necessary for the MAIN PWM operation to the register in the MAIN PWMIO.

Further, analog input channel data to be A/D converted is written to a latch within the timing controller 25.

The timing controller 25 first selects the latch 21 and sends data, ie, MAIN, to the D/A converter 4.
The D/A converter 4 outputs the PWM control value, and
While generating an analog voltage based on the data,
Select the feedback signal input terminal of the MAIN PWM output of analog multiplexer 8. The output of the D/A converter 4 is input to one input terminal of the comparator 5. Further, the output of the analog multiplexer 8 is inputted to the other input terminal of the comparator 5.

The comparator 5 compares the power of the two and outputs high when the input on the analog multiplexer 8 side is higher than the input on the D/A converter 4 side, and outputs low when it is lower. The output of the comparator 5 is input to a 1-bit x 511 register (latch) 7. The timing controller 25 is
After the time has elapsed for the output of comparator 5 to become sufficiently stable,
One bit of latch 7 corresponding to MAIN PWM is selected and the comparison result is latched.

Next, the timing controller 25 selects the latch 22 to output data to the D/A converter 4, and at the same time selects the feedback signal input terminal of the SOB PWMI output of the analog multiplexer 8, and outputs the data to the D/A converter 4 output and the analog multiplexer. 8 outputs are manually input to comparator 5. As described above, the timing controller 25 adjusts the Ib of the latch corresponding to the SUB PWMI output after the time has elapsed for the output of the comparator 5 to become sufficiently stable.
Select 1t and latch the comparison result.

Next, the same operation as described above is performed for MAIN PWM, then the same operation is performed for the 5LJB PWM2 output, and the same operation as for MAIN and SUBPWM3 is repeated. This is because the comparator operation for the MA I NPWM output requires high speed compared to other SUB PWM outputs. Next, the MAIN operation is performed, then the A/D operation is performed, and the above cycle of operations is repeated. In other words, MAIN→5U
BO→MAIN+5UB1→MAIN→5UB2→MA
One cycle is I N-+A/D, and this cycle is sequentially repeated.

Here, the operation of the A/D converter will be described. As mentioned above, the A/D converter 6 has a latch that holds data during conversion, but the initial value is set to 100 by the logic circuit.
OOOOB is latched. The latch contents are output to the D/A converter 4 in response to a selection signal from the timing controller 25.

The output of the D/A converter 4 is input to one terminal of the comparator 5, and the other terminal of the comparator 5 is inputted to the
The analog multi-break +8 is driven and input so that the analog input to be A/D converted is selected.

Based on this comparison result, if the analog human power is larger than 10000008, it is l100OOOB, and if it is smaller, it is 010.
The A/D converter 6 generates data 0000B and stores it in a latch that holds an intermediate conversion result within the A/D converter 6. Furthermore, in the next cycle, the A/D converter 6 similarly generates data xllooooB if the analog input is larger than xJO (1000B (x is O or 1), and xolooooB if it is smaller than xJO (x is O or 1), and stores it in the latch as data during conversion. In this way, each bit is determined one after another, and in the last cycle, xxxxxxxlB and analog human power are compared, and based on the comparison result, xx
At the same time that xxxxlB or xxxxxxxOB is stored in the A/D conversion practical register, 1000000B is stored in the mid-conversion latch. The CPU core unit 1 can read the A/D conversion value by selecting the A/D conversion practical register. That is, the A/D conversion operation is always performed, and the conversion result register always holds the latest conversion result.

Here, consider, for example, a case where the performance of the D/A converter 4 is tested. In this embodiment, the D/A converter 4 is 7b
IT configuration, but as mentioned above, power supply control, A/D
Since it serves as the reference signal source for all conversions, the accuracy of the D/A converter 4 determines the overall performance of the tick's operation. Therefore, it must be checked in considerable detail. Also,
When testing whether predetermined values are latched in the latches 21 to 24, the latches themselves and the pass lines must be tested, and several types of data must be set.

For the above inspection, for example, it is possible to write some types of data in the ROM area, read the values using software, and set them in the latches 21 to 24, but this requires a considerable amount of ROM area. In order to carry out various tests that are necessary and cannot be changed, the program becomes long. Therefore, in this embodiment, during testing, the human power value of a specific digital port is used as latch data to latch 21 to 21.
24, and the chip can be inspected by setting arbitrary values from outside the chip. Also, at the same time, D
The output of the /A converter 4 is directly output to one port of the analog multiplexer 8, and the digital manual data of the D/A converter 4 is directly output to the output port.

The test method will be explained in detail below. FIG. 1 is a block diagram of the main part of this embodiment including this test circuit.

The CPU checks the test terminal 20 at the time of reset. When the test terminal 20 is high, the CPU performs normal operation, and when it is low, a test program in a special area of the ROM area is activated to perform a test operation. At the same time, the boat's functions are switched for testing purposes. In the figure, the boat function is switched by manually connecting the test terminal 20 directly to the test circuits A and H at 26 and 27.

Test circuit A is an analog switch that directly outputs the output of D/A converter 4 to one channel of eight channels of analog input terminals. Test circuit B is a 3-state buffer that switches the digital power of the D/A converter 4 to be directly output to the digital port (LED port in the embodiment), and is also a 3-state buffer to prevent data from colliding at the same time. LED driver 1
Set 9 to high impedance.

The test program always checks the digital manual boat (not shown) and sets data in the latches 21 to 24 according to the input boat value. In this case, there are multiple latches to set, so the input port is
It is divided into 7 bits: bit and data set in the latch. That is, for example, the upper 2 bits of the 9-bit manual data are selected as a latch, and the lower 7 bits are set as data. The program reads these 9 bits, addresses one of the latches 21 to 24 with the upper 2 bits, and sends the lower 7 bits as data onto the data bus. Now, to make the discussion m*, let's explain that there are two latches, and the data of the first latch will be stored in the boat as "
November, month” and then “ooooooo” as the data for the second latch.

”. Then, when you check the LED boat, “1
111111" and "oooooooo" should be output alternately. For example, if only one of the data is output, the latch is malfunctioning, the address decoding is malfunctioning, or the output line of the address decoding is malfunctioning. In other words, it is possible to determine whether the select line of the latch is disconnected or short-circuited.

Next, if you give "1010101" as the first latch data and "01 (11030") as the second latch data, the LED boat will similarly have 1010+01" and "01010".
10” are output alternately, but here, for example, 03 (11
If "01" is output, it can be determined that there is a possibility that the input line of the 6th bit of the first latch is shorted to an adjacent bit or shorted to V.0.

Also, as the first (D latch data) “ooooooo
” to “101111-” and determine the voltage of the analog human power O, it is possible to check whether the degree of turbulence of the D/A converter 4 is within the normal range with respect to the set value.

In this way, CPU core 1. Latches 21-24, D
/A converter 4 can be inspected in a short time.

Similar functions and effects can be obtained even if the above-described embodiments are modified as shown in A to C below.

a. Use the LED driver 19 without setting it to 3 states. That is, if the LED boat has a normal oven drain (oven collector) configuration, wired OR is possible. Immediately after entering the test program, 'o' is output from the CPU as LED data. Do this.

The output of LED driver] 9 is in the OFF state.

The output of test circuit B is directly output to the LED boat.

b. Example is test circuit A with test terminal 20.

B is active, but 1 as a test flag
A bit latch is provided, and the CPU sets and resets the 1-bit latch using software.

(b) During normal operation, the test terminal 20 is
Even if it becomes OW, the hardware will not switch to test operation unless the software reads the test terminal and sets the flag.

(b) Since the test circuits A and B switch the normal boat functions, the original boat functions cannot be tested. Therefore, for example, by setting 1 bit of the input port as a test mode switching bit and changing whether or not test circuits A and B are activated by setting and resetting this 1 bit, the original port function can also be tested.

When there is a shortage of C9 input ports, the boat that is originally an output boat is used as a human-powered boat only during testing.

The above is an example of a control device for a copying machine, but the test operation described above is applicable to numerical data processing devices, including D/A converters, that convert analog amounts into digital data and process the data with a CPU. It is clear that it can be done.

(Effects of the Invention) As explained above, according to the present invention, the test terminal is set to the other logic level to perform the test operation, and the D/A
Instruct the data to be converted from one group of digital ports, read from the other group of digital ports whether the specified data is set in the latch and supplied to the D/A converter, and convert the conversion result of the D/A converter to analog Since it can be read from the port, inspection of the CPU, latch, and D/A converter can be performed in a short time.
In addition, inspection of various patterns can be performed without using up the ROM area.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a main part of an embodiment of the present invention, and FIG. 2 is a block diagram of the entire embodiment. 1...CPυ core 4-----D/A converter 8-----Analog multiplexer 19----LED driver 20----Test terminals 21 to 24---- latch

Claims (2)

[Claims] (1) A data processing device characterized by comprising the following components a to e. a, CPU, ROM, D/A converter, test terminal,
Multiple groups of digital and analog ports. b. A latch in which data to be D/A converted is set and supplies the data to the D/A converter. c. When the test terminal is at one logic level, read data from the ROM and set it in the latch, and when the test terminal is at the other logic level, data according to the state of the group of digital ports. means for setting the latch to the latch. d. means for supplying the data of the latch to another group of the digital ports when the test terminal is at another logic level; e. means for supplying the output of the D/A converter to the analog port when the test terminal is at the other logic level; (2) The data processing device according to claim 1, digital peripheral circuits such as ROM, RAM, timer, etc. storing control programs for the image forming device, and control circuits such as various power supplies of the image forming device are integrated on the same chip. 1. A control device for an image forming apparatus, characterized in that the control device is formed as follows.