JPH02228733A - Information processor - Google Patents

Abstract

PURPOSE:To minimize the number of bits of a register and to easily decide each state by outputting a condition code, which indicates the state of data held in the register, together with data after decoding this code. CONSTITUTION:When the operation between contents of registers 3 and 9 is performed in a computing element 7, the condition code is formed by a condition code forming circuit 10 and is set to a register 1. The output of a decoder 2 is used to discriminate whether the condition code meets the branch condition or not. Since the output of the decoder 2 is outputted to a bus 6 together with contents of the register 1 in parallel, this output is operated as a part of contents of the register 1. Thus, the number of bits of the register is minimized and each state is easily decided.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device, and more particularly to an information processing device having a register that holds a condition code together with data.

Generally, information processing devices employ a control method in which it is determined whether or not to perform a branch instruction (jump) based on the content of data held in a register, that is, the state of the data in that register. There are things that are. In this case, a condition code indicating each state of data is held in a register along with the data, and determination is made based on this condition code.

In addition, there were the following methods for holding the condition code. First, there is a method in which the number of types of each state of data is expressed as a binary number, and the number is stored in a register as it is in the binary state. According to this method,
Since the number of bits used for the condition code is minimized, the number of register bits can be reduced.

However, in this method, in order to determine which of the states the current register state is in, it is necessary to perform the determination for each state one by one, which takes time. There is a drawback.

Second, there is a method in which one bit is associated with each state of data, and the data is held in registers with the same number of bits as the number of types of the state. According to this method, it is only necessary to determine which digit of the bit is "1" (or "OJ"), which makes the determination easier and requires less time.

However, this method has the drawback that the number of bits in the register increases, resulting in an increase in the size of the circuits that make up the device.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks, and its purpose is to minimize the number of register bits and to facilitate determination of each state. The objective is to provide an information processing device that can.

An information processing apparatus according to the present invention is an information processing apparatus having a holding means including N bits (N is an integer) in which state data indicating the state of data held within the own means is held, The present invention is characterized in that it has a decoding means for decoding N-bit state data into 2N bits, and outputs the held data and the 2N-bit data decoded by the decoding means.

K-sama Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing the configuration of main parts of an embodiment of an information processing apparatus according to the present invention. In FIG. 1, the information processing apparatus according to an embodiment of the present invention has registers 1.3 and 9
, decoder 2, arithmetic unit 7, buses 5.6 and 8,
Condition code generation circuit 10 and instruction succession mechanism 1
1 and a constant generation circuit 13. Note that unless otherwise specified, numbers in brackets are assumed to be binary numbers.

This example is an example of conditional branching based on the contents of a condition code, and shows a case where the condition code is N-2 bits.

Register 1 is a register containing 2 bits of a condition code.

Decoder 2 converts the 2 bits of the condition code into 4
In this embodiment, the condition code is "00".
rloOO'', r OI J roloJ,
r L OJ to rolo", 'IL' to "0"
001" respectively.

By doing so, each state of the contents of the register, that is, each condition code, corresponds to each digit of the decoded result.

The condition code generation circuit 10 generates a condition code based on the state of the operation in the arithmetic unit 7 (overflow, carry, etc.). Then, the contents of the 2-bit condition code are set in register 1.

The constant generation circuit 13 generates constants according to the contents of the instruction read from the instruction reading mechanism 11.

In addition, in this information processing device, there is an instruction to calculate the contents of register 3 and the contents of register 9, an instruction to calculate the contents of register 1 and the above-mentioned constant, and the result of the previous calculation in calculation unit 7. It is assumed that a conditional branch instruction is defined that branches depending on the result of determining whether the value is 0 or not.

In such a configuration, branching is performed depending on the condition code when the contents of register 3 and the contents of register 9 are operated. First, the contents of register 3 and register 9
When the arithmetic unit 7 performs an operation with the contents of , a condition code is generated by the condition code generation circuit 10 and set in the register 1. Therefore, register 1
The number of bits can be minimized.

Here, the output of the decoder 2 is used to determine whether the condition code matches the branch condition.The output of the decoder 2 is output to the bus 6 in parallel with the contents of the register 1. By doing so, the operation can be performed as part of the contents of register 1. Figure 2 conceptually shows this situation.

In FIG. 2, 21 is the contents of the register 1, that is, the data held, and 22 is the output of the result of decoding the condition code by the decoder 2.

In other words, since the contents of register 1 itself and the decoded result of the condition code are output to bus 6 in parallel, logical operations can be performed on the original contents of register 1, and it is also easy to determine the condition code based on the decoded result. This means that it can be done.

Next, a specific example of condition code determination will be shown.

In order to determine the condition code, the contents of the register 1 including the output of the decoder 2 and a constant generated by the constant generation circuit 13 are operated.

Here, the condition code is "00" or "0".
1”, we want to branch, then decoder 2
A branch will be taken when the output of is riQOOJ or roloo. Therefore, the corresponding bit is set to "1",
The other bits are set to 0, and the constant expanded to the bus width is ANDed with the contents of register 1. In this case, if the bus is a 16-bit bus, the constant is rQQOc.
”(L hexadecimal)-rlloo.

Therefore, if we perform an AND operation on this constant r11QO'' and the output of decoder 2, the result will be r 0000 J
(In other words, aρgO), it is possible to determine whether the branching condition is met with only one operation. If the result of the operation is not aρgO (that is, if it is true), the branching instruction is executed. Note that an instruction is given in advance from the instruction successive mechanism 11 so that the constant generation circuit 13 generates a constant according to the branch condition.

In other words, according to this embodiment, a conditional branch based on a condition code can be realized only by calculating - degrees.

In addition, in this embodiment, the case where the condition code before decoding is 2 bits has been explained, but the condition code is 3 bits.
It may be bits or 4 bits, and the number of bits is not limited to that number because it corresponds to the number of types of states of the contents of the register. In those cases, the data after decoding becomes 8 bits and 16 bits, respectively.

In addition, in this embodiment, conditional branching using condition codes has been explained, but this is not limited to this case.
According to the present invention, by performing a single logical operation on the decoded output that is output together with the contents of the register, the result of determining the state of the contents can be reduced to a 1-bit numerical value. It can be widely used in information processing devices, etc.

As explained above, the present invention minimizes the number of register bits by decoding the condition code indicating the state of data held in the register and then outputting it together with the data. This has the effect of making it easier to determine each state.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the main parts of an information processing apparatus according to an embodiment of the present invention, and FIG. 2 is a conceptual diagram showing the contents of data on the bus 6. As shown in FIG. Explanation of symbols of main parts 1.3.9 ・・・・・・ Register 2 ・・・・・・
- Decoder arithmetic unit condition code generation circuit instruction continuous generation mechanism constant generation circuit

Claims (1)

[Claims] (1) An information processing device having a holding means including N bits (N is an integer) in which state data indicating the state of data held in the own means is held, the N-bit state data being stored in 2^N bits. 1. An information processing apparatus comprising: a decoding means for decoding the stored data; and outputting the held data and 2^N-bit data decoded by the decoding means.