JPH02228751A - Information processor - Google Patents

Abstract

PURPOSE:To prevent a central processing unit from being restricted when the state of a channel device is not specified, namely, when an input / output instruction is generated by competition by supervising the operating state of the channel device and informing channel device availability of the central processing unit when a usable state is determined. CONSTITUTION:After it is informed of a central processing unit 1 by a channel device use informing means 61 that a channel device 2 is under using, the channel device availability is informed of the central processing unit 1 when the usable state of the channel device 2 is detected with a channel device supervising means 62. Accordingly, at the time of the competition, it is responded to the early released I/O instruction that the channel device is under using. Then, the restricting time of the CPU to the I/O instruction an be shortened. Thus, when the state of the channel device is not determined and the competition of the I/O instruction is generated, the restricting time of the CPU is shortened.

Description

Detailed Description of the Invention (Summary) A channel processing device comprising an input/output processor that controls an interface to a central processing unit and a channel device to control an interface to an input/output device, When an input/output start command is output from the central processing unit to the input/output processor to instruct input/output operations,
The input/output processor is an information processing device that instructs the channel device to perform the input/output operation and releases the central processing unit, and includes processing requests from the input/output device to the channel device;
The purpose of the present invention is to prevent the central processing unit from being constrained when the status of the channel device is uncertain, which occurs due to competition between input/output commands from the central processing unit to the channel device. a central processing unit channel device in use reporting means for reporting to the central processing unit that the channel device is in use when an input/output activation command for the input/output processor is input to the input/output processor; After that, the channel processing device is provided with channel device monitoring means for monitoring the operating status of the channel device and, when the state of the channel device is determined to be usable, to report the availability of the channel device to the central processing device. do.

[Industrial application field]

The present invention provides a central processing unit (hereinafter abbreviated as CPU) that outputs early release type input/output activation instructions, and an input/output processor (hereinafter referred to as IO) that controls an interface to the CPU.
A channel device (hereinafter referred to as IOD) that controls the interface on the input/output device (hereinafter referred to as IOD) side
In an information processing device consisting of a channel processing device (hereinafter abbreviated as CHP) consisting of a channel processing device (hereinafter abbreviated as CHP), IO
Processing request from D to CHE and C to the CHH
This relates to control when input/output instructions (hereinafter abbreviated as I10 instructions) from the PU conflict.

[Conventional technology]

In information processing devices, the operating speed of CPUs has been increasing year by year. However, the operating speed of the IOD is much slower than that of the CPU due to the propagation delay on the cable and the physical operation of the IOD itself. Therefore, synchronous type! 10
When a command is issued, the CPU is dragged down by the response speed of the IOD, and as shown in the time chart of FIG. 4, the CPU appears to stop until a response is returned from the IOD.

Said! In order to prevent the processing speed of the information processing device from decreasing due to the issuance of 10 instructions, an early release type as shown in the time chart in Figure 5! Ten commands were devised.

FIG. 7 is a flowchart of a control program activated by the IOP. The I10 instruction is output from the CPU to 10P (time chart 51 in Figure 5, flow chart 71 in Figure 7), and the I10 instruction is an input/output activation command (hereinafter referred to as 5).
(abbreviated as IOF instruction) (Flowchart 7 in Figure 7)
2), IOP is in CHE state. After confirming that the channel status (hereinafter abbreviated as CH3) and subchannel status (hereinafter abbreviated as SCH3) are usable (Flowchart 1-7 74 in Figure 7),
Read the external register that stores information on whether or not the CHE can accept processing requests from the IOP (whether the CHE has started processing in response to a request from the IOD) (see the flowchart in Figure 7). 75), said CH
If E is not in operation (not performing processing according to a request from IOD and can accept processing requests from IOP), the CPU is freed (time chart 56 in Fig. 5, flow chart 76 in Fig. 7). , launch the CHE (7
7).

Thereafter, CHH access to the IOD is performed after releasing the CPU (52), and after the operation (53) is completed,
Report to CPU by interrupt (54.55).

In the above process, if CH3 and SCH3 are not available, the IOP reports "channel in use" to the CPU (7B) and releases the CPU. Thereafter, when the channel processing is completed, a corresponding report is made to the CPU, and with this as an opportunity, the CPU outputs a command to the IOP again.

Now, even if CH3 and SCH3 are available (73,
74L CHE may be currently running (75),
This is a case where the CHE is about to start some kind of processing, and the processing has not yet been reflected in the states of the CHE and SCH3. The processing start is reflected in the external register of the IOP as to whether or not the CHE is operating. This information only indicates that the CHE microprocessor is performing some processing, and the status of CH3 and SCH3 is determined by the completion of the CHE microprocessor's operation. If processing is not completed, CH
3,5CH5 remains usable. In other words,
IOP is when the CHE cannot determine what kind of processing it is about to perform.

In the above case, the IOP does not release the CPU, but instead uses CH3,
72, 73.7 until the state of SCH3 is determined, that is, until the CHE microprocessor finishes processing.
4.75 and idle loop.

[Problem to be solved by the invention]

Now, when the CHE starts some processing (CH3
, when SCH3 is not determined) means that from 10D to CH
This is the time to asynchronously report the status to E. The asynchronous status report can be roughly divided into two types.

■ If a previous data transfer was interrupted for some reason and the IOD requests its resumption.

In this case, data transfer is restarted, so CH3
and the status of 5CHS becomes in use, and 20P reports "Channel in use J to the CPU and releases the CPU (7th
Figure Flowchart 78).

■ If the IOD simply sends the status.

For example, when post-processing related to executed data transfer is completed, when notifying that an abnormality has occurred in the device, etc.

In this case, once the CHE receives the IOD status, CH3 becomes available. After receiving the device status, SCH3 becomes "interrupt pending" in order to report the IOD status to the CPU later.

However, the status report from 10D may be withdrawn midway through. For example, in a magnetic disk device, etc., when reporting the status that the head has completed moving to a specified position, the response from the CHE side is delayed for some reason, and the disk needs to rotate again. This is the case. At this time, the IOP will remain in the loop (7) until the CHE is able to accept the IOP's request due to the withdrawal of the report.
1°72.73.74.75 and idle) will be repeated.

If the 5IOF command conflicts when the channel state is uncertain (when the status report from the IOD starts), the CPU is forced to wait for execution until the channel state is determined, resulting in a longer CPU time.

In the worst case, if the 100 stops when requesting to start a status report, the delayed response will tie up the CPU until the CHE detects the interface failure, and the early release type I10 instruction is used to There's no point in being there anymore.

Furthermore, if you have multiple systems with the same configuration, failures may occur.
Particularly in a hot standby system that prevents interruption of operations by switching to another system due to a delay in response, the CPU stoppage due to withdrawal of the status report is sufficient time to perform system switching. However, the problem is that system switching occurs due to an interface failure.

Therefore, an object of the present invention is to solve all the above problems and to
OD processing request to CHH and I1 to IOP
To provide an information processing device in which a CPU is not delayed when 0 instructions conflict.

[Means to solve problems]

In order to achieve the above object, the present invention enables the central processing unit to use the channel device when an input/output activation command for the channel device is input from the central processing unit to the input/output processor when the status of the channel device is uncertain. a channel device in use reporting means for a solid processing device that reports that the channel device is in use; and after responding that the channel device is in use due to the status of the channel device being uncertain, monitoring the operating status of the channel device, and determining that the state of the channel device is in the available state. The channel processing device is provided with channel device monitoring means for reporting to the central processing unit whether the channel device is available for use.

[Effect]

After the channel device in use reporting means reports that the channel device is in use to the central processing unit, when the channel device monitoring means detects that the channel device is available, it informs the central processing unit that the channel device is available. The structure shall be configured to inform.

〔Example〕

FIG. 1 is a block diagram of an embodiment of the present invention.
is CPU, 2 is IOP, 3 is C', H3, 4 is SCH3
, 5 is an external register, 6 is an IOP control program, 61 is a central processing unit channel device usage reporting program, 62 is a channel device availability monitoring program, 7 is a CHE, 8 to 11 are IODs, and 12 is a CHP. . The central processing unit channel device usage reporting program 61 and channel device availability monitoring program 62 are started at l0P2. FIG. 2 is a flow chart diagram of the channel device usage reporting program 61 for the central processing unit and the channel device availability monitoring program 62 in FIG.
FIG. 3 is a time chart diagram of the embodiment.

The present invention will be explained below with reference to the drawings.

If the I10 instruction is issued from the CPUI (Flowchart 21 in Figure 2 and Time Chart 31 in Figure 3), and the I10 instruction is a 5IOF instruction, CH33, 5 is issued as in the conventional example.
Check if CH34 is available (23.24). If it is not available, the CPU will display "Channel in use" as before.
Report to I and release the CPUI. The I10 instruction is 5
If it is not an IOF instruction, perform processing accordingly (20
0). I10 instructions other than the 5IOF instruction are “clear I1
0 instruction" and "Test I10 instruction"°, these are synchronous type I10 instructions.

The above processing is similar to the conventional example.

Now, suppose that 5CH54 is available (24). Then read external register 5 and CHE
If CHE7 is not processing, inform the CPU that it can be processed and release CPU 126), and start CHE7 (
27).

Now, assume that as a result of reading the external register 5, the CHE 7 is performing some operation. In other words, the I10 instruction for CPUI's l0P2 and l0DB
This is when there is a conflict of I10 requests to CHE7. As described in the related art, it is assumed that an asynchronous status report, etc. is started (25. Flowchart 33 in FIG. 3).

At this time, 10P2 is below channel availability report C, CA
(abbreviated as I)28), "Channel in use j"
Report to the PUI and release the CPUI (Flow chart 29 in Figure 2, Time chart 32 in Figure 3)).

After that, it is determined whether it is a pending process (203), and further C
It is determined whether the AI report is pending (204). Since it is on hold, check if CH33 is available (20
6), external register 5, if available
It is checked whether CHE is running (208). If the CHE is vacant, a CAI is issued to the CPUI, and the CPUI activates the 5IOF instruction again.

If the CHE7 is not empty, the program loops to 21, and since CAI is pending (203), the CH
It is determined whether E7 can be used. That is, the channel device availability monitoring program 62 is executed again.

Now, when it is determined in process 206 that CH33 is not vacant, the CAI report suspension is released (207).
Since the data transfer has started due to the request from the 10DB side, the report indicating that CHE7 is now available will be sent to the CHE processing request (201, 202).
).

Now, in this embodiment, the processing request from the l0D8 side and the c
Even if I10 requests from pui conflict, CPU
, so there is no processing delay.

In addition, if the status report from IOD is withdrawn midway,
The channel device availability monitoring program 62 monitors the time when the channel becomes "available" again at regular intervals, so if the CHE status of the external register 5 indicates "available", the channel device availability monitoring program 62 makes it available to the CPUI. Report possible.

In this embodiment, in response to an early release type I10 instruction at the time of contention, a response indicating that the channel is in use is sent. This results in I1
It is possible to shorten the CPU constraint time for the 0 instruction.

Additionally, as previously discussed, there is no CPU switching in a hot standby system when an IOD fails during contention.

The present invention has been described above according to examples. In the example,
Although the channel device availability monitoring program is configured within the suspension process, the present invention is not limited to this.

As shown above, the present invention can be modified in various ways in accordance with the gist of the present invention, and these modifications are not excluded.

[Effect] When the state of the channel device is uncertain, the CPU lock time when early release type I10 instructions conflict is significantly shortened. Therefore, the processing performance of the system is significantly improved, and even if a relatively minor failure such as an interface failure occurs, the CPU will not be stopped more than necessary, thereby preventing system switchover from occurring in the standby system. can.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
In the figure, 62 is a flow chart of the channel device availability monitoring program for the central processing unit, FIG. 3 is a time chart of the embodiment, and FIG. Figure 5 is a time chart when executing a conventional early release type ■/○ instruction, Figure 6 is a time chart when a conflict occurs, and Figure 7 is a time chart when a conventional ■○P instruction is executed. FIG. 2 is a flowchart of a control program. 1...CPU 2...10P 3...CH3 4...5CH3 5...External register 6...IOP control program 61...Central processing unit channel device usage reporting program 62.・・Channel device usability monitoring program 7 ・ ・ ・ CHE 8~9 ・ ・ ・ IOD Kisou 9 1/) 70. ``Rough'' old name 1 Figure CPt1 Futu WMf 閘宷also meeting rumors汅GItime time+!-to shame)'ty be CpLI 4上时閘）Yueshi IQ time child〒-1-1p No. 1

Claims (1)

[Claims] An input/output processor (2) and input/output devices (8 to 11) that control an interface to the central processing unit (1).
Channel device (7) controlling the side interface
a channel processing device (12) consisting of a ) is the channel device (7
) instructs the input/output operations to the central processing unit (1), and when the status of the channel device (7) is uncertain, the central processing unit (1) instructs the channel device (7) to perform the input/output operation and releases the central processing unit (1). When the input/output activation command for 7) is input to the input/output processor (2),
Central processing unit channel device usage reporting means (for reporting to the central processing unit (1) that the channel device (7) is in use;
61), and after responding that the channel device (7) is in use due to an uncertain status, the operating status of the channel device (7) is monitored, and when the state of the channel device (7) is determined to be available, Channel device monitoring means (6) that reports availability of the channel device (7) to the central processing unit (1).
2) is provided in a channel processing device (12).