JPH02228783A - Image processor - Google Patents

Abstract

PURPOSE: To realize relative addressing being a mechanism efficient for displaying the copy of an object by using an index register. CONSTITUTION: A coordinate staging part 15 contains an adder 31, a loading control state machine 33, a multiplexer 35, an XY coordinate register 37, a clip register 39, a raster offset register 41, index logic 43, test window control logic 45, a comparison logic/result storage device 47, a comparison control state machine 49 and state generation logic 51. The loading control state machine 33 for controlling the operation of the index register contained in index logic 43 is realized. Thus, data can be received at speed as fast as possible, total waiting time can be shortened and throughput can be reduced.

Description

[Detailed description of the invention] [Summary of the invention] The invention deals with degenerate quadrilateral objects, i.e. points.

An index register that cycles through 0, 1, 2.3 is used to store the coordinates of the four vertices of a quadrilateral object that includes lines and triangles and is to be displayed by the graphics display system. and loading device. In this way, the software ° commands specify the minimum number of x, y coordinate pairs to define the object: one pair of coordinates for a point, two pairs of coordinates for a line, two pairs of coordinates for a triangle, In the case of a rectangle, it is only necessary to define three pairs of coordinates, and in the case of a rectangle, two pairs of coordinates (by defining opposite corners).

The present invention further implements relative addressing, which is an efficient mechanism for representing replicas of objects, through the use of index registers. Relative addressing is best explained by the following example. The three vertices of the triangle are xol yo l x,
l y, and X2. Y. 150 pairs of Xs to replicate this object 50 times at different locations on the graphics display.

It will be necessary to remember the Y coordinate. When using relative addressing Zing, one vertex is the origin xol y
o, and the second and third vertices are offsets from the previous vertex, namely ΔXo, , ΔYOI and ΔX12. It is defined as ΔY12.

Note that ΔXab or ΔYab represents the difference between XIl and Xb or the difference between y and Yb. When replicating an object 50 times, for each replication (i.e., for each of the 50 object origins) we have two pairs of offsets and a new Xo,
All you have to do is memorize Yo.

The present invention will be described in the context of a graphics subsystem in which the comparison of coordinates and the clip window required to perform clipping is performed in eight-dware. The present invention performs the clipping of images to be displayed on a video display device in hardware to the extent possible, and in software includes images or portions of images that cannot be reliably clipped using the graphics subsystem of the present invention. form part of the device that leaves only the

〔Example〕

The present invention relates to the graphics subsystem of an engineering workstation.

Finally, the coordinate staging block and coordinate comparison provide the storage capacity and comparison information necessary to support arbitrary quadrilateral drawing with clipping and block image transfer with clipping (BLIT). A logic block (see FIG. 1) is provided. In either case, it is necessary to specify four pairs of X/Y coordinates and to specify the clipping window boundaries.

Supporting quadrilateral drawing suggests that the four vertices that define the quadrilateral can be used. The embodiments of the invention disclosed herein impose few restrictions on these vertices. The vertices are stored in four pairs of registers (one pair of registers consists of one register for the X coordinate and one register for the Y coordinate), and the vertex number O
to 3. Vertex O is connected to vertex 1,
Vertex l is to be connected to vertex 2, vertex 2 is to be connected to vertex 3, vertex 3 is to be connected to vertex O, and there is no connection between vertex 0 and vertex 2 or vertex l and vertex 3. Make it not exist. The coordinate staging section and comparison logic form the first stage of the pipeline that ultimately performs the storage of a specified quadrilateral into display memory. The stages that follow those stages in the pipeline have information about the relationship between each vertex and its neighbors (i.e., for vertex l, Xl and XO, Yl and YO, XI and X2, and Yl and Y
2). This information is necessary in order to properly supply the functional addressing block with a series of trapezoids that, when combined, accurately represent the original quadrilaterals. Decomposition of any quadrilateral and coordinate ordering are performed by logic.

Additionally, relationships between vertices and appropriate ripping boundaries are also required to support clipping to quadrilateral clipping boundaries in subsequent pipeline stages. In one example, this means comparing all X vertices to both the minimum X clip boundary and the maximum clip boundary. A similar series of comparisons is required for the Y coordinate. In some cases, these comparisons are
It can also indicate whether the object has visible (non-clipped) parts. By pre-identifying non-visible objects, the use of subsequent pipeline stages can be avoided since visible pixels are not identified for writing to the display memory. This is a performance advantage in that the drawing of the quadrilateral can be considered to have occurred immediately after the analysis of the clipping information.

The preferred embodiment of the graphics system described herein utilizes 16-bit two's complement arithmetic in determining the pixels associated with a line segment. This operation involves taking the difference between the X and Y vertices of the two line segments. To avoid arithmetic overflow, set the numerical range of X vertex value and Y vertex value to 1.
In other words, -214 and (2
”-1).

In support of this, checking the numerical range of vertices is performed by coordinate comparison logic.

When supporting BLIT, two vertices specifying the opposite corners of the source (SR(2) rectangle and the destination (Dgs'r
) four vertices are required, two vertices specifying opposite corners of the rectangle. The intent of the BLIT operation is to copy the pixels contained in the SRC rectangle to the DgST rectangle. In this example, the upper left corner of the SRC rectangle is stored as vertex 0, and the lower right corner of the SRC is stored as vertex l.

Similarly, the upper left corner of DEST is stored as vertex 2, and the lower right corner is stored as vertex 3. DEST SRC
In order to copy correctly, care must be taken when two rectangles overlap. When overlap occurs, the order in which pixels are copied is constrained if necessary to obtain correct results. This is a problem well known to painters. The information required to properly define pixel copy constraints includes SRC rectangle boundaries and DBST
There is a comparison with a rectangular boundary. This is the associated X coordinate and Y
Required for both coordinates.

Additionally, to support clipping of both SRC and DEST rectangles in subsequent stages of the pipeline, relationships of SRC' and DEST vertices with appropriate ripping boundaries are also required.

In this case as well, it is conceivable that either the SRC rectangle or the DEST rectangle is completely hidden (not visible) and there is no need to use the subsequent pipeline stage.

This is one performance advantage in that the execution of BLIT can be considered to have occurred immediately after the analysis of the clipping information.

The coordinate staging control logic supports multiple methods for obtaining coordinate values. Correspondingly, the coordinate comparison logic maintains the necessary comparison information regardless of how the coordinate values were provided.

The various methods of obtaining coordinates can be summarized as absolute, indexed, and relative. The particular method employed is determined by the address of the register used by the KCPU to identify the register to be loaded. The absolute coordinate value is
It is shrouded by storing the actual value provided to the register addressed by CPUK. This loading method is used when loading clip boundary registers and raster offset registers, as well as individual coordinate registers, as described below. The second method, indexing, is used to efficiently load multiple coordinates with the same value. In this case, the value supplied by the CPU is 1
The appropriate raster offset register (raster offset
). Addition of raster offset is done by CPU
This provides a means of offsetting the X/Y address space provided by the display to another area of display memory.

The index-directed loading mechanism utilizes a two-bit index to guide itself and represent how many and which coordinate registers to load during a given cycle. C
When PU identifies a degenerate quadrilateral, a point has a pair of X/Y
In the case of a line, two pairs of X/Y
, it is this mechanism that allows K to specify three pairs of X/Y in the case of a triangle. When any one of the above degenerate quadrilaterals is loaded into a four vertex register, one or more vertices will be repeated.

Subsequent stages of the pipeline can always interpret the defined object as a quadrilateral (even if it is a degenerate quadrilateral), and can never
This repetition is necessary to avoid treating all (j l triangles) as special cases. Further, according to the index instruction loading method, in order to correctly define all four inner parts of a quadrilateral corresponding to a rectangle, it is only necessary to input two opposing corners of the rectangle.

The third loading method, the relative method, allows the CPU to
It is used to specify only the difference between the most recently input coordinates and the desired new coordinate values. In this case, the CPU supplied delta, or offset, is added to the previously loaded coordinates before being loaded into one or more registers.

The coordinates most recently entered for the required addition (vert
A two-bit index is used to indicate x(1ndex-1) mod 4), which further indicates which register should be loaded, as in index-directed loading.

The end result is that the CPU is free to choose which method it supports to load the coordinate registers. When either operation - draw quadrilateral or BLIT is actually requested (after the coordinates have already been loaded), the current state of the four vertices, regardless of how they were obtained, is used directly. This is the CPU
give you maximum flexibility.

FIG. 1 is an overview of a graphics subsystem in which the present invention may be utilized. Path interface logic 11
is connected to a central processing unit (not shown) via an address bus, a data bus, and a control bus. The functional components of the graphics subsystem are a data path/memo interface 13, a coordinate staging section 15, a coordinate sequencing section 17, a functional addressing block 19, a mask generation block 21, and a linear address generator 23. It is.

Data path/memory interface 13 updates a frame buffer (not shown), which is a memory that stores graphical information to be displayed on a video display device such as a CRT. That is, data loaded into the frame buffer is accessed by video circuitry, which converts the data into appropriate electrical signals to turn on and off individual pixels of the video display. The data supplied from the bus interface logic is sent to the coordinate staging section 15;
Coordinate ordering is part 17, and function atrage/double block 1
9 is changed by the mask generation block 21 and the linear address generator 23. Functional Address Cinder block 19 further performs some of the ripping necessary to fit particular graphical objects into the clip windows in which they are to be displayed, and then forwards the signal to Mask Generation block 21.

The mask generation block 21 arranges the information from the beginning of the visible object to the end υ for each scan line and as 16 pixel sections used to address the data path/memory interface 13.

The mask generation signal is also provided to a linear address generator 23 which uses the addresses provided by the mask generation block 21 to linearly address the frame buffer for transfer to the output display device. Convert to a signal. One embodiment of the data path/memory interface 13 is found in co-pending application filed on May 1, 1988, application no. One embodiment of the coordinate ordering block 17 is found in the co-pending application filed on 1999-2007, and one embodiment of the functional addressing block 19 is found in the co-pending application filed on Are listed. One embodiment of the linear address generator 23 is:
It is stated in the co-pending application - application number - filed on the following day. The present invention resides in the coordinate staging unit 15, and as will be described in detail below with reference to FIGS. The present invention relates to a circuit that performs a number of operations on the basis of an input to generate information in the nature of a control signal that enables block image transfer (BLIT) to be performed. Accordingly, the present invention is directed to specific circuitry within the coordinate staging section 15.

It is well known to those skilled in the art how to implement the various timing and control signals necessary for the proper operation of the above-mentioned functional blocks that make up the video display system; , explanation thereof will be omitted except where deemed necessary for a correct understanding of the present invention.

Next, FIG. 2 will be explained. FIG. 2 shows an overview block diagram of the coordinate staging section 15. As shown in FIG. The coordinate staging section 15 includes an adder 31, a loading control state machine 33, a multiplexer 35, an XY coordinate register 37, a clip coordinate register 39, a raster offset register 41, an index logic 43, and a test window control logic 45. , a comparison logic/result storage 41 , a comparison control state machine 49 , and state generation logic 51 .

Before describing the characteristics of the invention, a brief description of how objects are displayed is provided below to aid in understanding the manner in which the invention is implemented.

The X and Y pairs of vertices represent video display coordinates. In the case of a normal display device, Xf'i is in the range of 0 to 1151, and Y is in the range of 0 to 899. Each X coordinate and each Y
Coordinates are stored in separate 32-bit registers or in a pair of 16-bit registers. Maximum screen coordinates (i.e. up to 65535, in other words -
32768 to +32767) 16
Although bits are more suitable, the most widely used data type for graphical software is 32-bits.
Thirty-two bits of information are stored because these 32 bits provide a range large enough to handle most real-life objects far beyond the range of video display devices.

A quadrilateral object has four pairs of vertices (Xo, To),
(x, .

Y+ ), (X2, Y2) and (x3+ Y
3) is expressed as a combination. If the object is a point,
All four pairs of vertices are the same, so three points are repeats of the previous one. If the object is a line, two of the four pairs of vertices (or three of the four pairs of vertices) are repeated. If the object is a triangle, four pairs of vertices are repeated. If the object is a quadrilateral, all four pairs are different. An object (i.e., a point, line, triangle, or rectangle) is defined by the minimum number of non-repeating vertices necessary to completely define the object, i.e., one pair for points and two pairs for lines. , is most efficiently defined using three pairs of vertices for a triangle, four pairs for a quadrilateral, and two pairs (opposing corners) for a rectangle.

When a block image transfer (BLIT) operation should be performed,
The four X/Y registers have the following translations and are loaded accordingly.

XO - the X coordinate of the upper left corner of the source block YO - the Y coordinate of the upper left corner of the source block X1 - the X coordinate of the lower right corner of the source block Y1 - the Y coordinate of the lower right corner of the source block X2
- X coordinate Y2 of the upper left corner of the destination block - Y coordinate X3 of the upper left corner of the destination block - X coordinate Y3 of the lower right corner of the destination block - Y coordinate of the lower right corner of the destination block Image to be displayed on a display device such as a CRT is a random access memory I known as a frame buffer
The pixels are formed as individual pixels stored in one or more planes of J (RAM). Note that in the case of a color system, the number of planes is usually eight. The data stored in the frame buffer consists of a pair of coordinates X and Y
addressed by. A pair of X and Y identifies one particular pixel in every plane, where X is a row.

Y is a column. One pixel is defined by a single bit taken from each plane. Thus, if eight planes are utilized, each displayed pixel is defined by eight bits of the frame buffer. In this way, one bit of one pixel is used to specify whether that pixel is on or off, and
The remaining 7 bits specify the pixel color, or
All eight bits are used to specify colors, one of which is the same as the background color of the display, thereby allowing the pixel to be turned off.

The invention primarily consists in implementing a loading control state machine 33 that controls the operation of index registers included in index logic 43. In this regard, the operation and construction of the other functional blocks shown in FIG. 2 will be described in only as much detail as is necessary for a proper understanding of the invention.

Adder 31 is a 16-pit or 32-bit two's complement binary adder with two inputs, DataIn derived from bus interface logic 11 and representing the input data from cptr, and raster offset register 4'. r, and an input from MUX 35, which is a multiplexer that selects one of a set of inputs obtained from X/Y coordinate register 37 and clip coordinate register 39, respectively. The inputs from MUX 35 are selected by signals generated by loading control state machine 33, as described below.

Next, the adder 31 and the multiplexer 35 will be explained in detail with reference to FIG. In FIG. 3, the adder 31 is 1
Shown as a 6-bit adder. In this regard, in the preferred embodiment, DataIn is 32 bits and the timing requirements of the pipeline utilized by the present invention are reduced by two steps to save space on the integrated circuit on which the present invention is implemented. Although it would be possible to use a 32-bit adder because . The differences when using a 32-bit adder will be obvious to those skilled in the art and will not be discussed here.

The multiplexer 35 actually consists of a pair of multiplexers 35B and 35b, and one upper and lower one of DataIn.
A third multiplexer 36 is used to input 6 pits. The multiplexers 35 & and 35b are
The upper and lower 16 pits are each received from seven 32-bit input terminals. The input details are one 16-bit input (extended to 32 bits with a sign) from the raster offset register 41 and three inputs from the X/Y coordinate register 37.
There are four 2-bit inputs and two 16-bit inputs (extended to 32 bits with sign) from clip coordinate register 39. The outputs of multiplexers 35a and 35b are combined to output the signal Da taout (C of these register values).
a fourth multiplexer 40 which passes the output of multiplexer 35& whenever the upper pit from X, , -X, or yo-Y3 is being accessed;
is also entered. Multiplexer 40 otherwise selects the output of multiplexer 35b. °The output of the multiplexer 40 is input to one input terminal of the logic gate 42, and the logic gate 42 is connected to one input terminal of the multiplexer 40.
Passes 6 bits of output or 16 bits of zero.

In particular, each time a bit of DataIn is provided by the multiplexer 36 to directly load (absolute load) a register in the raster offset register 47, the X/Y coordinate register 37, or the clip coordinate register 39, the logic gate 42 sends out a zero. Third
Logic circuits 44 and 46, further illustrated in the figure, perform the following functions. When the addition of the lower 16 bits is in progress, the AND game! Gate 44 causes its output to go low, causing adder 31 to perform a "0" carry-in.

The carrier of this addition is saved in flip-flop 46. During addition of the upper 16 bits, the output of flip-flop 46 is applied to the carry-in of adder 31 via AND gate 44. This combination results in a two-cycle 32-bit addition that is equivalent to a single-cycle 32-bit addition.

Adder 31. Raster offset register 41°X/Y
Coordinate register 37. Clip coordinate register 39, test window control logic 45 and comparison logic/result storage 49
The operation of is coordinated by the loading control state machine 33 and the compare logic state machine 49, and the functional blocks described above operate to cause data to flow along the pipeline. Accordingly, not all of the control lines emanating from the loading control state machine 33 and the compare logic state machine 49 are shown, but details thereof are provided below in the description of the loading control state machine 33 and the compare logic state machine 49. from,
It will be readily apparent to those skilled in the art.

Referring to FIG. 4, the X/X coordinate register 37 stores (Xo, Y, ) to (x,) of the object to be depicted.

Ys) A series of 16-bit registers that store vertices. One 16-bit register is used to store the upper 16 bits of each X coordinate and another 16 bit register is used to store the lower 16 bits of each X coordinate. Similarly, another 16-bit register holds the upper 16 bits of each X coordinate, and another 16-bit register holds the upper 16 bits of each
Holds the lower 16 bits of the coordinates. These registers are shown in FIG.
It is shown as an XOU representing the upper 16 bits of the L and Xo coordinates. In addition, registers XIL to X3L and XI
U-X3U represents the lower 16 bits and upper 16 bits of the X, -X3 coordinates, respectively.

Similarly, registers YOL 5-Y3L and YOU~Y3
U stores the lower 16 bits and upper 16 bits of the Yo to Y3 coordinates of the object. xo, yo refers to the corresponding pair of registers, i.e., XOU, XO
Refers to the 32-bit value stored in L, YOU, and YOL.

6 pairs of registers (XOL, YOL) ~ (X3L, Y3
L) is coupled to a pair of multiplexers that are used to select either the corresponding X or Y register. For example, registers XOL and YOL are coupled to multiplexers 61M and 61b. Loading control state machine 33 generates a signal that causes multiplexer 51a to select an input from register XOL or an input from register YOL depending on whether the X or X coordinate is to be acted upon. The multiplexers 621L and 62b to 64& and 64b are
6 pairs of registers (XIL.

YIL) to (X3L, Y3L) operate in the same way. multiplexer 61
The outputs of a-54a are sent to multiplexer 35b, and the outputs of multiplexers 61b-64b are sent to comparison logic/result storage 4T.

Block 67.6 labeled all 0s all 1s
9.71 and 73 are logic circuits that respectively test the upper 18 pits of the corresponding pair of X, X coordinates for an all-zero state or an all-one state.

16 of those bits are in a register (XOU.

The 17th and 18th bits are obtained from the group (XOL, YOL~
These are the top two pits obtained from the corresponding registers in (X3L, Y3L). In FIG. 4, the 17th and 18th bit inputs are not shown in order not to unnecessarily complicate the diagram. Multiple pairs of registers (XOU.

The outputs of YOU) to (X3U, Y3U) are sent to the paired multiplexers s1a, 61b to sta,
Similarly to 64b, the signals are respectively input to multiplexers 75 to T8 which select either the X coordinate or the X coordinate.

The outputs of multiplexers 75 to 78 are sent to multiplexer 35.
Sent to a. One of the four bits output from each of the logic blocks 67 to 73 is "l" if the upper 18 bits of the corresponding register are all zero or all l, but in other cases has all four bits zero.

The four 4-bit outputs from blocks 67-73 are input to state generation logic 51.

As shown in FIG. 5, the clip coordinate register consists of four registers: XC1XC11p, XC1XC11p,
YClipMin, YClipMax, and multiplexers 81a and 81b.

83a and 83b. The values stored in the above registers with the same name XC1XC11p, XC
IXCllp, YClipMin, YCIl
pMax defines the left, right, top, and bottom of the currently active window, respectively. These values are generated by the CPU and
It is input to the adder 31. Adder 31 adds O to these values.
As mentioned above, registers XC1XC11p,
XC1XC11p, YClipMin and YCli
Load into pMax.

multiplexer eta and 83 &, multiplexer 8
1b and 83b are in pairs XC1XC11p and XC according to control signals generated by loading control state machine 33 and comparison control state machine 49, respectively.
1l pMax or YCllpMin and YClipMa
Select x. The values from multiplexers 81a and 93a are sent to multiplexer 35 and multiplexer 81
The values from b and 83b are sent to comparison logic/result storage 47 and test window control logic 45.

As shown in FIG.
is two registers XRaaOff, YRasOff
and a multiplexer 53. The values XRa5Off and YRaaOff stored in the above registers with the same name are 4 in the X/Y coordinate register 37.
DataI before being stored in each of the X and Y coordinates of the set
Define the X and Y offsets to be added to n (if necessary), respectively. These values are CPU
generated by XRa5Off and YRaaOff
is memorized. Multiplexer 53 outputs X in accordance with a control signal generated by loading control state machine 33.
Select Ra5Off or YRasOff. The value selected by multiplexer 53 is sent to multiplexer 35.

Test Window Control Logic 45 Next, referring to FIG.
Explain. The CPU moves a predetermined distance from the currently active clipping window, that is, a predetermined number of pixels up and down (in the case of testYV&l), left and right (t e s
t XVa l) offset value tost
Generates XVil and testYVal. That is,
For a given window of the display, there is a ΔX and a ΔY that define a test window that surrounds the actual clip window. This test window eliminates the need to use hardware to calculate the location of objects or parts of objects that are outside the clipping window, in each case where it is advantageous to do so.
The aim is to eliminate it. Details regarding the use of test windows are provided in Co-pending Application - Application No.

4-bit values testXVal and testYVal
are stored in 4-bit registers treatX and testY, respectively. Multiplexer g1 receives the signal MUXEnab generated by loading control state machine 33.
The register ta depends on whether the X or Y coordinate is being affected as determined by la.
stXO value or register testY.

Select one of the values. The output of multiplexer 91 is input to a decrementer 93 and an incrementer 95. The decrementer 93 again determines whether the X or Y coordinate is being acted upon as determined by the signal MUX Enable generated by the loading control state machine 33.

Depending on the value XC1XC11p or &tYC1ipMLn
as a second input, incrementer 95 receives the value XC1XC
11p or YClipMax as the second input. The outputs generated by decrementer 93 and incrementer 95 are:
XTestMln, YTestMin and )('l'estMix, YTostMa
It is called x. The decrementer 91 has XC1XC11p and Y
From ClipMin, 2 to the power of (testX-1) and 2
By respectively subtracting values equal to the (testY-1) power of
Generate s tMin. Similarly, the incrementer 93
C1XC11p and YClipMax, 2 (tes
tX-1) power and 2 to the (testY-1) power (i.e. 2(t...tX-'1) (t...tYt
)) and 2 respectively to generate the values XTestMax and Y To s tMax x.

Loading control state machine 33 and indicator logic 430 - Loading control state machine 33 connects control signal MUXEnable
, Index and Register Enable are a series of control signals, one of which is the raster offset register 41°
A second control signal causes the various multiplexers included in the Y coordinate register 37 and the clip coordinate register 39 to select their respective X or Y inputs, and the second control signal causes the multiplexer 35 to select the input from the raster offset register 41, the /The input from the Y coordinate register 37 or the input from the clip coordinate register 39 is selected.

Index sets the index register included in index logic 43 to 0. A single control signal that increments by l for values of l and 2, respectively, and resets to zero (modulo 4) if the value is 3.

Reglster Enable is a series of control signals, one for each of the registers included in the raster offset register 41, the X/Y coordinate register 37, and the clip coordinate register 39;
The output line from adder 31 can be loaded with a 16-bit value.

The operation of loading control state machine 33 and indicator logic 43 will now be described in an example that is believed to clearly illustrate the details of the construction of the present invention.

As mentioned above, the image to be drawn consists of four pairs of vertices (XO+
YO) ~(x, ly3). The object is a point, line, triangle, rectangle, or quadrilateral. In the case of a point, all four pairs of vertices are the same, and in the case of a line, there are only two pairs of vertices that are different from the others. A quadrilateral has four different vertices. A rectangle is a special case of a quadrilateral, having only two distinct X coordinates and two distinct Y coordinates (by a pair of vertices defining diagonally opposite corners). rectangle). In the case of a triangle, there are only three pairs of vertices that are unique.

The index value specifies which registers should be enabled based on the type of object to be defined.

For proper operation, the Y value precedes the X value.

Except for the rectangular case, the index register is incremented after the X value is loaded into the appropriate register. In the case of a rectangle,
The index register is incremented after both the X and Y values. In this regard, the table below shows the enabled X
Listing the register. Although not shown in the table, it is believed that the enabled Y register corresponds to the enabled X register.

Dotted quadrilateral triangle Table 1 Index values when loading XO, XI, X2. X3-d, X2. X3. XD
X2. X3. XD, XlX0. Xi, X2 XI,
X2. X3 X2. X3. XO0x1x2 XO, Xi Xi, X2 X2. X3
X3, XO, Xi, X2 Kari, XO, XI Kari, xO An important point to note in Table 1 is that the coordinates pointed to by the index register are always written.

The type of write (point, line, triangle, etc.) indicates the number of subsequent registers (modulo 4) that are also written. For example, if the index is 2 when #i1X write is received, then the three registers are X2 and (X2+1)
Modulo 4 and (X2+2) Modulo 4, Tsumushi
2. X3 and XO are favored. A quadrilateral write to Y is considered to affect only Y2.

Examples 1-3 below illustrate the role of index registers in defining an object. Each line of the example describes the intended write operation, the index register value used by the loading control state machine to manage the loading of the coordinate register, the value stored in the coordinate register after the write, and the index after the write cycle is complete. value. The short name for the write command is Pnt X or Pn, which indicates black writing.
tY.

LineX or LineY indicating line writing, TriX and TriY indicating triangular writing, Q indicating quadrilateral writing
uadX and QuadY, and ReetX and RectY for rectangular write operations. The actual write operation specified by each write one command is actually a multi-clock cycle operation, as described below.

Throughout the examples below, the execution time of the commands is irrelevant.

As a means of clarifying how the following examples are to be interpreted, a first example will be explained. From that explanation, the meaning of the second and third examples should also become readily apparent.

P n t Y (5) At the time the command is received, all coordinate registers store the value "0" and the index is rl
Equal to J. The PntY(6) command indicates that a point with value 6 should be loaded into the Y coordinate register. The index is l
Therefore, according to Table 1, the input values (6) are Yl, Y
2. Should be stored in Y3 and YO. Next command P
When nt X (3) is received, convert point 3 to Xi,
．． It is instructed to load into X3 and XO. The index is incremented (modulo 4) at the end of the write cycle, as is the case after the end of all index indication X coordinate writes.
. The next write command is LineY (9). The index for this load is 2, and according to Table 1, Y2. Y
9 is loaded into 3 and YO. The last write command in this example is Lin@X(7). According to Table 1, X
2°X3 and XO are loaded with 7, after which the index register is incremented again. The final state of the coordinate register is two distinct vertices (three vertices at (7,9), and (
3, 6).

Geometrically speaking, this is, as expected, a single line with endpoints at (7,9) and (3,6).

First example Specified inclusion of line (3,6) (7,9) LineY (9) Writing LineX (7) Writing second example Triangle (1,5) (9,3) (4,6) Specification of 1 connection 0′ 硅♀ 1′ 禨Tri＼馨書TriY(6) Write TrlX(4) Write O303 3rd example Rectangle (0,7)(8,7)(8,1)(0,
1) Specification R””4(j) 94413611 02 03 book R@tsu♀) 04403611 03 00 book RectQg) o, i, io? In the first example of Book 711 00 01, the index register is arbitrarily set to 1 when the first coordinate is received, but the index register in the index logic 43 is set to 1 when there is an instruction from the CPU. Initial settings may be made based on the value appearing in DataIn. (However, the present invention operates properly regardless of the initial value of the index register when the loading sequence begins.) Also, in this example, XRa
5Off and YRasOff are assumed to store the value 0 so as not to obscure the operation of this circuit.

The loading control state machine 33 is connected to the comparison control state machine 4.
9, a pipeline scheme is provided to control the selection of registers and corresponding multiplexers necessary for the proper operation of comparison logic/results storage 47 and condition generation logic 51, in addition to loading the various registers described above. Control.

Additionally, if it is desired not to take advantage of the raster offset capabilities of the present invention, the comparison logic/result storage 47
Before performing the comparison performed by , it is necessary to force the addition of O to the input data for data storage in the X and Y coordinate registers.

In this regard, a loading control state machine 33;
MUX En generated by comparison control state machine 49
enable control signal and Register Enable
The control signal can also be confirmed from the timing sequence table shown in FIG. 9 and the following list showing the order of processing to be executed by the coordinate staging unit 15 for each input Y coordinate.

1. Receive the Y coordinate of DataIn2. The lower 16 bits of the received Y coordinate are a) YR
aaOff (lower 16 bits) or b) (jnd
The lower 16 of YOL to Y3L as instructed by ex-1)
or c) add 3 to Q, the upper 16 bits of the received Y coordinate, a) YR
aaOff (sign extension upper 16 bits) or b) YO indicated by (1ndex-1)
H-Y3H upper 16 bits or c) Add to 0 and compare the result of step 2 with other Y coordinates4.
tMin.

Compare with YClipMax and YTeatMax and check the top 18 pits of the results of steps 2 and 3 for all 1 and all 0 states In step 2 and step 3 above, option a)
, b) or (2) are selected as follows.

Non-relative write to indexed register (PNT
, LINE , TRI , QUAD , RECT), option a) is selected. Relative writes to the register indicated by the index (RELPNT, ILLINE, REL)
TRI, RI8LQUAD, RELRECT), option b) is selected. For all other writes select option c). Loading of the X coordinate follows the same flow.

Keeping in mind the constraints and definitions explained above, and also the indicator logic 43.
The index register value in is "01" and the registers (XO, YO) ~ as described above with reference to FIG.
Assuming that (X3.Y3) are all 0, as in the first example, define a line whose terminal point's X and Y coordinates are (3, 6) (7, 9). To load a register, events occur according to the sequence shown below.

At clock cycle 0, the P n t Y (6) write command places the value 6 on DataIn so that the register address input to the loading control state machine 33 contains a value indicating that the input data is one Y point. Make it.

In clock cycle 1 (see FIG. 3), multiplexer 36 receives an instruction to select the lower 16 bits of DataIn, and multiplexer 35 (i.e., multiplexers 35& and 35b) and 40 and logic gate 4
2 receives an instruction to pass the lower 16 bits of YRasOff. Thus, during clock cycle 1, adder 31 adds the output of multiplexer 36 and the output of logic gate 42 and produces the result at the output terminal.

At the end of clock cycle 1, registers YOL~Y3
L is inerpulled and the value from adder 31, i.e.
6 is loaded, representing the lower bit of the value 6 that was in DataIn. In clock cycle 2, multiplexer 36 receives an instruction to select the upper 16 bits of DataIn, and multiplexers 35 and 40 and logic gate 42 receive an instruction to pass the sign-extended upper 16 bits of YRasOff. . Thus, during clock cycle 2, adder 31 adds the output of multiplexer 36 and the output of logic gate 42 and produces the result at the output terminal. At the end of clock cycle 2,
Registers YOH-Y3H are enabled and adder 31
The value from the output terminal of is loaded.

In cycle 3, the pntx(3) write command is Data.
In is loaded with the value 3 so that the register address input to the loading control state machine 33 contains a value indicating that the input data is at point X. Also, clock cycle 3
Then, the multiplexer 36 receives an instruction to select the lower 16 bits of DataIn, and selects the lower 16 bits of the multiplexer 35.
and 40, and logic gate 42 receives an instruction to pass the lower 16 bits of XRa5Off. During clock cycle 3, adder 31 adds the output of multiplexer 36 and the output of logic gate 42 and produces the result at its output terminal. At the end of clock cycle 3, registers X0L-X3L are enabled and loaded with the value from adder 31, ie, 3, representing the lower bit of the value 3 that was in DataInK. clock cycle 4
Then, multiplexer 36 receives an instruction to select the upper 16 bits of DataIn, and multiplexers 35 and 40 and logic gate 42 receive an instruction to pass the sign-extended upper 16 bits of XRa5Off. In the clock cycler 4, the adder 31 adds the output of the multiplexer 36 and the output of the logic gate 42 and produces the result from the output terminal. During clock cycle 4, registers XOH-X3H are enabled and adder 3
The value from output terminal 1 is loaded and the index register is incremented. At clock cycle 5, the LineY(9) write command places the value 9 on pataIn, causing the register address input to loading control state machine 33 to contain a value indicating that the input data is a Y line. In clock cycle 5, multiplexer 36
Upon receiving an instruction to select the lower 16 bits of YRa, multiplexers 35 and 40 and logic gate 42 select the lower 16 bits of YRa.
Receives an instruction to pass the lower 16 bits of aOff. During clock cycle 5, adder 31 adds the output of multiplexer 36 and the output of logic gate 42;
The result is generated from the output terminal. clock cycle 5
At the end of , registers Y2L, Y3L and YOL are enabled and receive the value from adder 31, i.e. Dat
9 is loaded, representing the lower bit of the value 9 that was in aIn. In clock cycle 6, multiplexer 36 receives an instruction to select the upper 16 bits of DataIn, and multiplexers 35 and 40 and logic gate 42
receives an instruction to pass the sign-extended upper 16 bits of YRasOff. At clock cycle 6, adder 31 adds the output of multiplexer 36 and the output of logic gate 42 and produces the result at its output terminal. During clock cycle 6, registers Y2HY3H and Y
OH is enabled and loaded with the value from the output terminal of adder 31. Clock cycle? Well then, LinaX
(7) The write command puts the value 7 on DataIn, and the register address input to the loading control state machine 33 is
The input data is made to include a line indicating that it is an X-ray. Similarly, eventually registers X2L, X3L and XOL are enabled and loaded with the value 7, after which the index register is incremented from 2 to 3 as shown above. Loading of the X/Y coordinate registers for other objects also follows the same pipeline scheme as described above. Examples of triangles and rectangles are given in the second and third examples above. Quadrilateral objects are loaded in the same way.

The raster offset register 41 and the clip coordinate register 39 are the X/Y coordinate register 37 as explained above.
is loaded in a similar manner to the loading of logic gate 42
is commanded to be O on every addition cycle (ie, absolute loading).

The present invention further implements relative addressing through the use of index registers included in index logic 43, forming an efficient mechanism for displaying replicas of objects. ``Relative addressing is best explained using the following example. The three vertices of the triangle are (X(
ir yo ) + (XI +Y+) and (X2.
Y2). To replicate this object 50 times at different locations on the display device,
It would be necessary to store 150 pairs of X, Y coordinates.

When using relative addressing, place one vertex at the origin (
xol y, ), and the second and third vertices are defined as offsets from the previous vertex, i.e., Δxol
, ΔYOI and ΔX23. It is defined as ΔY23.

To duplicate the object 50 times, offset those two pairs and a new X for each duplicate. , Yo (i.e., 50
It is only necessary to store the object origin plus two pairs of offsets).

According to the invention, this begins with the X/Y coordinate register 3
7 into one of the pairs of registers in index-directed loading format (i.e., PntY.

This can be done by storing the origin coordinates versus vertices using PntX). Subsequently, two offset vertices are stored for the vertex indicated by the current value of the index register. This is done by selecting the vertex pointed to by (index-L) to be added to DataIn prior to register loading. The vertex represented by (1ndex-1) is the write type (PNT).

LINg, etc.), it is guaranteed that it was loaded when the index instruction was written earlier, so the vertex is
This is the vertex from which the relative offset is applied.

Comparison Logic/Result Storage Device 47 Next, the comparison logic/result storage device 41 will be explained with reference to FIGS. 7 and 8. Comparison logic/result storage 41 includes multiplexers 101 , 103 , 105 .

101 and 109 (see FIG. 7), and comparators 121 to 109 (see FIG. 7).
124, multiplexers 131 to 146 and register R
1 to R44 (see FIG. 8).

Registers R1 to R44 are used for comparator 1 as shown in Table 2.
The results of operations 21 to 124 are stored.

2nd I i6 XO:X Cl f pMl n XO:XTeatMln XO:X C1i pMax XO:X T e s tMax tMax :XC1lpXC1 1p:XTeatMin X2:XC1ipXC1 1p:XTestMax X3:XC1ipXC1 1p :XTe s tMt n X3: Xl:X2 xl:X3 X2 :X3 Table YO :Y C1i pMl n YO: YTestMln YO: YClipMax YO: YTestMax Yl: YClipMin Yl: YTestMin Yl: YCllpMax Yl: YTegtMax Y2: YClipMln Y2: YTestMln Y2: YClipMax Y9: YTestMax Y3: YCllpMin Y3: YTa stMl n Y3: YCllpMax Y3:YTastMax YO:YI YO:Y2 YO:Y3 Yl:Y2 Yl :Y3 Y2 :Y3 In Table 2, XC11p stores the 1-bit result.
Min/Max, Y C1i pMl n/Max
, XTe s tMf n/Max and YTe a
With the exception of the comparison value involving tMin/Max, the indicated register stores the 2-bit result of the intercomparison of the two indicated values. If the value to the left of the colon is greater than the value to the right of the colon, the binary value stored in the corresponding register is "10". Also, if the value to the left of the colon is smaller than the value to the right of the colon, the binary value stored in the corresponding register is "01". If the two values are equal, the binary value stored in the corresponding register is '00'
It is. XC1XC11p, YClipMin, X
For TestMin and Y Ta s tMl n,
If the compared coordinate value is smaller, "1-1" is stored, but otherwise "0" is stored. xcitpMax, YCllpMax, XTe
In the case of atMax and YTsstMax, if the compared value is larger, 1'' is stored, otherwise 1-o'' is stored.

Multiplexers 101, 103, 105, 107
The inputs to 109 and 109 are the X/Y coordinate register 37, that is, XOL, YOL~
, YC order pMin and XC order pMax, YCNpMa
x and the test window control logic 45, i.e., XTe
stMin.

YTastMin, XTestMax and YTe
It is obtained from s tMax . Naturally, at one point in time? /L/ Chipleku? 101, 1
The inputs for 03, 105, 107 and 109 are:
MUX Ena generated by comparison control state machine 49
Based on the ble signal, it becomes either the X value or the Y value as described above.

Comparator 121 compares the output of multiplexer 101 and the output of multiplexer 109. Similarly, comparator 1
22 to 124 are the output of the multiplexer 103, the output of the multiplexer 105, and the multiplexer 10, respectively.
7 and the output of multiplexer 109 are compared. The outputs of comparators 121-124 are input to multiplexers 131-146 which route the appropriate data to registers R1-R44 to be loaded as described below.

The output of the comparator 121 is as shown in FIG. 8 and Table 3 below.
, R5, R9, R13, R17, R18 and R19, and for the Y value R23, R24°R25, R2
6, R27, R31, R35, R39, R40 and R4
Multiplexer 131 used to load 1
~135, 139 and 143. In Table 3, A, B, C and D are comparators 121, 122
, 123 and 124, respectively.

The output of the comparator 122 is as shown in FIG. 8 and Table 3.
Regarding the X value, registers R2, R5, R6゜R7, R8
, R10, R14, R17, R20 and R21, and for the Y value registers R24, R27, R28, R
29, R30, R32, R36, R39, R42 and R
Multiplexer 13 used to load 43
2, 135, 136, 137, 138, 14
0 and 144.

The output of the comparator 123 is as shown in FIG. 8 and Table 3.
Regarding the X value, registers R3, R7, R9゜R10, R
Load 12, R15, R18, R20 and R22,
Regarding the Y value, registers R25, R29°R31, R3
2. Multiplexer 133, 13 used to load R34, R37, R40, R42 and R44
7, 139, 140, 142 and 145.

The output of the comparator 124 is as shown in FIG. 8 and Table 3.
Regarding the X value, registers R4, R8, R12゜R13,
Load R14, R15, R16, R19, R21 and R22, and change the Y value to R26°R30,
R34, R35, R36, R37, R38, R41, R
Multiplexers 134, 138, 142, 143 used to load R43 and R44.

144, 145 and 146.

The comparisons performed and stored are carried out by the coordinate ordering section 17 and the functional addressing block 19, which assists in the operation (.
DRAW or BLIT, also known as quadrilateral drawing
) is required to perform the correct clipping as well as perform the correct clipping.

Comparison Control State Machine 49 Comparison control state machine 49 includes comparison logic/result storage 47
Logic that enables various comparators, multiplexers, and registers in the The truth table for the absolute loading of the coordinate and clip registers by the comparison control state machine 49 is shown in Table 3 for clock O and clock 1. In the table, the comparators 121 to 124 are indicated as A, B, C, and D, respectively. Table 3 shows the inputs XOL~X3L, XC1ipMin,
XCI ipMax, XTeatMln and X
To a ty (each comparator 12 for each of ax
It represents outputs from 1 to 124. In this connection, according to FIG. 8, multiplexers 101 , 103 .

It can be seen that the outputs of 105 and 107 are input to one side of comparators 121-124, and the output of multiplexer 109 is input to the other side. For consistency, instead of doing the opposite order, e.g. comparing XIL and XOL, we compare XoL with Xll, XIL with
It is necessary to memorize the comparison with L, the comparison between X2L and X3L, etc. Therefore, when the column labeled Reverse is "yes", the outputs of comparators 121-124 are reversed. This is multiplexer 131-146
is processed by the input on the right side of . Comparators 121-124
The outputs of are input directly to the left side of multiplexers 131-146. The right input terminal of the multiplexer receives the two-bit output from the designated comparator, in reverse bit order. That is, the column labeled Reverse indicates the M of multiplexers 131-146 for absolute coordinate loads.
It forms a truth table regarding the UX selection line.

Table 3 XOL:XIL XOL:X2L XOL:X3L XOL:XClipMXC 11p:XTestMin OXI Comparison XIL:X0L XIL:X2L XIL:X3L XIL:XC11pMXC 11p:XTestMin Xi L :X Cl i pMa xXIL:XTe
stMax Reverse cycle No No YES YES YES YES YES YES YES YES YES Write to comparator X3 wRr'rg'rox3 Comparison X3L:X0L X3L:XIL i pMa xX3L:XTe
stMax Reverse cycle No No No No No No YES YES YES YES YES YES YES X2L:X0L X2L:XIL.

X2L:X3L X2L :X Cl i pMl n X2L:XTestMin ClipMin:X2L XC11pMiRe:X3L XTestMin: XOL XTestMin:XIL XTestMtn:X2L X TeBtMin:X3L No No No No No No No No No No Comparator Comparison Reverse Cycle A
o No OCXC1XC11p:X2L No No 〇D XCIXCllp:X3L
No No OA XTaatMax:X
O3No No IB X Te a t
Max :XIL No ICXTest
Max:X2L No No ID XT
eatMax:X3L No No 1YOL~Y
3L, YCllpMin, YClipMax, Y
Regarding TesbMin and YTastMax, the third
Just repeat the results in the table. Figure 9 shows Dat
aIn signal and the raster offset register 41,
/Y coordinate register 37, clip coordinate register 39, and comparison logic/result storage 47.

The comparison control state machine utilizes both the index register value associated with the write cycle and Table 4 to support the index directed loading scheme as previously described. Since the register pointed to by the index register value is always written to, regardless of the type of write indicated by the index, the appropriate MUX enable for multiplexers 101, 103, 105, and 107 is determined by the compare control state machine. , is chosen assuming a single register write to that coordinate. For example, if a rectangle write to X with index 3 is received, the comparison logic will operate as if an explicit write to
L and '1 (XOL, XIL, X2L, XC1XC1
1p, XC1XC11p.

XTestMin, XTestMax).

The difference between an absolute loading of a register and an indexed (or relative indexed) load is that in the case of indexed loading,
Two or more coordinate storage registers at 47 may be enabled to receive the results of the comparison, and multiplexer 1
The multiplexer selection for 31-146 consists in being generated according to Table 4 rather than Table 3.

In the example of writing rectangle
3~rt16. R17 to R19 and R21 to R22 are written. The following pairs of registers individually store the same comparison results: (R17, R21).

(R18, R22), (R1, R13), (R2, R1
4).

(R3, R15) and (R4, R16).

Table 4 Comparator Comparison B XO:XI CXO:X2 D XO:X3 CXl:X2 D Xl:X3 D :Xl Xo:X2 XO:X3 Xi :X2 Xl:X3 X2 :X3 INE INE INE INE INE INE yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes X3 X2 :X3 xo:xi XO:X2 XO:X3 Xl:X2 XI :X3 X2:X3 XO:Xl Xo :X2 XO:X3 Xl:X2 INE INE INIIE INE INE INE INE INE INE Reverse no no no no no no yes yes yes yes yes yes yes yes yes yes yes yeB yes no no no no yes yes yes yes yes ye8 yes yes yes yes yes yes no menoh comparison xo:xi XO:X2 XO:X3 Xi :X2 X3 X2: XO:X3 Xl:X2 Xl:X3 no no no no yes yes yes yes no no no no no no no yes yes xo:xt XO:X2 XO:X3 XO:Xl Xl:X2 Xi :X3 UAD UAD UAD yes yes 0 yes yes 0 yes yes 0 no no 1 yes yes 1 yes yes 1 no no 2 no no 2 yes yes 2 XO:X3 Xl:X3 X2:X3 UAD UAD UAD no no no no no nQ No condition occurs Logic 51 The state generation logic 51 is the control signal HW/SW, Up/R-t.
Generate o-L and HID/'VIS. HW/SW
whether the operation is performed by the hardware of the invention;
This is a 2-bit signal indicating whether the program is executed by software or by software. Up/R-to-t is a two-bit signal that indicates whether the operation is to be performed in the top-to-bottom, bottom-to-top, right-to-left, or left-to-right direction. HID/V
IS is a two-bit signal that indicates whether the object to be rendered is hidden, ie, behind the active clip window, or visible. To generate these signals, the state generation logic 51 outputs the outputs of registers R1-R22 for the X coordinate and register R for the Y coordinate.
23 to R24 outputs, and the X/Y coordinate register 37
, the upper 18 bits are all 1 and all O
It receives as input four 4-bit value signs indicating that . With reference to FIGS. 10-14, which are truth tables for the logic executed by the state generation logic 51, how the state generation logic generates the above signals will now be described. The logic circuitry required to implement the truth tables of FIGS. 10-14 is well within the capabilities of those skilled in the relevant art.

FIG. 10 is a truth table using λ comparisons regarding the XO coordinates (XOL and X0H). X1-X3 and YO-
A truth table that uses the comparison results for Y3 substitutes those coordinates, and for the Y coordinate, XC1lpMln,
X C1ipMax, XTeatMin and XTe
YClipMln, YClipM instead of atMax
ax, YTestMin and YTestMax. The left side of the table is the input, and the right side is the output. In the table, the symbol "-" means no consideration, and 0 and (O represent that the pass bit values are all l and not all 1, respectively.
7), Z and 1z represent that the bus bit values are all 0 and not necessarily all 0 (from the X/Y coordinate register 37). r XQ 1
nside 214J converts the 32-bit XO coordinate to 15
Indicates that it can be displayed in bits, r
de clip J means that XO is the clip window
Represents being on or inside the boundary, [XO1n
side test J means that XO is the test window
Indicates being on or inside a boundary. Output r
O(XC1XC11p J, "XO(XTestM
ln J , r XO > XC1XC11p J and rx.

) XTestMax J is fed back and used as input. Inputs on the horizontal line are ANDed and outputs on the vertical columns are ORed to form the output.
Calculated. That is, taking the first two rows of FIG. 10 as an example, Xo(31) (i.e., its code pit) is 0.
and XO(:30:14) (i.e. upper bits 14 to 30) are all O, or XOI:
31) is 1 and X0C30:14) are all 1
If so, it is XOFiinside214. Similarly, regarding the last row of Figure 10, XO(XTas
tMin is O and I) (i.e., false) and X O>X
If Te g tMax is 0, then XO is inside the test window.

Figures 11a and 11s are truth tables that utilize comparisons between each of the four X vertices and each of the four Y vertices. As in Figure 1O, the values on the horizontal input lines are ANDed together and the result is a logical value of 1 (
true) or 0 (false) and outputs the indicated output (top
, bottom, ri-ght and 1ef) are formed by ORing their corresponding vertical columns. Output top, bottom shown as 0,1°2 or 3.

right and 1ef are interpreted as follows. value 0
, ], , 2 or 3 is XO-X3 or YO-Y
Which coordinates among 3 are the maximum (top) and minimum (botto)?
+f+)+right or left
). Symbols on the input side <, >, E,
L and G represent that the specified comparison result is less than, greater than, equal to, less than or equal to, and greater than or equal to, respectively.

Although the meanings of the outputs are defined by the table, what each of the indicated outputs represents will be explained in words below.

+11egal-4 means that when drawing a horizontal line through an object defined by 4 pairs of vertices, the line will intersect more than one edge. An object that forms a bow tie is an example of an object that makes illegal true.

horiz - means all four vertices have the same Y value.

ver,t means all four vertices have the same X value.

rect means that the object defined by four coordinates forms a rectangle.

1ine The object defined by the four coordinates is one
It means to form the lines of a book.

EQOI - means that vertex O is equal to vertex 1 (defines the same point).

EQ 12 - means vertex 1 is equal to vertex 2 (defines the same point).

EQ 23 - means vertex 2 is equal to vertex 3 (defines the same point).

EQ 30 - means that vertex 3 is equal to vertex O (defines the same point).

Figures 12a to 12d define truth tables that utilize comparisons of four X vertices and four Y vertices with clipping boundaries. Input top, bottom.

right and 1ef are taken from the truth tables in FIGS. 11a and 11s. output top visi
ble.

1) ottom visible, right v
When le is 1 (ie, true), the object defined by the four coordinate pairs is inside the clip window. 5urro
When und clip is 1, the object is outside the clip window, but surrounds the clip window. hidden can only be applied to quadrilaterals,
All four vertices are located on the right, left, and right side of the clip window.
Denotes being above or below. hidden 01(
BLIT SRC rectangle) and hidden 2
3 (pointing to the BLIT DEST rectangle) has a similar meaning with respect to BLIT.

FIG. 13 defines a truth table that utilizes comparisons of the four X vertices and four Y vertices with the boundaries of the test window. Output r top wlthin test J and r
bottom within test J, when true, indicates that the edge of the object is inside the top border and inside the bottom border of the test window, respectively.

FIG. 14 shows that the signal b
lit r-to-1, blit up, drawr
By generating -to -1 and draw up, we define a truth table indicating the direction in which the object should be drawn or BLIT should be performed. These signals constitute the signal Drawing Direction On shown in FIG. A more detailed description of this aspect of the invention can be found at
Seen in the co-pending application - Application No. - filed on

Based on the truth tables of FIGS. 10-14, state generation logic 51 generates signals HW, SW as shown in FIG.

HID and VIS are generated as follows.

For quadrilateral objects: HW = hidden or 5urround clip or (not hidden and not illegal and all vertices are 1nside 2" and (all vertices are 1nside test or (line and at least 1 two terminal points are 1nside test) or (XO~X3
is 1nside test and the top or bottom vertex is 1nside test) or rect).

5W = not HW and HID = hidden VIS = not hidden but BLIT: HW = hid 23 or (hid 01 and BLIT SRCCF (K = 1
0) or (not hidol and BLIT SRCCHK=10 and hid
23 and the source rectangle is 1nside 2” and the destination rectangle is 1nside 2”) or (BLIT 'SR
CCHK = 01 and not hid 23 and source rectangle is 1naide 2" and destination rectangle is 1nside 2") where BLIT SRC
CHK is a 2-bit direct from the CPU that is set to ``10'' if it is desired to consider the relationship between the source rectangle and the clip/know window. This is necessary because the various graphics software that may utilize the present invention are inconsistent in their handling of SRC rectangles and clipping boundaries. For this reason, the preferred embodiment provides the left side B as a software selectable option.
Equipped with LIT SRC rectangular clip inspection (B
LIT SRCCHK=01 disables SRC clip checking, BLIT SRCCHK=10
(enables SRC clip checking).

5W = HW not HID = hid 23 VIS = hid 23 The preferred embodiment of the present invention utilizes a two clock cycle coordinate load step followed by a two clock cycle comparison step. ing. These two stages can overlap as described above, but the total latency is 3 clock cycles, and every other clock cycle can receive a new input (or new result). ) (i.e., the throughput is 2
clock cycle). In the above example, it can also be seen that the coordinate staging section 15 receives data at the fastest possible rate given the preferred embodiment.

However, it should be obvious to those skilled in the art that the circuit described above will handle any slower (less frequent) data arrival rate. It is also obvious that the total waiting time and throughput can be reduced as a simple extension of the present invention if additional logic is acceptable.

[Brief explanation of the drawing]

FIG. 1 is an overview block diagram of a graphics subsystem for a workstation according to the present invention, FIG. 2 is a block diagram of a coordinate staging section of the graphics subsystem according to the present invention, and FIG. 3 is a block diagram of an adder 31 and a multiplexer. 35, FIG. 4 is a detailed block diagram of the X/Y coordinate register 37, FIG. 5 is a detailed block diagram of the clip coordinate register 39, and FIG. 6 is a raster offset register. 7 is a detailed block diagram of the test window control logic 45. FIG. 8 is a detailed block diagram of the comparison logic/result storage 47. FIG. 9 is a detailed block diagram of the test window control logic 45. A table showing the relative timing of the comparisons performed by the control state machine 35 and the comparison logic/result storage 47, FIG. Figure 11 is a truth table that uses comparisons between each of the four X coordinates and each of the four Y coordinates, and Figures 12a to 12d are the truth tables for the four
Figure 13 is a truth table that uses comparisons of vertices and clipping boundaries; Figure 13 is a truth table that uses comparisons of four X vertices and four Y vertices with test window boundaries; A truth table indicating the direction in which an object should be drawn or a blit should be performed. 11...Bus interface logic, 13...Data path/memory interface, 15...Coordinate staging section, 17...Coordinate ordering section, 19...
...Functional addressing block, 21...Mask generation block, 23...Linear address generator, 31
... Adder, 33 ... Loading control state machine, 35 Multiplexer, 37 ... X/Y coordinate register, 39 ... Clip coordinate register, 41.
- Raster offset register, 43e number index logic, 45... test window control logic, 47...
comparison logic/result storage, 49...comparison control state machine, 51...state generation logic; Patent Applicant: Sun Microsystems Incorporated Agent, Masaki Yamakawa, C.J./wa 5 FIG, 1 FIG, 3! 1 Q)

Claims (2)

[Claims] (1) An image processing device that loads the coordinates of the object, either a quadrilateral to be rendered or a block image to be moved, into a plurality of registers to be displayed by the graphics subsystem. , comprising loading means for loading the coordinates of the object into a plurality of object coordinate registers, and the object to be displayed has the minimum number of coordinates necessary to uniquely define the object. equipment defined by (2) an object, either a quadrilateral to be rendered or a block image to be moved, and a device for loading into a plurality of registers the object coordinates of this object to be displayed by the graphics subsystem; Then, a predetermined a test window with an offset and a Y offset, the object coordinates and the clip coordinates, the offset being used in calculations to perform object clipping prior to display. In the image processing device, i) loading the object coordinates into a plurality of object coordinate registers, ii) loading the clip coordinates into a plurality of clip coordinate registers, and iii) loading the predetermined offset into a plurality of offset registers. A device that is equipped with a loading means for loading, and in which the object to be displayed is defined by the minimum number of coordinates necessary to uniquely define the object.