JPH0222905A - Protecting circuit for fet amplifier power source - Google Patents

Abstract

PURPOSE:To prevent breakdown of an FET by preventing the output of a positive voltage for the drain voltage at the time of not outputting a normal negative voltage for the gate voltage from a power source. CONSTITUTION:A positive voltage +VD for the drain voltage and a negative voltage -VG for the gate voltage which are outputted from the power source are compared with each other by a comparator 3 after being converted to logical levels by level converters 1 and 2 and calculated. When it is detected that the normal negative voltage -VG is not outputted but the positive voltage +VD is outputted, the positive voltage +VD for the drain voltage from a power source 100 is forcibly turned off by a switch means 4. Consequently, the positive voltage +VD for the drain voltage is not outputted before the output of the normal negative voltage -VG for the gate voltage. Thus, the FET of a load is protected.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a protection circuit for a sequence power supply for an FET amplifier that applies a negative voltage -V to the gate G of an FET whose source S is grounded and a positive voltage +vD to the drain D. Positive drain voltage +V before gate voltage -VIS
. In order to prevent the FET from being damaged by causing excessive drain current to flow through the FET, the positive voltage +VD for the drain voltage of the power supply output and the negative voltage -V for the gate voltage are set to the respective levels. After converting to logic level with a converter, comparison calculation is performed with a comparator, and the specified negative voltage -
When it is detected that the positive voltage +vD is output without vG being output, the positive voltage +VD for the drain voltage from the power supply is forcibly cut off by the switch means.

[Industrial application field]

The present invention relates to a protection circuit for a power supply for an FET amplifier using an FET (field effect transistor) as an amplification element used in a transmitting section of a wireless device.

If a positive drain voltage is not applied to the FET amplifier after the negative gate voltage exceeds a certain value, an overcurrent will flow through the drain and the FET will be damaged.

For this reason, a sequence power supply in which the order of voltages applied to the gate and drain of the FET is determined is used in an FET amplifier whose source is grounded.

[Conventional technology]

A conventional example of a sequence power supply for an FET amplifier is shown in FIG. The sequence power supply 100 is inside the dashed line in the figure.
Input a positive voltage +V and a negative voltage -vl, perform voltage control as described later, output a specified positive voltage +VD and negative voltage -v6, and apply a negative voltage -■ to the gate G of the FET whose source S is grounded. is supplied through choke L1, positive voltage +VD is supplied to drain D through choke L2, and high frequency input R
FET that amplifies Fin and outputs high frequency output RFout
The sequence power supply 100 that determines the DC bias of the amplifier 200 includes transistors TR1 and TR2.
゜A positive voltage series control power supply unit 10A consisting of TR5 and resistors R1 and R2, a transistor TR3 and resistor R3,
It is composed of a negative voltage series control type power supply section 20^ formed by R4, and a drain voltage control section 30^ formed of a Zener diode D1, resistors R5 and R6, and transistors TR4 and TR5. Normally, +12V is applied to the positive input +VI, and -12V is applied to the negative input -V. Then, the negative output -VG of the negative input series control power supply section 20A is -VG = -VI X R4/(R3+R4)
+V mt (TR3) is output, and it is approximately -5V during normal operation.

The positive output +VD of the positive voltage series control power supply section 10A is +
VD = (+VI - Vct(TR5)) x R
2/(R1+R2) +v ct(TR5)-V C1
(TR2)-V It (TRI) is output, which is approximately +IOV during normal operation.

When negative voltage -VG is not output, V
mt (TR4) =+VI -Is (TR4) X
Since R5-+0.7V is applied, TR4 is ON,
TR5 is turned OFF.

At this time, v3 of TR2 is V 1 (TR2) = +VI - L (TR2) x
R1=+V I, and V st (TR2) =
Turns off because it becomes OV.

When the collector current of TR2 does not flow, the base current of TRI also does not flow, so TRI is also turned off, and the positive output +v8 becomes Ov.

When the value of negative output -vG exceeds the breakdown voltage VDI of Zener diode D1, in TR4, V mt (TR4) = -VIV ol, and TR
4 is 0FFL, and TR5 is turned on, so the positive output +v, which is the specified approximately +IOV, is output.

[Problem to be solved by the invention]

Sequence power supply 1 in Figure 5 of the conventional power supply for FET amplifiers
00 is the Zener diode D1.00 of the drain voltage control section 30A. When the transistor TR4 fails in short circuit mode,
At the time of failure in the open mode of transistor TR3, the drain voltage of the positive output +v is higher than the gate voltage of the negative output -Va.
There is a problem that the signal is output first and applied to the FET amplifier 200, damaging the FET. The present invention aims to solve this problem.

[Means to solve the problem]

This problem is solved by the sequence power supply 100 as shown in FIG.
The positive voltage +VD17 for the drain voltage of the output and the negative voltage -VG4n for the gate voltage are respectively connected to the positive voltage level converter 1.
The negative voltage is input to the level converter 2 and converted to a logic level, and then the comparator 3 performs a comparison operation to obtain the negative voltage -VGifi.
When the comparator 3 detects that the positive voltage +VDin is input first without inputting the positive voltage +VDi, the positive voltage +VDi for the drain voltage from the power supply 100 is output +V. This problem is solved by the present invention, which is provided with a protection circuit 10 consisting of a switch means 4 that forcibly turns off the □.

In the principle diagram of FIG. 1 showing the configuration of the protection circuit for the FET amplifier power supply of the present invention, 100 controls the input positive voltage +v1 and negative voltage -vl, and controls the specified positive voltage +V and negative voltage -■ , a negative voltage -vG is supplied to the gate G of the FET whose source S is grounded, and a positive voltage +v0 is supplied to the drain D to determine the DC bias.

1 is the specified positive voltage + for the drain voltage from the power supply 100.
This is a positive voltage level conversion circuit that outputs logic level H when VD is input.

2 is a specified negative voltage V for gate voltage from the power supply 100,
This is a negative voltage level conversion circuit that outputs a logic level H when it is input.

3 is the logic level H of the output of the positive voltage level conversion circuit 1
/L and the logic level L of the output of the negative voltage level conversion circuit 2
/H, which outputs a logic level H when the output logic level of the negative voltage level conversion circuit 2 is H and the output logic level of the positive voltage level conversion circuit 1 is H. do.

Reference numeral 4 denotes a switch means which operates according to the logic level H of the output of the comparator 3 and forcibly cuts off the positive voltage +vD for the drain voltage inputted from the power supply 100 so as not to output it.

[Effect]

The positive voltage level conversion circuit 1 outputs a logic level H to the comparator 3 when a specified positive voltage +VD for drain voltage is input from the power supply 100. The negative voltage level conversion circuit 2 outputs a logic level L to the comparator 3 when a specified negative voltage -vG for gate voltage is input from the power supply 100.

The comparator 3 normally compares the logic level H of the output of the positive voltage level conversion circuit 1 and the logic level L of the output of the negative voltage level conversion circuit 2, outputs an output level L, and operates the switch means 5. Although not operated, negative voltage level conversion circuit 2
When the logic level of the output of the positive voltage level conversion circuit 1 is H, the logic level H is outputted to drive the switch means 5.

The switching means 4 performs a switching operation according to the logic level H of the output of the comparator 3, and forcibly cuts off the positive voltage +vD for the drain voltage inputted from the power supply 100 and does not output it. The problem is solved because the positive voltage +vD for the drain voltage is no longer outputted before the voltage -V is outputted.

〔Example〕

FIG. 2 shows the configuration of the protection circuit for the FET amplifier power supply according to the first embodiment of the present invention, FIG. 3 is a time chart for explaining its operation, and FIG. FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention.

In FIG. 2, the positive voltage level conversion circuit 1 is connected to a resistor R
1 and a resistor R2, from the power supply 100 to a specified positive voltage for the drain voltage + voltage of vDIN + IO
When V is input, the voltage at point a between the ground of resistor R2 of the voltage dividing circuit is converted to a logic level H and output to the comparator 3. The negative voltage level conversion circuit 2 includes a comparator COMP
1. It is composed of resistors R3, R4, and diode D1, and receives a specified negative voltage -v for the gate voltage from the power supply 100.
When the INN voltage of -5V is input to the input terminal of the comparator COMP1, the voltage divider circuit of resistors R3 and R4 divides the power supply -
A voltage -3V obtained by dividing 5V is input as an offset voltage (discrimination voltage) to one input terminal, the level is discriminated, the logic level is converted to L, and the voltage is output to the comparator 3. The diode D1 is
COM when power -5v is turned on before power +5v
This prevents the output of P1 from becoming negative and damaging the comparator 3.

Comparator 3 is composed of NAND (Nando game), and the third
Logic level H/L of the output of the positive voltage level conversion circuit 1 at the time of positive input ■+vDIN and negative input ■
-vGIN, the logic level L/H of the output of the level conversion circuit 2 of the negative voltage is input and a comparison operation is performed.

In other words, during normal operation, when inputting the logic level H of the conversion output when positive input +v, IN is the specified value +IOV, and the logic level H of the conversion output when IN is the specified value +IOV, and the negative input -vt, the logic level L of the conversion output when IN is the specified value -5V, the positive The output point a of the voltage level conversion circuit 1 is the third
The output of the negative voltage level conversion circuit 2 at point b becomes "L' at point 05 in the figure, and at that time, the output of the comparator becomes level L as shown in the figure ■. Therefore, without driving the switch means 4, the specified input from the power supply 100 is +V, and the +IOV of IN is the specified output.
Output as +IOV of +v0°u7.

Then, the Zener diode D of the drain voltage control section 30
1 is a short-circuit failure, the output point a of the positive voltage level conversion circuit 1 becomes "H" at point 08 in the time chart in Figure 3, but the output point b of the negative voltage level conversion circuit 2 becomes "H". , Figure 0
As shown in point 5, ■ -VOIN becomes "H'" during the transient period when it reaches the specified value -5v and when it deviates from the specified value -5v, and becomes "L" at other times. During a transient period, the output of the comparator becomes level H as shown in Figure 2, driving the switch means 4 ON, and +IOV of +VD IN, which is the specified input from the power supply 100, is cut off only during the transient period, but during steady state outputs the specified input ■+vl, +IOV of IN as the specified output ■+v0°.÷IOV.

When the transistor TR3 of the negative voltage series control power supply section 20 has an open circuit failure, the positive voltage +V from the power supply 100 is
The voltage at ll IN + IOV is input to the level converter 1, and the converted output at point 08 becomes the normal logic level "H", but the negative voltage -VG IN voltage -5v is disconnected due to an open failure of transistor TR3. Then, the 05 point of the conversion output becomes the abnormal level H of the logic level 1H'', and the comparator 3
The output of the NAND gate NAND outputs a logic level "H#" and sends the logic level H to the switch means 5.

The switch means 4 is composed of a drive transistor TRI and a relay RL1 having an open contact rL1 that is opened during operation, and is switched by the logic level H of the output of the gate NAND of the comparator 3 to open the contact rL1. Open,
■Forcibly cut off the positive input + VD IN specified value + tOV input from the power supply 100 and do not output it.

Therefore, the protection circuit for the FET amplifier power supply according to the first embodiment of the present invention shown in FIG.
Before the specified negative voltage -vG -5V for the gate voltage of FET 00 is not output, the positive voltage +IOV of +vD for the drain voltage is first output and applied to the FET, causing an excessive drain current to flow. There is no problem as it will not be destroyed.

In the protection circuit for the FET amplifier power supply according to the second embodiment of the present invention shown in FIG. A closed contact rL11 connected between the emitter of the transistor TR2 and the ground operates at a drive voltage higher than the positive output voltage +V, the specified value of out +IOV, and operates at the specified value +10VT degrees, and a slow-acting contact rL11 that operates at a voltage of +12V. Open contact rL 12 series circuit is connected to the input control transistor T of the series control type power supply 10, which is the input terminal of the positive input voltage +V.
Provided between the emitter and base of R2 and set the specified voltage +IO
It consists of a positive voltage electromagnetic relay RL1 that short-circuits the emitter and base when V is applied. The negative voltage level conversion circuit 2 includes a negative voltage electromagnetic relay RL having a closing contact point 2 that operates at a specified voltage of -5V of the negative output voltage -VG.
Consisting of 2. The comparator 3 is configured to perform a comparison operation by setting the sensing voltages of the positive voltage electromagnetic relay RL1 to +10V and +12V, and setting the sensing voltage of the negative voltage electromagnetic relay RL2 to -5V. and power supply 1
00 to the input positive voltage for the drain voltage + specified voltage of vDIN + lOv, if applied when the voltage of negative voltage electromagnetic relay RL 2 is -5V or less, for example -V, is -4V, the positive voltage electromagnetic relay Closed contact of RL 1 rL 11
is closed, slow opening contact rL 1 operated at voltage +12V
2 is still in the closed state, so the positive voltage series controlled power supply 1
The emitter and base of the zero input control transistor TR2 are short-circuited. Therefore, the transistor TR2 is turned off, and the base current of the output control transistor TRI stops flowing, so that the positive output voltage +V of the emitter output,
The load FET is protected from damage due to excessive drain current.

〔Effect of the invention〕

As explained above, if the protection circuit of the present invention is used, before the specified negative voltage for the gate voltage of the FET of the FET amplifier is not output from the sequence power supply, the positive voltage for the drain voltage will be output first and tN F This eliminates the possibility of an excessive drain current being applied to ET and causing destruction, thereby providing the effect of protecting the expensive FET of the load.

4 is a switch means; 100 is the power supply, 200 is a FET amplifier.

[Brief explanation of the drawing]

FIG. 1 is a principle diagram showing the configuration of the protection circuit for the FET amplifier power supply according to the present invention. FIG. 2 is a block diagram showing the configuration of the protection circuit for the FET amplifier power supply according to the first embodiment of the present invention. The figure is a time chart for explaining the operation of the first embodiment of the present invention, FIG. 4 is a block diagram showing the configuration of the protection circuit for the FET amplifier power supply according to the second embodiment of the present invention, and FIG. is the conventional FE
It is a block diagram of the protection circuit of the power supply for T amplifiers. In the figure, 1 is a positive voltage level converter, 2 is a negative voltage level converter, 3 is a comparator,

Claims (1)

[Claims] A positive voltage (+V_I) and a negative voltage (-V_I) are input and controlled, and a specified negative voltage (-V_G) is outputted as a source (S).
is supplied to the gate (G) of the grounded FET, outputs a specified positive voltage (+V_D) and supplies it to the drain (D), amplifies the high frequency input (RFin) and outputs it (RFout).
The power supply (100) for the ET amplifier (200) is connected to the power supply (
A positive voltage level conversion circuit (1) outputs a logic level H when a specified positive voltage (+V_D_i_n) is input from the power supply (100);
), a negative voltage level conversion circuit (2) outputs a logic level L when the positive voltage level conversion circuit (1) is input, and a logic level (H
/L) and the logic level (L/H) from the negative voltage level conversion circuit (2) and calculate the negative voltage level conversion circuit (2).
) is H, and when the logic level from the positive voltage level conversion circuit (1) is H, a comparator (3) outputs a logic level H, and the logic of the output of the comparator (3). A switch means (4) is provided which operates at level H to forcibly cut off the positive voltage (+V_D) from the power source (100), and a prescribed negative voltage (-) for the gate voltage is supplied from the power source (100).
Positive voltage (+
FE characterized by not outputting V_D)
Protection circuit for power supply for T amplifier.