JPH0222927A - Noise reduction circuit for digital modulation - Google Patents

Abstract

PURPOSE:To suppress distortion or a noise due to the overload on the gradient of an analog waveform at minimum by varying step size i.e., sampling size. CONSTITUTION:A count-up clock or a count-down clock is selected by a signal selector 5 by sending signals in the case of attaching steep inclination and moderate inclination on an input analog signal, and it is sent to an up/down counter 6, and the parallel output of the up/down counter 6 is sent to a waveform converter 7. And the waveform converted output of the step size is converted from the waveform converter 7 by a sign from a sign comparator 3, then, it is sent as digital modulated output. Thus, since the step size of a digital waveform is varied according to the change of the inclination of the input analog waveform, it is possible to reduce the distortion or the noise generated by the overload on the gradient.

Description

[Detailed Description of the Invention] [Summary] The purpose of the present invention is to perform digitization with less error and distortion without increasing the sampling frequency (speed) regarding a noise reduction circuit in digital modulation that converts analog signals such as audio into digital signals. A slope detector that calculates the slope of the input analog waveform, a positive/negative comparator that calculates whether the slope is positive or negative, and a sampling clock from the clock generator are selected by the output from the slope detector. The waveform converter comprises a signal selector, an up-down counter that counts input from the signal selector and outputs a parallel value, and a waveform converter that outputs a step size according to the parallel output of the up-down counter. If the output of the positive/negative comparator is "0", a negative value is outputted, and if the output of the positive/negative comparator is "1", a positive value is outputted, and the step size output is added to the original waveform.

[Industrial application field]

The present invention relates to a noise reduction circuit in digital modulation that converts an analog signal such as voice into a digital signal.

In recent years, with the digitization of various communication technologies, more advanced technology has been required to digitize analog signals such as voice. In digitizing analog signals, it is necessary to perform digitization with a small amount of error without increasing the sampling frequency (speed).

[Conventional technology]

Delta modulation is one of the conventional digitization techniques for converting analog signals such as voice into digital signals. FIG. 5 shows a block diagram of conventional delta modulation.

In the figure, 1 is a low frequency filter, 3 is a positive/negative comparator, and 7
' is a "Qll", "l" pulse generator, 8 is an analog input, and 15 is a digitized output.The low frequency filter 1 is a filter that removes the harmonic part of the analog input signal 8 and passes the low frequency part. Comparator 3 is a device that compares and calculates whether the slope of the analog waveform is up or down, and if it is up, it is +1.
If it is downstream, -1 is sent. The “0” and “1” pulse generator 7’ is based on the calculation result from the positive/negative comparator 3.
A pulse of θ'' or “1” is sent to an adder 17 to be added to the original signal and sent as a digital output 15.

In delta modulation, a single bit of sampling simply represents the differential sample polarity, thereby meaning an increase or decrease from the previous sample. Therefore, a digital signal is created in the feedback bus by increasing the quantization level when the input is positive and decreasing the quantization level when it is negative.

[Problem to be solved by the invention]

However, with this conventional method, the digital waveform may not be able to approach sudden changes in the input analog signal, and for this reason, when reproducing the digital waveform into an analog signal, it may not return to the original analog waveform. This sometimes caused waveform distortion and noise.

FIG. 6 shows an example of comparison between a conventional analog waveform and a digital waveform. In the figure, A shows the waveform of the input analog signal 8, and D shows the waveform of the digital output signal 15. The digital waveform varies depending on the sampling frequency, and each waveform is composed of a sampling rate t and a sampling size V. .

In this method, the optimal values for the analog signal are found at sampling rate t and sampling size V, but since the values of sampling rate 1 and sampling size V are constant and there is a limit on sampling rate t, As a result, the digital signal cannot hollow into the analog signal, causing waveform distortion and noise.

Since there is also a limit to the sampling frequency, ie, the sampling rate t, the present invention aims to minimize distortion and noise due to slope overload of the analog waveform by making the step size, ie, the sampling size V, variable. .

[Means to solve the problem]

In Fig. 1, which shows the principle configuration of the present invention, 1 is a low frequency filter, 2 is a slope detector, 3 is a positive/negative comparator, and 4 is a low frequency filter.
5 is a clock generator, 5 is a signal selector, 6 is an up/down counter, and 7 is a waveform converter.

The low frequency filter 1 is a filter that removes the harmonic part of the analog input waveform, the slope detector 2 is a detector that calculates the slope of the input analog waveform, and the positive/negative comparator 3 calculates whether the slope is positive or negative. The signal selector 5 converts the sampling clock from the clock generator 4 into the slope detector 2.
The up/down counter 6 is a counter that counts the input from the signal selector 5 and outputs a parallel value, and the waveform converter 7 selects according to the count parallel output of the up/down counter 6. This is a converter that outputs the step size.

The step size output from the waveform converter 7 is configured to be added to the waveform from the low frequency filter 1 by outputting a negative value if the output of the positive/negative comparator 3 is "0" or a positive value if the output is "1". do.

[Effect]

FIG. 2 shows an explanatory diagram of the principle of the present invention. FIG. 2 shows an exploded diagram of gradient overload of an analog signal.

In the figure, α represents an analog signal, Δt represents a sampling rate, and ΔV represents a rising potential per Δt. In this method, the value γ of [ΔV/Δt] is determined for each Δ, and when r<1, the step size is decreased, and when r>1, the step size is increased. Therefore, if the slope of the input analog waveform is steep, the step size will become larger, and if the slope is smooth, the step size will become smaller. You will be able to hollow against overload.

The above principle is applied to the inclination detector 2 to send signals for steep inclinations and gentle inclinations,
The signal selector 5 selects either a count-up clock or a count-down clock and sends it to the up-down counter 6. The parallel output of the up-down counter 6 is sent to the waveform converter 7, and the waveform converter 7 outputs a step-size waveform conversion. is converted into a positive/negative value from the positive/negative comparator 3 and sent to an adder, and the output waveform is corrected and sent as a digital modulation output.

〔Example〕

A block diagram of an embodiment of the invention is shown in FIG.

In the figure, 1 to 7 indicate the same numbers as in the principle block diagram of FIG. Output signals, 11 is a sampling clock signal from the clock generator 4, 12 is a countdown clock signal from the signal selector 5, 13 is a count up clock signal from the signal selector 5, and 14 is a parallel count output signal from the up/down counter 6. , 15 is a digital modulation output signal, 16 is a step size waveform conversion output signal from the waveform converter 7, and 17 is an adder for adding and outputting the waveform conversion output signal.

A waveform diagram and a time chart of the embodiment of the present invention are shown in FIG. 4, and the operation of this embodiment will be explained with reference to FIGS. 3 and 4.

The sampling clock signal 11 is, for example, a 20 KHz clock signal and uses constant clock pulses.

The positive/negative judgment output signal 10 sends a signal of "1 m" when the slope of the analog signal rises, and "0" when the slope falls.The slope judgment output signal 9 sends a signal of "0" when the slope is gentle.
When the slope becomes steep, 1'' is sent.The countdown clock signal 12 is a signal generated when the slope is gentle, and the countdown clock signal 13 is a signal generated when the slope becomes steep.Up-down The parallel output count signal 14 of the counter counts the sampling size as a digital value. For example, when counting down from "10'", it is between "10" and "0", and when counting up, it is between "10" and "0". The digital value is varied and counted between 20". The direction is determined by the positive/negative judgment output signal 10 on the absolute value of this count output, and the waveform conversion output signal 16 is sent out, which is added to the original waveform by the adder 17. Therefore, where the waveform of the input analog signal 8 is gradual, the number of wave height steps of the digital waveform 15 is small, and where the waveform of the input analog signal 8 is steep, the wave height of the digital waveform 15 is small. The number of steps increases, and a waveform of the digital output signal 15 that is hollow to the input analog signal 8 can be formed.

〔Effect of the invention〕

As explained above, according to the present invention, by changing the step size of the digital waveform in accordance with the change in the slope of the input analog waveform, distortion and noise caused by slope overload can be reduced. It greatly contributes to performance improvement.

[Brief explanation of the drawing]

Fig. 1 is a diagram of the principle configuration of the present invention, Fig. 2 is an explanatory diagram of the principle of the present invention, Fig. 3 is a block diagram of an embodiment of the invention, Fig. 4 is a waveform diagram and a time chart diagram of the embodiment, FIG. 5 shows a block diagram of the conventional example, and FIG. 6 shows a waveform diagram of the conventional example. In the figure, 1 is a low frequency filter, 2 is a tilt detector, and 3 is a low frequency filter.
is a positive/negative comparator, 4 is a clock generator, 5 is a signal selector, 6 is an up/down counter, 7 is a waveform converter, 8 is an input analog signal, 9 is a slope judgment output signal, 10 is a positive/negative judgment output signal, 11 is a 12 is a countdown clock signal, 13 is a count amplifier clock signal, 14 is a parallel count output signal, 15 is a digital modulation output signal, 16 is a step size waveform conversion output signal, and 17 is an adder. Peppa

Claims (1)

[Claims] In digital modulation that converts analog signals such as audio into digital signals, a slope detector (2) that calculates the slope of an input analog waveform.
and a positive/negative comparator (3) that calculates whether the gradient is positive or negative.
a signal selector (5) that selects a sampling clock from a clock generator based on the output from the slope detector; an up/down counter (6) that counts input from the signal selector and outputs a parallel value; A waveform converter (7) that outputs a step size according to the parallel output of the up-down counter is provided, and if the output of the positive/negative comparator (3) is "0", the step size output of the waveform converter (7) is negative. A noise reduction circuit for digital modulation, characterized in that if the value is "1", a positive value is output and added to the original waveform.