JPH02229454A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enhance a positional accuracy of a semiconductor chip in a transverse direction by a method wherein the semiconductor chip is fixed and bonded inside a recessed part in a substrate via a bonding material and a flattening layer is formed between the surface of the semiconductor substrate and the surface of the semiconductor chip. CONSTITUTION:A substrate, with a plane orientation of 100, 110 or the like, which can be etched anisotropically is used for an Si substrate 1. A tapered hole 2 used to fill a chip 3 in which a semiconductor element has been formed is formed in the Si substrate 1 by an anisotropic etching operation using an alkaline solution. The semiconductor chip 3 is fixed to the tapered hole 3 by using a bonding member 4. A groove 9 produced between the Si substrate 1 and the semiconductor chip 3 is filled with a flattening layer 5 which is used both for groove-filling use and for flattening use. An electrode 6, of an element, formed on the Si substrate 1 and an electrode 8 of the semiconductor chip 3 are connected electrically by using an electrode wiring part 7 formed on the flattening layer 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a technology for mounting semiconductor devices, and is for integrating semiconductor chips on a substrate.

[Conventional technology]

In the production of semiconductor devices, for example, compound semiconductors and St
Research is progressing on technology for forming elements formed on the same substrate, but there are many difficult problems that need to be solved. Furthermore, with regard to elements formed on St, it is extremely difficult to manufacture power elements in the same manufacturing process as ordinary elements (arithmetic elements, amplification elements, photoelectric exchange elements, etc.); There is no choice but to make it a hybrid by using the flip-chip method. If left as is, this would not only be disadvantageous to miniaturization of the element, but also limit the reliability.

Also, in recent years, in order to solve the above-mentioned problems, a through-hole is formed in the substrate in advance, and a semiconductor chip having a substantially rectangular prism shape is buried inside the hole using epoxy resin, and then contact wiring is formed. Hybrid integrated circuits have also been devised. [Problems to be Solved by the Invention] However, as a result of studies conducted by the present inventors, it has been found that even such technology has the following problems. In other words, ■After the semiconductor chip is aligned relative to the hole, it is filled with resin and cured by heat. Therefore, the position of the chip is likely to shift during resin filling and heat curing, and for this reason, the wiring mask is Many are required.

■Since the hole for loading the chip runs through the board, the strength of the board is low and durability is poor. ■Due to the through-holes, the amount of resin filling increases, making the wafer more likely to warp or crack, resulting in poor durability. Therefore, if the coefficient of thermal expansion of the resin is large,
(/M!) Wiring formed on resin is easily disconnected. ■Due to the through-holes, the board must be firmly fixed during manufacturing (to prevent misalignment and to prevent resin from seeping into the chip surface during resin filling), making it difficult to handle during the manufacturing process.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to solve the above-mentioned problems in a type of semiconductor device in which a semiconductor chip is directly bonded to a substrate.

[Means to solve the problem]

In order to achieve the above object, a semiconductor device of the present invention includes: a substrate in which a recessed portion having a bottom is formed; a semiconductor chip fixedly bonded within the recessed portion via a bonding material; a surface of the semiconductor substrate; It is characterized by comprising a flattening layer formed between the surfaces of the semiconductor chip to flatten the space between the two surfaces.

Further, the bottom of the recess is formed flat, and the shape and size of the flat bottom are substantially equal to the shape and size of the bottom of the semiconductor chip that is joined to the recess. It's okay.

[Effect]

According to the present invention, since the bottom exists in the recess for bonding and housing the semiconductor chip, the strength of the substrate after bonding the chip is high, and the bonding material, planarization layer, etc. existing between the substrate and the semiconductor chip are The filling volume can be made relatively small, which is advantageous in terms of reliability. Furthermore, work efficiency will also improve. Furthermore, by making the bottom of the recess flat and approximately equal in shape and size to the bottom of the semiconductor chip, when the semiconductor chip is housed in the recess, the bottom of the semiconductor chip corresponds to the bottom of the recess. This improves the accuracy of the chip position in the lateral direction. [Example] Hereinafter, an explanation will be given using an example shown in the drawings.

FIG. 1 is a sectional view showing the basic structure of a semiconductor device according to a first embodiment of the present invention.

In the figure, 1 is St in which semiconductor elements are built in advance.
The plane orientation (100
), (110), etc. are preferably used. This S
A tapered hole 2 (corresponding to a recess in the present invention) for embedding a chip 3 having a semiconductor element formed thereon is formed in the t-substrate l by anisotropic etching using an alkaline solution. The depth of the tapered hole 2 is approximately the thickness of the semiconductor chip 3,
The shape of the bottom of the hole is made to be the same as or slightly larger (about several μm) than the shape of the bottom 3a of the semiconductor chip 3. Semiconductor chip 3
is fixed to the tapered hole 2 by a joining member 4. A groove 9 formed between the Si substrate 1 and the semiconductor chip 3 is filled with a flattening layer 5 that serves both as groove filling and flattening. Also, S
Element electrodes 6 and semiconductor chip 3 formed on i-substrate 1
It is electrically connected to the electrode 8 using the electrode wiring 7 formed on the planarization layer 5, and the semiconductor chip 3 and the Si-based substrate 1 operate like an 1 chip.

Here, the semiconductor chip 3 may be any electronic device as long as it is an electronic device in which elements such as transistors, capacitors, and resistors are formed on a semiconductor substrate such as Si or GaAs, and the bonding member 4 is one that can bond the semiconductor chip 3 and the Si substrate l. Any material is fine, but it can be processed at a temperature below the heat-resistant temperature of the element considering the heating limit temperature (approximately 500'C) for the material of the wiring 7 (for example, aluminum), and the formation temperature of the passivation film to be formed afterwards (350-400'C). ℃ degree), etc., it is desirable to use a material with a high heat resistance temperature (for example, polyimide resin, AI.1-St eutectic). Further, the material of the wiring 7 may be any material as long as it can electrically connect the chip and the substrate (for example, Au, Mo, W, aluminum).

Further, the flattening layer 5 may be of any material as long as it can be easily filled into the groove and preferably has the same thermal properties as the adhesive layer (for example, polyimide resin).

An example of the outline of the manufacturing process for realizing the structure described above is shown in Figures 2(a) to 2.Although only the schematic structure is mechanically shown in Figure 2, detailed Specifically, it has a structure shown in the cross-sectional view of Fig. 3, and the manufacturing process will be explained assuming the structure shown in Fig. 3. First, the structure shown in Fig. 2(a) is A semiconductor element 10 (MOSFET in the figure) having an electrode 6 is formed on the St substrate 1 by a normal semiconductor process so that 11
is an insulating film formed on a Si substrate (e.g. Sing)
The device is protected on this film It! 12 (for example, S
The substrate is supplied in a state where t2Nm) is formed. After this, the protective film 12 is subjected to anisotropic etching (etching liquid: alkaline aqueous solution (KO\H, NaOH) when forming the tapered hole 2).
etc.)), it is patterned using a normal photo process. By controlling the etching time, the shape and size wa (see FIG. 3) of the flat bottom portion of the tapered hole 2 formed at this time can be set by several μm with respect to the shape and size W1 of the bottom surface of the semiconductor chip 3, which will be described later. It is possible to process the semiconductor chip 3 with the following accuracy, and the positional accuracy of the semiconductor chip 3 in the lateral direction (plane direction) can be kept within a range of about a few μm due to the flat part at the bottom of the tapered hole 2. Also, regarding the positional accuracy in the thickness direction of the board, what is the accuracy of the tapered hole 2? It is possible to process the thickness d0 with an accuracy of several μm or less by taking into account the thickness d1 of the semiconductor chip 3 and the thickness of the bonding member 4. Note that the taper angle θ of the tapered hole 2 is S of the (100) plane.
When using i-substrate 1, the angle is 54.7°, which is (110
) plane is used, the angle is 35.3°.

Next, as shown in FIG. 2(b), a semiconductor element formed on a substrate having a predetermined thickness d1 is sized to a predetermined size w.
1 to form a semiconductor chip 3. This semiconductor chip 3 is a semiconductor element such as a compound semiconductor (e.g. GaAs) element, a Si power element, a memory element, etc., and is a semiconductor element that is difficult to manufacture using the same manufacturing process as the element formed on the St substrate 1. The advantages of the present invention can be especially utilized if the The semiconductor chip has an electrode 8 and an insulating film (for example, SiO) 13.
, and a protective film 14 are formed.

Next, as shown in FIG. 2(C), the Si substrate 1 and the semiconductor chip 3 are bonded. This semiconductor chip 3 and Si substrate 1
In order to ensure that the semiconductor chip 3 and the surface of the Si substrate 1 are on the same plane when bonding the tapered hole 2 of It is desirable to do so. For this reason, the bonding member 4 is preferably made of a flexible material at this point (for example, polyimide resin, low melting point glass). After leveling, heat treatment is performed at 350°C to harden the joining member (polyimide). After fixing the semiconductor chip 3, in order to electrically connect the chip side electrode 8 and the substrate side electrode 6, thin film wiring is performed using a normal semiconductor process in order to further reduce the size and improve the reliability of the wiring. ．． For this purpose, it is necessary to fill and flatten the groove formed between the semiconductor chip 3 and the side surface of the tapered hole 2 to a state where wiring is possible. Therefore, as shown in FIG. 2(d), the grooves are filled with a groove-filling layer 5a and processing is performed.

The groove filling layer 5a is filled into the groove 9 by a disbending method or a subin coating method depending on the condition of the material.
Possible materials include fluid resins (for example, polyimide resins). If polyimide is used, it is cured by heat treatment at about 350 degrees after filling.

Thereafter, if necessary, etchback is performed by dry etching or the like as shown in FIG. 2(e), and then a flattening layer 5b is formed as shown in FIG. 2(f). In this case, the planarizing material may be polyimide resin, an insulating vapor deposited film, or the like.

After making it possible to wire in this way, as shown in Figure 2 (g
:), a contact hole is made by dry etching or the like in a portion of the flattening layer 5b on the electrode 6.8, an electrode film is formed of aluminum or the like, and then patterned to form a desired wiring 15. Finally, a protective film 16 (for example, a SizNa film) is formed over the entire device to complete the manufacturing process.

In addition, in the above-mentioned process, if it is not preferable for the trench filling layer 5a to cover the semiconductor element from the viewpoint of the element characteristics, the process from the process shown in FIG. 2(d) to FIG. 2(e)→(f)→( g)
However, if there is no problem, it is possible to proceed from the process shown in FIG. 2(d) to the process of FIG. Since the semiconductor chip 3 is bonded and fixed to the substrate, workability is good in the manufacturing process, and the strength of the substrate can be increased, resulting in excellent durability.

Also, compared to the conventional technology of forming through holes in the substrate, Si
Since the filling volume of the bonding member 4 and the planarization layer 5 existing between the substrate 1 and the semiconductor chip 3 is small, it is advantageous in terms of warpage and cranking of the substrate, and the wiring l5 on the planarization layer 5 is reduced. Confidence also increases.

Furthermore, since the shape and size of the flat part at the bottom of the tapered hole 2 are made approximately equal to the shape and size of the bottom surface of the semiconductor chip 3, the semiconductor chip 3 is housed in the tapered hole 2, and the semiconductor chip 3 and the Si substrate When smoothing the surface of semiconductor chip 1, the lateral position of semiconductor chip 3 is inevitably determined, and the positional accuracy can be improved.

Next, a second embodiment of the present invention is shown in the sectional view of FIG. As shown in this example, the number of semiconductor chips 3 is not limited to one, but may be multiple. Also, the SL substrate 1 does not need to have a semiconductor element built in, and the Si substrate 1 is simply It may also be used as a wiring board. Next, a third embodiment of the present invention is shown in the sectional view of FIG. The base material of semiconductor chip 3 has 31 base materials S with the same surface orientation as temporary 1.
In the case of a T wafer, it is possible to form the same tapered surface by anisotropic etching, and as shown in the figure, it is possible to create a structure without a trench filling layer, simplifying the process. In addition, by rubbing and adhering the semiconductor chip 3 to the tapered portion of the St substrate 1 during bonding, it is possible to further improve the accuracy of the chip position in the lateral direction. Next, a fourth embodiment of the present invention is shown in FIG. In this example,
The shape of the recess for embedding the chip is formed in a vertical plane, and the material of the substrate 1 can be ceramics, metal, resin, etc. In this example, the recesses must be formed by machining or the like, and cannot be formed by anisotropic etching as in the first to third embodiments.
As a result, the accuracy is lower. Next, a fifth embodiment of the present invention is shown in FIG. In this example,
HF using single crystal Si substrate or polycrystalline St substrate? A recess for embedding the chip is formed by isotropic etching using S liquid or the like. Note that the positional accuracy of the chip can be ensured by the positional accuracy of a mounting device having a pattern recognition function.

Furthermore, in the fourth and fifth embodiments, since it is not necessary to form the recessed portions by anisotropic etching, it is possible to use a substrate that is cheaper than single crystal Si (for example, polycrystalline S11 metal ceramic, glass, resin, etc.).

Next, a sixth embodiment of the present invention is shown in FIG. The bottom of the recess does not need to be flat, and as in this example, the semiconductor chip 3
It may also have a triangular cross section to match the bottom shape.

〔Effect of the invention〕

As described above, according to the present invention, in a semiconductor device of the type in which a semiconductor chip is directly bonded to a substrate, the strength of the substrate after the chip is bonded is increased, and the bonding member existing between the substrate and the semiconductor chip is The filling volume of the flattening layer and the like can be made relatively small, which is advantageous in terms of reliability. Furthermore, workability also improves.

Furthermore, the positional accuracy between the semiconductor chip and the substrate can be improved, and the cost of managing positional accuracy can be significantly reduced.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the basic structure of the first embodiment of the present invention,
FIGS. 2(a) to (6) are sectional views for explaining the manufacturing process of the first embodiment, FIG. 3 is a sectional view showing details of the structure of the first embodiment, and FIG. 4 is a sectional view for explaining the manufacturing process of the first embodiment. 5 is a sectional view of the third embodiment, FIG. 6 is a sectional view of the fourth embodiment,
FIG. 7 is a sectional view of the fifth embodiment, and FIG. 8 is a sectional view of the sixth embodiment. DESCRIPTION OF SYMBOLS 1... Si substrate, 2... Taper hole, 3... Semiconductor chip, 4... Bonding member, 5... Flattening layer, 6, 8
...electrode, 7...wiring. 1:si@so4. Hakamaai Misaki Material 71 Layout 2: Teha/Hole 3: Semiconductor Ichi, F/5;

Claims (2)

[Claims] (1) A substrate in which a recessed portion having a bottom is formed; a semiconductor chip fixedly bonded within the recessed portion via a bonding material; 1. A semiconductor device comprising: a planarization layer formed for planarization. (2) the bottom of the recess is formed flat;
2. The semiconductor device according to claim 1, wherein the shape and size of the flat bottom portion and the shape and size of the bottom portion joined to the recessed portion of the semiconductor chip are substantially the same.